Searched refs:MCG_C6_VDIV0_MASK (Results 1 – 25 of 64) sorted by relevance
123
196 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); in SystemCoreClockUpdate()
195 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); in SystemCoreClockUpdate()
182 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); in SystemCoreClockUpdate()
191 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); in SystemCoreClockUpdate()
204 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); in SystemCoreClockUpdate()
190 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); in SystemCoreClockUpdate()
200 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); in SystemCoreClockUpdate()
209 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U); in SystemCoreClockUpdate()
85 #define MCG_C6_VDIV0_VAL ((MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)767 MCG->C6 = (MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv); in CLOCK_EnablePll0()
85 #define MCG_C6_VDIV0_VAL ((MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)820 MCG->C6 = (MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv); in CLOCK_EnablePll0()
67 #define MCG_C6_VDIV0_VAL ((uint8_t)(MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)994 MCG->C6 = (uint8_t)((MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv)); in CLOCK_EnablePll0()
67 #define MCG_C6_VDIV0_VAL ((uint8_t)(MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)952 MCG->C6 = (uint8_t)((MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv)); in CLOCK_EnablePll0()
67 #define MCG_C6_VDIV0_VAL ((uint8_t)(MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)1009 MCG->C6 = (uint8_t)((MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv)); in CLOCK_EnablePll0()
67 #define MCG_C6_VDIV0_VAL ((uint8_t)(MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)1014 MCG->C6 = (uint8_t)((MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv)); in CLOCK_EnablePll0()
67 #define MCG_C6_VDIV0_VAL ((uint8_t)(MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)1013 MCG->C6 = (uint8_t)((MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv)); in CLOCK_EnablePll0()
67 #define MCG_C6_VDIV0_VAL ((uint8_t)(MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)1024 MCG->C6 = (uint8_t)((MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv)); in CLOCK_EnablePll0()
67 #define MCG_C6_VDIV0_VAL ((uint8_t)(MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)1066 MCG->C6 = (uint8_t)((MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv)); in CLOCK_EnablePll0()
67 #define MCG_C6_VDIV0_VAL ((uint8_t)(MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)1045 MCG->C6 = (uint8_t)((MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv)); in CLOCK_EnablePll0()
67 #define MCG_C6_VDIV0_VAL ((uint8_t)(MCG->C6 & MCG_C6_VDIV0_MASK) >> MCG_C6_VDIV0_SHIFT)1057 MCG->C6 = (uint8_t)((MCG->C6 & ~MCG_C6_VDIV0_MASK) | MCG_C6_VDIV0(config->vdiv)); in CLOCK_EnablePll0()
