1 /*
2 ** ###################################################################
3 **     Processors:          MK22FN512CAP12
4 **                          MK22FN512VDC12
5 **                          MK22FN512VFX12
6 **                          MK22FN512VLH12
7 **                          MK22FN512VLL12
8 **                          MK22FN512VMP12
9 **
10 **     Compilers:           Freescale C/C++ for Embedded ARM
11 **                          GNU C Compiler
12 **                          IAR ANSI C/C++ Compiler for ARM
13 **                          Keil ARM C/C++ Compiler
14 **                          MCUXpresso Compiler
15 **
16 **     Reference manual:    K22P121M120SF7RM, Rev. 1, March 24, 2014
17 **     Version:             rev. 2.9, 2016-03-21
18 **     Build:               b181105
19 **
20 **     Abstract:
21 **         Provides a system configuration function and a global variable that
22 **         contains the system frequency. It configures the device and initializes
23 **         the oscillator (PLL) that is part of the microcontroller device.
24 **
25 **     Copyright 2016 Freescale Semiconductor, Inc.
26 **     Copyright 2016-2018 NXP
27 **     All rights reserved.
28 **
29 **     SPDX-License-Identifier: BSD-3-Clause
30 **
31 **     http:                 www.nxp.com
32 **     mail:                 support@nxp.com
33 **
34 **     Revisions:
35 **     - rev. 1.0 (2013-07-23)
36 **         Initial version.
37 **     - rev. 1.1 (2013-09-17)
38 **         RM rev. 0.4 update.
39 **     - rev. 2.0 (2013-10-29)
40 **         Register accessor macros added to the memory map.
41 **         Symbols for Processor Expert memory map compatibility added to the memory map.
42 **         Startup file for gcc has been updated according to CMSIS 3.2.
43 **         System initialization updated.
44 **     - rev. 2.1 (2013-10-30)
45 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
46 **     - rev. 2.2 (2013-12-20)
47 **         Update according to reference manual rev. 0.6,
48 **     - rev. 2.3 (2014-01-13)
49 **         Update according to reference manual rev. 0.61,
50 **     - rev. 2.4 (2014-02-10)
51 **         The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
52 **     - rev. 2.5 (2014-05-06)
53 **         Update according to reference manual rev. 1.0,
54 **         Update of system and startup files.
55 **         Module access macro module_BASES replaced by module_BASE_PTRS.
56 **     - rev. 2.6 (2014-08-28)
57 **         Update of system files - default clock configuration changed.
58 **         Update of startup files - possibility to override DefaultISR added.
59 **     - rev. 2.7 (2014-10-14)
60 **         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
61 **     - rev. 2.8 (2015-02-19)
62 **         Renamed interrupt vector LLW to LLWU.
63 **     - rev. 2.9 (2016-03-21)
64 **         Added MK22FN512VFX12 part.
65 **         GPIO - renamed port instances: PTx -> GPIOx.
66 **
67 ** ###################################################################
68 */
69 
70 /*!
71  * @file MK22F51212
72  * @version 2.9
73  * @date 2016-03-21
74  * @brief Device specific configuration file for MK22F51212 (implementation file)
75  *
76  * Provides a system configuration function and a global variable that contains
77  * the system frequency. It configures the device and initializes the oscillator
78  * (PLL) that is part of the microcontroller device.
79  */
80 
81 #include <stdint.h>
82 #include "fsl_device_registers.h"
83 
84 
85 
86 /* ----------------------------------------------------------------------------
87    -- Core clock
88    ---------------------------------------------------------------------------- */
89 
90 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
91 
92 /* ----------------------------------------------------------------------------
93    -- SystemInit()
94    ---------------------------------------------------------------------------- */
95 
SystemInit(void)96 void SystemInit (void) {
97 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
98   SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
99 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
100 
101 #if (DISABLE_WDOG)
102   /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
103   WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
104   /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
105   WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
106   /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
107   WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
108                  WDOG_STCTRLH_WAITEN_MASK |
109                  WDOG_STCTRLH_STOPEN_MASK |
110                  WDOG_STCTRLH_ALLOWUPDATE_MASK |
111                  WDOG_STCTRLH_CLKSRC_MASK |
112                  0x0100U;
113 #endif /* (DISABLE_WDOG) */
114 
115   SystemInitHook();
116 }
117 
118 /* ----------------------------------------------------------------------------
119    -- SystemCoreClockUpdate()
120    ---------------------------------------------------------------------------- */
121 
SystemCoreClockUpdate(void)122 void SystemCoreClockUpdate (void) {
123 
124   uint32_t MCGOUTClock;                /* Variable to store output clock frequency of the MCG module */
125   uint16_t Divider;
126   uint8_t tmpC7 = 0;
127 
128   if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
129     /* Output of FLL or PLL is selected */
130     if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
131       /* FLL is selected */
132       if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
133         /* External reference clock is selected */
134         switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
135         case 0x00U:
136           MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
137           break;
138         case 0x01U:
139           MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
140           break;
141         case 0x02U:
142         default:
143           MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
144           break;
145         }
146         tmpC7 = MCG->C7;
147         if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((tmpC7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
148           switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
149           case 0x38U:
150             Divider = 1536U;
151             break;
152           case 0x30U:
153             Divider = 1280U;
154             break;
155           default:
156             Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
157             break;
158           }
159         } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
160           Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
161         }
162         MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
163       } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
164         MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
165       } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
166       /* Select correct multiplier to calculate the MCG output clock  */
167       switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
168         case 0x00U:
169           MCGOUTClock *= 640U;
170           break;
171         case 0x20U:
172           MCGOUTClock *= 1280U;
173           break;
174         case 0x40U:
175           MCGOUTClock *= 1920U;
176           break;
177         case 0x60U:
178           MCGOUTClock *= 2560U;
179           break;
180         case 0x80U:
181           MCGOUTClock *= 732U;
182           break;
183         case 0xA0U:
184           MCGOUTClock *= 1464U;
185           break;
186         case 0xC0U:
187           MCGOUTClock *= 2197U;
188           break;
189         case 0xE0U:
190           MCGOUTClock *= 2929U;
191           break;
192         default:
193           MCGOUTClock *= 640U;
194           break;
195       }
196     } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
197       /* PLL is selected */
198       Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
199       MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
200       Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
201       MCGOUTClock *= Divider;          /* Calculate the MCG output clock */
202     } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
203   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
204     /* Internal reference clock is selected */
205     if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
206       MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
207     } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
208       Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
209       MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
210     } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
211   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
212     /* External reference clock is selected */
213     switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
214     case 0x00U:
215       MCGOUTClock = CPU_XTAL_CLK_HZ;   /* System oscillator drives MCG clock */
216       break;
217     case 0x01U:
218       MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
219       break;
220     case 0x02U:
221     default:
222       MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
223       break;
224     }
225   } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
226     /* Reserved value */
227     return;
228   } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
229   SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
230 }
231 
232 /* ----------------------------------------------------------------------------
233    -- SystemInitHook()
234    ---------------------------------------------------------------------------- */
235 
SystemInitHook(void)236 __attribute__ ((weak)) void SystemInitHook (void) {
237   /* Void implementation of the weak function. */
238 }
239