1 /*
2 ** ###################################################################
3 ** Processors: MK24FN1M0CAJ12
4 ** MK24FN1M0VDC12
5 ** MK24FN1M0VLL12
6 ** MK24FN1M0VLQ12
7 **
8 ** Compilers: Freescale C/C++ for Embedded ARM
9 ** GNU C Compiler
10 ** IAR ANSI C/C++ Compiler for ARM
11 ** Keil ARM C/C++ Compiler
12 ** MCUXpresso Compiler
13 **
14 ** Reference manual: K24P144M120SF5RM, Rev.2, January 2014
15 ** Version: rev. 2.8, 2016-03-21
16 ** Build: b181105
17 **
18 ** Abstract:
19 ** Provides a system configuration function and a global variable that
20 ** contains the system frequency. It configures the device and initializes
21 ** the oscillator (PLL) that is part of the microcontroller device.
22 **
23 ** Copyright 2016 Freescale Semiconductor, Inc.
24 ** Copyright 2016-2018 NXP
25 ** All rights reserved.
26 **
27 ** SPDX-License-Identifier: BSD-3-Clause
28 **
29 ** http: www.nxp.com
30 ** mail: support@nxp.com
31 **
32 ** Revisions:
33 ** - rev. 1.0 (2013-08-12)
34 ** Initial version.
35 ** - rev. 2.0 (2013-10-29)
36 ** Register accessor macros added to the memory map.
37 ** Symbols for Processor Expert memory map compatibility added to the memory map.
38 ** Startup file for gcc has been updated according to CMSIS 3.2.
39 ** System initialization updated.
40 ** MCG - registers updated.
41 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
42 ** - rev. 2.1 (2013-10-30)
43 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
44 ** - rev. 2.2 (2013-12-09)
45 ** DMA - EARS register removed.
46 ** AIPS0, AIPS1 - MPRA register updated.
47 ** - rev. 2.3 (2014-01-24)
48 ** Update according to reference manual rev. 2
49 ** ENET, MCG, MCM, SIM, USB - registers updated
50 ** - rev. 2.4 (2014-02-10)
51 ** The declaration of clock configurations has been moved to separate header file system_MK24F12.h
52 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
53 ** Module access macro module_BASES replaced by module_BASE_PTRS.
54 ** - rev. 2.5 (2014-08-28)
55 ** Update of system files - default clock configuration changed.
56 ** Update of startup files - possibility to override DefaultISR added.
57 ** - rev. 2.6 (2014-10-14)
58 ** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
59 ** - rev. 2.7 (2015-02-19)
60 ** Renamed interrupt vector LLW to LLWU.
61 ** - rev. 2.8 (2016-03-21)
62 ** Added MK24FN1M0CAJ12 part.
63 ** GPIO - renamed port instances: PTx -> GPIOx.
64 **
65 ** ###################################################################
66 */
67
68 /*!
69 * @file MK24F12
70 * @version 2.8
71 * @date 2016-03-21
72 * @brief Device specific configuration file for MK24F12 (implementation file)
73 *
74 * Provides a system configuration function and a global variable that contains
75 * the system frequency. It configures the device and initializes the oscillator
76 * (PLL) that is part of the microcontroller device.
77 */
78
79 #include <stdint.h>
80 #include "fsl_device_registers.h"
81
82
83
84 /* ----------------------------------------------------------------------------
85 -- Core clock
86 ---------------------------------------------------------------------------- */
87
88 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
89
90 /* ----------------------------------------------------------------------------
91 -- SystemInit()
92 ---------------------------------------------------------------------------- */
93
SystemInit(void)94 void SystemInit (void) {
95 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
96 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
97 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
98 #if (DISABLE_WDOG)
99 /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
100 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
101 /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
102 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
103 /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
104 WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
105 WDOG_STCTRLH_WAITEN_MASK |
106 WDOG_STCTRLH_STOPEN_MASK |
107 WDOG_STCTRLH_ALLOWUPDATE_MASK |
108 WDOG_STCTRLH_CLKSRC_MASK |
109 0x0100U;
110 #endif /* (DISABLE_WDOG) */
111
112 SystemInitHook();
113 }
114
115 /* ----------------------------------------------------------------------------
116 -- SystemCoreClockUpdate()
117 ---------------------------------------------------------------------------- */
118
SystemCoreClockUpdate(void)119 void SystemCoreClockUpdate (void) {
120 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
121 uint16_t Divider;
122 uint8_t tmpC7 = 0;
123
124 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
125 /* Output of FLL or PLL is selected */
126 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
127 /* FLL is selected */
128 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
129 /* External reference clock is selected */
130 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
131 case 0x00U:
132 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
133 break;
134 case 0x01U:
135 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
136 break;
137 case 0x02U:
138 default:
139 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
140 break;
141 }
142 tmpC7 = MCG->C7;
143 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((tmpC7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
144 switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
145 case 0x38U:
146 Divider = 1536U;
147 break;
148 case 0x30U:
149 Divider = 1280U;
150 break;
151 default:
152 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
153 break;
154 }
155 } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
156 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
157 }
158 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
159 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
160 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
161 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
162 /* Select correct multiplier to calculate the MCG output clock */
163 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
164 case 0x00U:
165 MCGOUTClock *= 640U;
166 break;
167 case 0x20U:
168 MCGOUTClock *= 1280U;
169 break;
170 case 0x40U:
171 MCGOUTClock *= 1920U;
172 break;
173 case 0x60U:
174 MCGOUTClock *= 2560U;
175 break;
176 case 0x80U:
177 MCGOUTClock *= 732U;
178 break;
179 case 0xA0U:
180 MCGOUTClock *= 1464U;
181 break;
182 case 0xC0U:
183 MCGOUTClock *= 2197U;
184 break;
185 case 0xE0U:
186 MCGOUTClock *= 2929U;
187 break;
188 default:
189 MCGOUTClock *= 640U;
190 break;
191 }
192 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
193 /* PLL is selected */
194 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
195 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
196 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
197 MCGOUTClock *= Divider; /* Calculate the MCG output clock */
198 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
199 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
200 /* Internal reference clock is selected */
201 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
202 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
203 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
204 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
205 MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
206 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
207 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
208 /* External reference clock is selected */
209 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
210 case 0x00U:
211 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
212 break;
213 case 0x01U:
214 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
215 break;
216 case 0x02U:
217 default:
218 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
219 break;
220 }
221 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
222 /* Reserved value */
223 return;
224 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
225 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
226 }
227
228 /* ----------------------------------------------------------------------------
229 -- SystemInitHook()
230 ---------------------------------------------------------------------------- */
231
SystemInitHook(void)232 __attribute__ ((weak)) void SystemInitHook (void) {
233 /* Void implementation of the weak function. */
234 }
235
