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Searched refs:CMP_SCR_CFF_SHIFT (Results 1 – 25 of 55) sorted by relevance

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/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKL25Z4/
DMKL25Z4.h664 #define CMP_SCR_CFF_SHIFT (1U) macro
665 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) …
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKL17Z644/
DMKL17Z644.h878 #define CMP_SCR_CFF_SHIFT (1U) macro
883 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) …
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKL27Z644/
DMKL27Z644.h887 #define CMP_SCR_CFF_SHIFT (1U) macro
892 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) …
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK02F12810/
DMK02F12810.h946 #define CMP_SCR_CFF_SHIFT (1U) macro
951 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) …
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV30F12810/
DMKV30F12810.h950 #define CMP_SCR_CFF_SHIFT (1U) macro
955 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) …
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV10Z7/
DMKV10Z7.h864 #define CMP_SCR_CFF_SHIFT (1U) macro
869 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) …
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV10Z1287/
DMKV10Z1287.h855 #define CMP_SCR_CFF_SHIFT (1U) macro
860 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) …
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV31F12810/
DMKV31F12810.h963 #define CMP_SCR_CFF_SHIFT (1U) macro
968 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) …
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKM14ZA5/
DMKM14ZA5.h3228 #define CMP_SCR_CFF_SHIFT (1U) macro
3233 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) …
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV11Z7/
DMKV11Z7.h1642 #define CMP_SCR_CFF_SHIFT (1U) macro
1647 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) …
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV31F25612/
DMKV31F25612.h965 #define CMP_SCR_CFF_SHIFT (1U) macro
970 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) …
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKV31F51212/
DMKV31F51212.h965 #define CMP_SCR_CFF_SHIFT (1U) macro
970 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) …
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/K32L2B11A/
DK32L2B11A.h910 #define CMP_SCR_CFF_SHIFT (1U) macro
915 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/K32L2B31A/
DK32L2B31A.h910 #define CMP_SCR_CFF_SHIFT (1U) macro
915 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/K32L2B21A/
DK32L2B21A.h910 #define CMP_SCR_CFF_SHIFT (1U) macro
915 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK22F12810/
DMK22F12810.h965 #define CMP_SCR_CFF_SHIFT (1U) macro
970 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) …
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK22F25612/
DMK22F25612.h971 #define CMP_SCR_CFF_SHIFT (1U) macro
976 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) …
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK22F51212/
DMK22F51212.h981 #define CMP_SCR_CFF_SHIFT (1U) macro
986 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) …
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKW22D5/
DMKW22D5.h1212 #define CMP_SCR_CFF_SHIFT (1U) macro
1213 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) …
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKW24D5/
DMKW24D5.h1212 #define CMP_SCR_CFF_SHIFT (1U) macro
1213 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) …
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/K32L2A31A/
DK32L2A31A.h1939 #define CMP_SCR_CFF_SHIFT (1U) macro
1944 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKM33ZA5/
DMKM33ZA5.h3230 #define CMP_SCR_CFF_SHIFT (1U) macro
3235 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) …
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/K32L2A41A/
DK32L2A41A.h1939 #define CMP_SCR_CFF_SHIFT (1U) macro
1944 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MKM34ZA5/
DMKM34ZA5.h3226 #define CMP_SCR_CFF_SHIFT (1U) macro
3231 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) …
/hal_nxp-3.6.0/mcux/mcux-sdk/devices/MK22F12/
DMK22F12.h4787 #define CMP_SCR_CFF_SHIFT (1U) macro
4792 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) …

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