1 /* 2 ** ################################################################### 3 ** Processors: MKM14Z128ACHH5 4 ** MKM14Z64ACHH5 5 ** 6 ** Compilers: Freescale C/C++ for Embedded ARM 7 ** GNU C Compiler 8 ** IAR ANSI C/C++ Compiler for ARM 9 ** Keil ARM C/C++ Compiler 10 ** MCUXpresso Compiler 11 ** 12 ** Reference manual: MKMxxZxxACxx5RM, Rev. 2, 10/2017 13 ** Version: rev. 1.0, 2014-07-22 14 ** Build: b210422 15 ** 16 ** Abstract: 17 ** CMSIS Peripheral Access Layer for MKM14ZA5 18 ** 19 ** Copyright 1997-2016 Freescale Semiconductor, Inc. 20 ** Copyright 2016-2021 NXP 21 ** All rights reserved. 22 ** 23 ** SPDX-License-Identifier: BSD-3-Clause 24 ** 25 ** http: www.nxp.com 26 ** mail: support@nxp.com 27 ** 28 ** Revisions: 29 ** - rev. 1.0 (2014-07-22) 30 ** Initial version. 31 ** 32 ** ################################################################### 33 */ 34 35 /*! 36 * @file MKM14ZA5.h 37 * @version 1.0 38 * @date 2014-07-22 39 * @brief CMSIS Peripheral Access Layer for MKM14ZA5 40 * 41 * CMSIS Peripheral Access Layer for MKM14ZA5 42 */ 43 44 #ifndef _MKM14ZA5_H_ 45 #define _MKM14ZA5_H_ /**< Symbol preventing repeated inclusion */ 46 47 /** Memory map major version (memory maps with equal major version number are 48 * compatible) */ 49 #define MCU_MEM_MAP_VERSION 0x0100U 50 /** Memory map minor version */ 51 #define MCU_MEM_MAP_VERSION_MINOR 0x0000U 52 53 54 /* ---------------------------------------------------------------------------- 55 -- Interrupt vector numbers 56 ---------------------------------------------------------------------------- */ 57 58 /*! 59 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers 60 * @{ 61 */ 62 63 /** Interrupt Number Definitions */ 64 #define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */ 65 66 typedef enum IRQn { 67 /* Auxiliary constants */ 68 NotAvail_IRQn = -128, /**< Not available device specific interrupt */ 69 70 /* Core interrupts */ 71 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ 72 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ 73 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ 74 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ 75 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ 76 77 /* Device specific interrupts */ 78 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete */ 79 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */ 80 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */ 81 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete */ 82 SPI0_IRQn = 4, /**< SPI0 ORed interrupt */ 83 SPI1_IRQn = 5, /**< SPI1 ORed interrupt */ 84 PMC_IRQn = 6, /**< Low-voltage detect, low-voltage warning */ 85 TMR0_IRQn = 7, /**< Quad Timer Channel 0 */ 86 TMR1_IRQn = 8, /**< Quad Timer Channel 1 */ 87 TMR2_IRQn = 9, /**< Quad Timer Channel 2 */ 88 TMR3_IRQn = 10, /**< Quad Timer Channel 3 */ 89 PIT0_PIT1_IRQn = 11, /**< PIT0/PIT1 ORed interrupt */ 90 LLWU_IRQn = 12, /**< Low Leakage Wakeup */ 91 FTFA_IRQn = 13, /**< Command complete and read collision */ 92 CMP0_CMP1_IRQn = 14, /**< CMP0/CMP1 ORed interrupt */ 93 Reserved31_IRQn = 15, /**< Reserved interrupt */ 94 ADC_IRQn = 16, /**< ADC interrupt */ 95 PTx_IRQn = 17, /**< Single interrupt vector for GPIOA,GPIOB,GPIOC,GPIOD,GPIOE,GPIOF,GPIOG,GPIOH,GPIOI */ 96 RNGA_IRQn = 18, /**< RNGA interrupt */ 97 UART0_UART1_IRQn = 19, /**< UART0/UART1 ORed interrupt */ 98 UART2_UART3_IRQn = 20, /**< UART2/UART3 ORed interrupt */ 99 AFE_CH0_IRQn = 21, /**< AFE Channel 0 */ 100 AFE_CH1_IRQn = 22, /**< AFE Channel 1 */ 101 AFE_CH2_IRQn = 23, /**< AFE Channel 2 */ 102 AFE_CH3_IRQn = 24, /**< AFE Channel 3 */ 103 RTC_IRQn = 25, /**< IRTC interrupt */ 104 I2C0_I2C1_IRQn = 26, /**< I2C0/I2C1 ORed interrupt */ 105 EWM_IRQn = 27, /**< External Watchdog Monitor */ 106 MCG_IRQn = 28, /**< MCG interrupt */ 107 WDOG_IRQn = 29, /**< WDOG ORed interrupt */ 108 LPTMR_IRQn = 30, /**< LPTMR interrupt */ 109 XBAR_IRQn = 31 /**< XBAR interrupt */ 110 } IRQn_Type; 111 112 /*! 113 * @} 114 */ /* end of group Interrupt_vector_numbers */ 115 116 117 /* ---------------------------------------------------------------------------- 118 -- Cortex M0 Core Configuration 119 ---------------------------------------------------------------------------- */ 120 121 /*! 122 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration 123 * @{ 124 */ 125 126 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */ 127 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ 128 #define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */ 129 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */ 130 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ 131 132 #include "core_cm0plus.h" /* Core Peripheral Access Layer */ 133 #include "system_MKM14ZA5.h" /* Device specific configuration file */ 134 135 /*! 136 * @} 137 */ /* end of group Cortex_Core_Configuration */ 138 139 140 /* ---------------------------------------------------------------------------- 141 -- Mapping Information 142 ---------------------------------------------------------------------------- */ 143 144 /*! 145 * @addtogroup Mapping_Information Mapping Information 146 * @{ 147 */ 148 149 /** Mapping Information */ 150 /*! 151 * @addtogroup edma_request 152 * @{ 153 */ 154 155 /******************************************************************************* 156 * Definitions 157 ******************************************************************************/ 158 159 /*! 160 * @brief Structure for the DMA hardware request 161 * 162 * Defines the structure for the DMA hardware request collections. The user can configure the 163 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index 164 * of the hardware request varies according to the to SoC. 165 */ 166 typedef enum _dma_request_source 167 { 168 kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled */ 169 kDmaRequestMux0SPI0Tx = 1|0x100U, /**< SPI0 Transmit (DMAMUX0) */ 170 kDmaRequestMux0SPI0Rx = 2|0x100U, /**< SPI0 Receive (DMAMUX0) */ 171 kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 Transmit (DMAMUX0) */ 172 kDmaRequestMux0UART0Rx = 4|0x100U, /**< UART0 Receive (DMAMUX0) */ 173 kDmaRequestMux0I2C0 = 5|0x100U, /**< I2C0 (DMAMUX0) */ 174 kDmaRequestMux0XBAR = 6|0x100U, /**< XBAR (DMAMUX0) */ 175 kDmaRequestMux0UART3Tx = 7|0x100U, /**< UART3 Transmit (DMAMUX0) */ 176 kDmaRequestMux0UART3Rx = 8|0x100U, /**< UART3 Receive (DMAMUX0) */ 177 kDmaRequestMux0AFEChannel0 = 9|0x100U, /**< AFE channel 0 (DMAMUX0) */ 178 kDmaRequestMux0TMR0 = 10|0x100U, /**< TMR0 (DMAMUX0) */ 179 kDmaRequestMux0TMR3 = 11|0x100U, /**< TMR3 (DMAMUX0) */ 180 kDmaRequestMux0AFEChannel2 = 12|0x100U, /**< AFE channel 2 (DMAMUX0) */ 181 kDmaRequestMux0ADC = 13|0x100U, /**< ADC (DMAMUX0) */ 182 kDmaRequestMux0CMP0 = 14|0x100U, /**< CMP0 (DMAMUX0) */ 183 kDmaRequestMux0PTE = 15|0x100U, /**< PTE (DMAMUX0) */ 184 kDmaRequestMux0PTA = 16|0x100U, /**< PTA (DMAMUX0) */ 185 kDmaRequestMux0AlwaysEnabledslot17 = 17|0x100U, /**< DMAMUX Always Enabled slot */ 186 kDmaRequestMux0AlwaysEnabledslot18 = 18|0x100U, /**< DMAMUX Always Enabled slot */ 187 kDmaRequestMux0Reserved19 = 19|0x100U, /**< Reserved19 */ 188 kDmaRequestMux0Reserved20 = 20|0x100U, /**< Reserved20 */ 189 kDmaRequestMux0Reserved21 = 21|0x100U, /**< Reserved21 */ 190 kDmaRequestMux0Reserved22 = 22|0x100U, /**< Reserved22 */ 191 kDmaRequestMux0Reserved23 = 23|0x100U, /**< Reserved23 */ 192 kDmaRequestMux0Reserved24 = 24|0x100U, /**< Reserved24 */ 193 kDmaRequestMux0Reserved25 = 25|0x100U, /**< Reserved25 */ 194 kDmaRequestMux0Reserved26 = 26|0x100U, /**< Reserved26 */ 195 kDmaRequestMux0Reserved27 = 27|0x100U, /**< Reserved27 */ 196 kDmaRequestMux0Reserved28 = 28|0x100U, /**< Reserved28 */ 197 kDmaRequestMux0Reserved29 = 29|0x100U, /**< Reserved29 */ 198 kDmaRequestMux0Reserved30 = 30|0x100U, /**< Reserved30 */ 199 kDmaRequestMux0Reserved31 = 31|0x100U, /**< Reserved31 */ 200 kDmaRequestMux0Reserved32 = 32|0x100U, /**< Reserved32 */ 201 kDmaRequestMux0Reserved33 = 33|0x100U, /**< Reserved33 */ 202 kDmaRequestMux0Reserved34 = 34|0x100U, /**< Reserved34 */ 203 kDmaRequestMux0Reserved35 = 35|0x100U, /**< Reserved35 */ 204 kDmaRequestMux0Reserved36 = 36|0x100U, /**< Reserved36 */ 205 kDmaRequestMux0Reserved37 = 37|0x100U, /**< Reserved37 */ 206 kDmaRequestMux0Reserved38 = 38|0x100U, /**< Reserved38 */ 207 kDmaRequestMux0Reserved39 = 39|0x100U, /**< Reserved39 */ 208 kDmaRequestMux0Reserved40 = 40|0x100U, /**< Reserved40 */ 209 kDmaRequestMux0Reserved41 = 41|0x100U, /**< Reserved41 */ 210 kDmaRequestMux0Reserved42 = 42|0x100U, /**< Reserved42 */ 211 kDmaRequestMux0Reserved43 = 43|0x100U, /**< Reserved43 */ 212 kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */ 213 kDmaRequestMux0Reserved45 = 45|0x100U, /**< Reserved45 */ 214 kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */ 215 kDmaRequestMux0Reserved47 = 47|0x100U, /**< Reserved47 */ 216 kDmaRequestMux0Reserved48 = 48|0x100U, /**< Reserved48 */ 217 kDmaRequestMux0Reserved49 = 49|0x100U, /**< Reserved49 */ 218 kDmaRequestMux0Reserved50 = 50|0x100U, /**< Reserved50 */ 219 kDmaRequestMux0Reserved51 = 51|0x100U, /**< Reserved51 */ 220 kDmaRequestMux0Reserved52 = 52|0x100U, /**< Reserved52 */ 221 kDmaRequestMux0Reserved53 = 53|0x100U, /**< Reserved53 */ 222 kDmaRequestMux0Reserved54 = 54|0x100U, /**< Reserved54 */ 223 kDmaRequestMux0Reserved55 = 55|0x100U, /**< Reserved55 */ 224 kDmaRequestMux0Reserved56 = 56|0x100U, /**< Reserved56 */ 225 kDmaRequestMux0Reserved57 = 57|0x100U, /**< Reserved57 */ 226 kDmaRequestMux0Reserved58 = 58|0x100U, /**< Reserved58 */ 227 kDmaRequestMux0Reserved59 = 59|0x100U, /**< Reserved59 */ 228 kDmaRequestMux0Reserved60 = 60|0x100U, /**< Reserved60 */ 229 kDmaRequestMux0Reserved61 = 61|0x100U, /**< Reserved61 */ 230 kDmaRequestMux0Reserved62 = 62|0x100U, /**< Reserved62 */ 231 kDmaRequestMux0Reserved63 = 63|0x100U, /**< Reserved63 */ 232 kDmaRequestMux1Disable = 0|0x200U, /**< DMAMUX TriggerDisabled */ 233 kDmaRequestMux1SPI0Tx = 1|0x200U, /**< SPI0 Transmit (DMAMUX1) */ 234 kDmaRequestMux1SPI0Rx = 2|0x200U, /**< SPI0 Receive (DMAMUX1) */ 235 kDmaRequestMux1UART1Tx = 3|0x200U, /**< UART1 Transmit (DMAMUX1) */ 236 kDmaRequestMux1UART1Rx = 4|0x200U, /**< UART1 Receive (DMAMUX1) */ 237 kDmaRequestMux1I2C0 = 5|0x200U, /**< I2C0 (DMAMUX1) */ 238 kDmaRequestMux1XBAR = 6|0x200U, /**< XBAR (DMAMUX1) */ 239 kDmaRequestMux1UART3Tx = 7|0x200U, /**< UART3 Transmit (DMAMUX1) */ 240 kDmaRequestMux1UART3Rx = 8|0x200U, /**< UART3 Receive (DMAMUX1) */ 241 kDmaRequestMux1AFEChannel0 = 9|0x200U, /**< AFE channel 0 (DMAMUX1) */ 242 kDmaRequestMux1TMR0 = 10|0x200U, /**< TMR0 (DMAMUX1) */ 243 kDmaRequestMux1TMR3 = 11|0x200U, /**< TMR3 (DMAMUX1) */ 244 kDmaRequestMux1AFEChannel2 = 12|0x200U, /**< AFE channel 2 (DMAMUX1) */ 245 kDmaRequestMux1PTE = 13|0x200U, /**< PTE (DMAMUX1) */ 246 kDmaRequestMux1CMP0 = 14|0x200U, /**< CMP0 (DMAMUX1) */ 247 kDmaRequestMux1PTF = 15|0x200U, /**< PTF (DMAMUX1) */ 248 kDmaRequestMux1PTB = 16|0x200U, /**< PTB (DMAMUX1) */ 249 kDmaRequestMux1AlwaysEnabledslot17 = 17|0x200U, /**< DMAMUX Always Enabled slot */ 250 kDmaRequestMux1AlwaysEnabledslot18 = 18|0x200U, /**< DMAMUX Always Enabled slot */ 251 kDmaRequestMux1Reserved19 = 19|0x200U, /**< Reserved19 */ 252 kDmaRequestMux1Reserved20 = 20|0x200U, /**< Reserved20 */ 253 kDmaRequestMux1Reserved21 = 21|0x200U, /**< Reserved21 */ 254 kDmaRequestMux1Reserved22 = 22|0x200U, /**< Reserved22 */ 255 kDmaRequestMux1Reserved23 = 23|0x200U, /**< Reserved23 */ 256 kDmaRequestMux1Reserved24 = 24|0x200U, /**< Reserved24 */ 257 kDmaRequestMux1Reserved25 = 25|0x200U, /**< Reserved25 */ 258 kDmaRequestMux1Reserved26 = 26|0x200U, /**< Reserved26 */ 259 kDmaRequestMux1Reserved27 = 27|0x200U, /**< Reserved27 */ 260 kDmaRequestMux1Reserved28 = 28|0x200U, /**< Reserved28 */ 261 kDmaRequestMux1Reserved29 = 29|0x200U, /**< Reserved29 */ 262 kDmaRequestMux1Reserved30 = 30|0x200U, /**< Reserved30 */ 263 kDmaRequestMux1Reserved31 = 31|0x200U, /**< Reserved31 */ 264 kDmaRequestMux1Reserved32 = 32|0x200U, /**< Reserved32 */ 265 kDmaRequestMux1Reserved33 = 33|0x200U, /**< Reserved33 */ 266 kDmaRequestMux1Reserved34 = 34|0x200U, /**< Reserved34 */ 267 kDmaRequestMux1Reserved35 = 35|0x200U, /**< Reserved35 */ 268 kDmaRequestMux1Reserved36 = 36|0x200U, /**< Reserved36 */ 269 kDmaRequestMux1Reserved37 = 37|0x200U, /**< Reserved37 */ 270 kDmaRequestMux1Reserved38 = 38|0x200U, /**< Reserved38 */ 271 kDmaRequestMux1Reserved39 = 39|0x200U, /**< Reserved39 */ 272 kDmaRequestMux1Reserved40 = 40|0x200U, /**< Reserved40 */ 273 kDmaRequestMux1Reserved41 = 41|0x200U, /**< Reserved41 */ 274 kDmaRequestMux1Reserved42 = 42|0x200U, /**< Reserved42 */ 275 kDmaRequestMux1Reserved43 = 43|0x200U, /**< Reserved43 */ 276 kDmaRequestMux1Reserved44 = 44|0x200U, /**< Reserved44 */ 277 kDmaRequestMux1Reserved45 = 45|0x200U, /**< Reserved45 */ 278 kDmaRequestMux1Reserved46 = 46|0x200U, /**< Reserved46 */ 279 kDmaRequestMux1Reserved47 = 47|0x200U, /**< Reserved47 */ 280 kDmaRequestMux1Reserved48 = 48|0x200U, /**< Reserved48 */ 281 kDmaRequestMux1Reserved49 = 49|0x200U, /**< Reserved49 */ 282 kDmaRequestMux1Reserved50 = 50|0x200U, /**< Reserved50 */ 283 kDmaRequestMux1Reserved51 = 51|0x200U, /**< Reserved51 */ 284 kDmaRequestMux1Reserved52 = 52|0x200U, /**< Reserved52 */ 285 kDmaRequestMux1Reserved53 = 53|0x200U, /**< Reserved53 */ 286 kDmaRequestMux1Reserved54 = 54|0x200U, /**< Reserved54 */ 287 kDmaRequestMux1Reserved55 = 55|0x200U, /**< Reserved55 */ 288 kDmaRequestMux1Reserved56 = 56|0x200U, /**< Reserved56 */ 289 kDmaRequestMux1Reserved57 = 57|0x200U, /**< Reserved57 */ 290 kDmaRequestMux1Reserved58 = 58|0x200U, /**< Reserved58 */ 291 kDmaRequestMux1Reserved59 = 59|0x200U, /**< Reserved59 */ 292 kDmaRequestMux1Reserved60 = 60|0x200U, /**< Reserved60 */ 293 kDmaRequestMux1Reserved61 = 61|0x200U, /**< Reserved61 */ 294 kDmaRequestMux1Reserved62 = 62|0x200U, /**< Reserved62 */ 295 kDmaRequestMux1Reserved63 = 63|0x200U, /**< Reserved63 */ 296 kDmaRequestMux2Disable = 0|0x300U, /**< DMAMUX TriggerDisabled */ 297 kDmaRequestMux2SPI1Tx = 1|0x300U, /**< SPI1 Transmit (DMAMUX2) */ 298 kDmaRequestMux2SPI1Rx = 2|0x300U, /**< SPI1 Receive (DMAMUX2) */ 299 kDmaRequestMux2UART1Tx = 3|0x300U, /**< UART1 Transmit (DMAMUX2) */ 300 kDmaRequestMux2UART1Rx = 4|0x300U, /**< UART1 Receive (DMAMUX2) */ 301 kDmaRequestMux2I2C1 = 5|0x300U, /**< I2C1 (DMAMUX2) */ 302 kDmaRequestMux2XBAR = 6|0x300U, /**< XBAR (DMAMUX2) */ 303 kDmaRequestMux2UART2Tx = 7|0x300U, /**< UART2 Transmit (DMAMUX2) */ 304 kDmaRequestMux2UART2Rx = 8|0x300U, /**< UART2 Receive (DMAMUX2) */ 305 kDmaRequestMux2AFEChannel1 = 9|0x300U, /**< AFE channel 1 (DMAMUX2) */ 306 kDmaRequestMux2TMR2 = 10|0x300U, /**< TMR2 (DMAMUX2) */ 307 kDmaRequestMux2TMR1 = 11|0x300U, /**< TMR1 (DMAMUX2) */ 308 kDmaRequestMux2AFEChannel3 = 12|0x300U, /**< AFE channel 3 (DMAMUX2) */ 309 kDmaRequestMux2PTI = 13|0x300U, /**< PTI (DMAMUX2) */ 310 kDmaRequestMux2CMP1 = 14|0x300U, /**< CMP1 (DMAMUX2) */ 311 kDmaRequestMux2PTG = 15|0x300U, /**< PTG (DMAMUX2) */ 312 kDmaRequestMux2PTC = 16|0x300U, /**< PTC (DMAMUX2) */ 313 kDmaRequestMux2AlwaysEnabledslot17 = 17|0x300U, /**< DMAMUX Always Enabled slot */ 314 kDmaRequestMux2AlwaysEnabledslot18 = 18|0x300U, /**< DMAMUX Always Enabled slot */ 315 kDmaRequestMux2Reserved19 = 19|0x300U, /**< Reserved19 */ 316 kDmaRequestMux2Reserved20 = 20|0x300U, /**< Reserved20 */ 317 kDmaRequestMux2Reserved21 = 21|0x300U, /**< Reserved21 */ 318 kDmaRequestMux2Reserved22 = 22|0x300U, /**< Reserved22 */ 319 kDmaRequestMux2Reserved23 = 23|0x300U, /**< Reserved23 */ 320 kDmaRequestMux2Reserved24 = 24|0x300U, /**< Reserved24 */ 321 kDmaRequestMux2Reserved25 = 25|0x300U, /**< Reserved25 */ 322 kDmaRequestMux2Reserved26 = 26|0x300U, /**< Reserved26 */ 323 kDmaRequestMux2Reserved27 = 27|0x300U, /**< Reserved27 */ 324 kDmaRequestMux2Reserved28 = 28|0x300U, /**< Reserved28 */ 325 kDmaRequestMux2Reserved29 = 29|0x300U, /**< Reserved29 */ 326 kDmaRequestMux2Reserved30 = 30|0x300U, /**< Reserved30 */ 327 kDmaRequestMux2Reserved31 = 31|0x300U, /**< Reserved31 */ 328 kDmaRequestMux2Reserved32 = 32|0x300U, /**< Reserved32 */ 329 kDmaRequestMux2Reserved33 = 33|0x300U, /**< Reserved33 */ 330 kDmaRequestMux2Reserved34 = 34|0x300U, /**< Reserved34 */ 331 kDmaRequestMux2Reserved35 = 35|0x300U, /**< Reserved35 */ 332 kDmaRequestMux2Reserved36 = 36|0x300U, /**< Reserved36 */ 333 kDmaRequestMux2Reserved37 = 37|0x300U, /**< Reserved37 */ 334 kDmaRequestMux2Reserved38 = 38|0x300U, /**< Reserved38 */ 335 kDmaRequestMux2Reserved39 = 39|0x300U, /**< Reserved39 */ 336 kDmaRequestMux2Reserved40 = 40|0x300U, /**< Reserved40 */ 337 kDmaRequestMux2Reserved41 = 41|0x300U, /**< Reserved41 */ 338 kDmaRequestMux2Reserved42 = 42|0x300U, /**< Reserved42 */ 339 kDmaRequestMux2Reserved43 = 43|0x300U, /**< Reserved43 */ 340 kDmaRequestMux2Reserved44 = 44|0x300U, /**< Reserved44 */ 341 kDmaRequestMux2Reserved45 = 45|0x300U, /**< Reserved45 */ 342 kDmaRequestMux2Reserved46 = 46|0x300U, /**< Reserved46 */ 343 kDmaRequestMux2Reserved47 = 47|0x300U, /**< Reserved47 */ 344 kDmaRequestMux2Reserved48 = 48|0x300U, /**< Reserved48 */ 345 kDmaRequestMux2Reserved49 = 49|0x300U, /**< Reserved49 */ 346 kDmaRequestMux2Reserved50 = 50|0x300U, /**< Reserved50 */ 347 kDmaRequestMux2Reserved51 = 51|0x300U, /**< Reserved51 */ 348 kDmaRequestMux2Reserved52 = 52|0x300U, /**< Reserved52 */ 349 kDmaRequestMux2Reserved53 = 53|0x300U, /**< Reserved53 */ 350 kDmaRequestMux2Reserved54 = 54|0x300U, /**< Reserved54 */ 351 kDmaRequestMux2Reserved55 = 55|0x300U, /**< Reserved55 */ 352 kDmaRequestMux2Reserved56 = 56|0x300U, /**< Reserved56 */ 353 kDmaRequestMux2Reserved57 = 57|0x300U, /**< Reserved57 */ 354 kDmaRequestMux2Reserved58 = 58|0x300U, /**< Reserved58 */ 355 kDmaRequestMux2Reserved59 = 59|0x300U, /**< Reserved59 */ 356 kDmaRequestMux2Reserved60 = 60|0x300U, /**< Reserved60 */ 357 kDmaRequestMux2Reserved61 = 61|0x300U, /**< Reserved61 */ 358 kDmaRequestMux2Reserved62 = 62|0x300U, /**< Reserved62 */ 359 kDmaRequestMux2Reserved63 = 63|0x300U, /**< Reserved63 */ 360 kDmaRequestMux3Disable = 0|0x400U, /**< DMAMUX TriggerDisabled */ 361 kDmaRequestMux3SPI1Tx = 1|0x400U, /**< SPI1 Transmit (DMAMUX3) */ 362 kDmaRequestMux3SPI1Rx = 2|0x400U, /**< SPI1 Receive (DMAMUX3) */ 363 kDmaRequestMux3UART0Tx = 3|0x400U, /**< UART0 Transmit (DMAMUX3) */ 364 kDmaRequestMux3UART0Rx = 4|0x400U, /**< UART0 Receive (DMAMUX3) */ 365 kDmaRequestMux3I2C1 = 5|0x400U, /**< I2C1 (DMAMUX3) */ 366 kDmaRequestMux3XBAR = 6|0x400U, /**< XBAR (DMAMUX3) */ 367 kDmaRequestMux3UART2Tx = 7|0x400U, /**< UART2 Transmit (DMAMUX3) */ 368 kDmaRequestMux3UART2Rx = 8|0x400U, /**< UART2 Receive (DMAMUX3) */ 369 kDmaRequestMux3AFEChannel1 = 9|0x400U, /**< AFE channel 1 (DMAMUX3) */ 370 kDmaRequestMux3TMR2 = 10|0x400U, /**< TMR2 (DMAMUX3) */ 371 kDmaRequestMux3TMR1 = 11|0x400U, /**< TMR1 (DMAMUX3) */ 372 kDmaRequestMux3AFEChannel3 = 12|0x400U, /**< AFE channel 3 (DMAMUX3) */ 373 kDmaRequestMux3ADC = 13|0x400U, /**< ADC (DMAMUX3) */ 374 kDmaRequestMux3CMP1 = 14|0x400U, /**< CMP1 (DMAMUX3) */ 375 kDmaRequestMux3PTH = 15|0x400U, /**< PTH (DMAMUX3) */ 376 kDmaRequestMux3PTD = 16|0x400U, /**< PTD (DMAMUX3) */ 377 kDmaRequestMux3AlwaysEnabledslot17 = 17|0x400U, /**< DMAMUX Always Enabled slot */ 378 kDmaRequestMux3AlwaysEnabledslot18 = 18|0x400U, /**< DMAMUX Always Enabled slot */ 379 kDmaRequestMux3Reserved19 = 19|0x400U, /**< Reserved19 */ 380 kDmaRequestMux3Reserved20 = 20|0x400U, /**< Reserved20 */ 381 kDmaRequestMux3Reserved21 = 21|0x400U, /**< Reserved21 */ 382 kDmaRequestMux3Reserved22 = 22|0x400U, /**< Reserved22 */ 383 kDmaRequestMux3Reserved23 = 23|0x400U, /**< Reserved23 */ 384 kDmaRequestMux3Reserved24 = 24|0x400U, /**< Reserved24 */ 385 kDmaRequestMux3Reserved25 = 25|0x400U, /**< Reserved25 */ 386 kDmaRequestMux3Reserved26 = 26|0x400U, /**< Reserved26 */ 387 kDmaRequestMux3Reserved27 = 27|0x400U, /**< Reserved27 */ 388 kDmaRequestMux3Reserved28 = 28|0x400U, /**< Reserved28 */ 389 kDmaRequestMux3Reserved29 = 29|0x400U, /**< Reserved29 */ 390 kDmaRequestMux3Reserved30 = 30|0x400U, /**< Reserved30 */ 391 kDmaRequestMux3Reserved31 = 31|0x400U, /**< Reserved31 */ 392 kDmaRequestMux3Reserved32 = 32|0x400U, /**< Reserved32 */ 393 kDmaRequestMux3Reserved33 = 33|0x400U, /**< Reserved33 */ 394 kDmaRequestMux3Reserved34 = 34|0x400U, /**< Reserved34 */ 395 kDmaRequestMux3Reserved35 = 35|0x400U, /**< Reserved35 */ 396 kDmaRequestMux3Reserved36 = 36|0x400U, /**< Reserved36 */ 397 kDmaRequestMux3Reserved37 = 37|0x400U, /**< Reserved37 */ 398 kDmaRequestMux3Reserved38 = 38|0x400U, /**< Reserved38 */ 399 kDmaRequestMux3Reserved39 = 39|0x400U, /**< Reserved39 */ 400 kDmaRequestMux3Reserved40 = 40|0x400U, /**< Reserved40 */ 401 kDmaRequestMux3Reserved41 = 41|0x400U, /**< Reserved41 */ 402 kDmaRequestMux3Reserved42 = 42|0x400U, /**< Reserved42 */ 403 kDmaRequestMux3Reserved43 = 43|0x400U, /**< Reserved43 */ 404 kDmaRequestMux3Reserved44 = 44|0x400U, /**< Reserved44 */ 405 kDmaRequestMux3Reserved45 = 45|0x400U, /**< Reserved45 */ 406 kDmaRequestMux3Reserved46 = 46|0x400U, /**< Reserved46 */ 407 kDmaRequestMux3Reserved47 = 47|0x400U, /**< Reserved47 */ 408 kDmaRequestMux3Reserved48 = 48|0x400U, /**< Reserved48 */ 409 kDmaRequestMux3Reserved49 = 49|0x400U, /**< Reserved49 */ 410 kDmaRequestMux3Reserved50 = 50|0x400U, /**< Reserved50 */ 411 kDmaRequestMux3Reserved51 = 51|0x400U, /**< Reserved51 */ 412 kDmaRequestMux3Reserved52 = 52|0x400U, /**< Reserved52 */ 413 kDmaRequestMux3Reserved53 = 53|0x400U, /**< Reserved53 */ 414 kDmaRequestMux3Reserved54 = 54|0x400U, /**< Reserved54 */ 415 kDmaRequestMux3Reserved55 = 55|0x400U, /**< Reserved55 */ 416 kDmaRequestMux3Reserved56 = 56|0x400U, /**< Reserved56 */ 417 kDmaRequestMux3Reserved57 = 57|0x400U, /**< Reserved57 */ 418 kDmaRequestMux3Reserved58 = 58|0x400U, /**< Reserved58 */ 419 kDmaRequestMux3Reserved59 = 59|0x400U, /**< Reserved59 */ 420 kDmaRequestMux3Reserved60 = 60|0x400U, /**< Reserved60 */ 421 kDmaRequestMux3Reserved61 = 61|0x400U, /**< Reserved61 */ 422 kDmaRequestMux3Reserved62 = 62|0x400U, /**< Reserved62 */ 423 kDmaRequestMux3Reserved63 = 63|0x400U, /**< Reserved63 */ 424 } dma_request_source_t; 425 426 /* @} */ 427 428 typedef enum _xbar_input_signal 429 { 430 kXBAR_InputVdd = 0|0x100U, /**< Logic 1 (VDD) output assigned to XBAR_IN0 input. */ 431 kXBAR_InputVss = 1|0x100U, /**< Logic 0 (VSS) output assigned to XBAR_IN1 input. */ 432 kXBAR_InputAfeClock = 2|0x100U, /**< AFE modulator clock output output assigned to XBAR_IN2 input. */ 433 kXBAR_InputAfeModDataOutput = 3|0x100U, /**< AFE modulator data output output assigned to XBAR_IN3 input. */ 434 kXBAR_InputLptmrOutput = 4|0x100U, /**< LPTimer Output output assigned to XBAR_IN4 input. */ 435 kXBAR_InputClockOutput = 5|0x100U, /**< Clock Output output assigned to XBAR_IN5 input. */ 436 kXBAR_InputTmrCh0Output = 6|0x100U, /**< Quad Timer channel 0 output output assigned to XBAR_IN6 input. */ 437 kXBAR_InputTmrCh1Output = 7|0x100U, /**< Quad Timer channel 1 output output assigned to XBAR_IN7 input. */ 438 kXBAR_InputTmrCh2Output = 8|0x100U, /**< Quad Timer channel 2 output output assigned to XBAR_IN8 input. */ 439 kXBAR_InputTmrCh3Output = 9|0x100U, /**< Quad Timer channel 3 output output assigned to XBAR_IN9 input. */ 440 kXBAR_InputRtcClockOutput = 10|0x100U, /**< iRTC Clock Output output assigned to XBAR_IN10 input. */ 441 kXBAR_InputCmp0Output = 11|0x100U, /**< CMP0 Output output assigned to XBAR_IN11 input. */ 442 kXBAR_InputCmp1Output = 12|0x100U, /**< CMP1 Output output assigned to XBAR_IN12 input. */ 443 kXBAR_InputRtcAlarmOutput = 13|0x100U, /**< iRTC Alarm Output output assigned to XBAR_IN13 input. */ 444 kXBAR_InputUartTxOutput = 14|0x100U, /**< UART TX Output (after modulation) output assigned to XBAR_IN14 input. */ 445 kXBAR_InputEwmOutput = 15|0x100U, /**< EWM Output (EWM_OUT) output assigned to XBAR_IN15 input. */ 446 kXBAR_InputPitOut = 16|0x100U, /**< PIT Output output assigned to XBAR_IN16 input. */ 447 kXBAR_InputXbarIn0 = 17|0x100U, /**< XBAR Input pin 0 output assigned to XBAR_IN17 input. */ 448 kXBAR_InputXbarIn1 = 18|0x100U, /**< XBAR Input pin 1 output assigned to XBAR_IN18 input. */ 449 kXBAR_InputXbarIn2 = 19|0x100U, /**< XBAR Input pin 2 output assigned to XBAR_IN19 input. */ 450 kXBAR_InputXbarIn3 = 20|0x100U, /**< XBAR Input pin 3 output assigned to XBAR_IN20 input. */ 451 kXBAR_InputXbarIn4 = 21|0x100U, /**< XBAR Input pin 4 output assigned to XBAR_IN21 input. */ 452 kXBAR_InputXbarIn5 = 22|0x100U, /**< XBAR Input pin 5 output assigned to XBAR_IN22 input. */ 453 kXBAR_InputXbarIn6 = 23|0x100U, /**< XBAR Input pin 6 output assigned to XBAR_IN23 input. */ 454 kXBAR_InputXbarIn7 = 24|0x100U, /**< XBAR Input pin 7 output assigned to XBAR_IN24 input. */ 455 kXBAR_InputXbarIn8 = 25|0x100U, /**< XBAR Input pin 8 output assigned to XBAR_IN25 input. */ 456 kXBAR_InputAdcCocoFlag = 26|0x100U, /**< ORed conversion complete flag for all SAR ADC channels output assigned to XBAR_IN26 input. */ 457 kXBAR_InputAfeAllCocFlag = 27|0x100U, /**< ORed conversion complete flag for all AFE channels output assigned to XBAR_IN27 input. */ 458 kXBAR_InputAfeCh0CocFlag = 28|0x100U, /**< AFE Channel 0 conversion complete output assigned to XBAR_IN28 input. */ 459 kXBAR_InputAfeCh1CocFlag = 29|0x100U, /**< AFE Channel 1 conversion complete output assigned to XBAR_IN29 input. */ 460 kXBAR_InputAfeCh2CocFlag = 30|0x100U, /**< AFE Channel 2 conversion complete output assigned to XBAR_IN30 input. */ 461 kXBAR_InputAfeCh3CocFlag = 31|0x100U, /**< AFE Channel 3 conversion complete output assigned to XBAR_IN31 input. */ 462 kXBAR_InputDmaDoneSignal = 32|0x100U, /**< DMA Done Signal output assigned to XBAR_IN32 input. */ 463 } xbar_input_signal_t; 464 465 typedef enum _xbar_output_signal 466 { 467 kXBAR_OutputXbDmaInt = 0|0x100U, /**< XBAR_OUT0 output assigned to XBAR DMA request or Interrupt */ 468 kXBAR_OutputAfeCh0ExmodData = 1|0x100U, /**< XBAR_OUT1 output assigned to External modulator data input for AFE Channel 0 */ 469 kXBAR_OutputAfeCh1ExmodData = 2|0x100U, /**< XBAR_OUT2 output assigned to External modulator data input for AFE Channel 1 */ 470 kXBAR_OutputAfeCh2ExmodData = 3|0x100U, /**< XBAR_OUT3 output assigned to External modulator data input for AFE Channel 2 */ 471 kXBAR_OutputAfeCh3ExmodData = 4|0x100U, /**< XBAR_OUT4 output assigned to External modulator data input for AFE Channel 3 */ 472 kXBAR_OutputTmrCh0SecInput = 5|0x100U, /**< XBAR_OUT5 output assigned to Quad Timer channel 0 secondary input */ 473 kXBAR_OutputTmrCh1SecInput = 6|0x100U, /**< XBAR_OUT6 output assigned to Quad Timer channel 1 secondary input */ 474 kXBAR_OutputTmrCh2SecInput = 7|0x100U, /**< XBAR_OUT7 output assigned to Quad Timer channel 2 secondary input */ 475 kXBAR_OutputTmrCh3SecInput = 8|0x100U, /**< XBAR_OUT8 output assigned to Quad Timer channel 3 secondary input */ 476 kXBAR_OutputTmrClockInput1 = 9|0x100U, /**< XBAR_OUT9 output assigned to Quad Timer primary clock input 1 */ 477 kXBAR_OutputTmrClockInput2 = 10|0x100U, /**< XBAR_OUT10 output assigned to Quad Timer primary clock input 2 */ 478 kXBAR_OutputCmp0SampleWinInput = 11|0x100U, /**< XBAR_OUT11 output assigned to CMP0 Sample Window input */ 479 kXBAR_OutputCmp1SampleWinInput = 12|0x100U, /**< XBAR_OUT12 output assigned to CMP1 Sample Window input */ 480 kXBAR_OutputUartRxInput = 13|0x100U, /**< XBAR_OUT13 output assigned to UART Rx IrDA Input */ 481 kXBAR_OutputUartTxModCarrier = 14|0x100U, /**< XBAR_OUT14 output assigned to SIM UART Tx IrDA Modulator Carrier Input */ 482 kXBAR_OutputAdcTrgA = 15|0x100U, /**< XBAR_OUT15 output assigned to SAR ADC trigger select A pulse */ 483 kXBAR_OutputAdcTrgB = 16|0x100U, /**< XBAR_OUT16 output assigned to SAR ADC trigger select B pulse */ 484 kXBAR_OutputXbOut0 = 17|0x100U, /**< XBAR_OUT17 output assigned to XBAR Output pin 0 */ 485 kXBAR_OutputXbOut1 = 18|0x100U, /**< XBAR_OUT18 output assigned to XBAR Output pin 1 */ 486 kXBAR_OutputXbOut2 = 19|0x100U, /**< XBAR_OUT19 output assigned to XBAR Output pin 2 */ 487 kXBAR_OutputXbOut3 = 20|0x100U, /**< XBAR_OUT20 output assigned to XBAR Output pin 3 */ 488 kXBAR_OutputXbOut4 = 21|0x100U, /**< XBAR_OUT21 output assigned to XBAR Output pin 4 */ 489 kXBAR_OutputXbOut5 = 22|0x100U, /**< XBAR_OUT22 output assigned to XBAR Output pin 5 */ 490 kXBAR_OutputXbOut6 = 23|0x100U, /**< XBAR_OUT23 output assigned to XBAR Output pin 6 */ 491 kXBAR_OutputXbOut7 = 24|0x100U, /**< XBAR_OUT24 output assigned to XBAR Output pin 7 */ 492 kXBAR_OutputXbOut8 = 25|0x100U, /**< XBAR_OUT25 output assigned to XBAR Output pin 8 */ 493 kXBAR_OutputAdcTrgC = 26|0x100U, /**< XBAR_OUT26 output assigned to SAR ADC trigger select C pulse */ 494 kXBAR_OutputAdcTrgD = 27|0x100U, /**< XBAR_OUT27 output assigned to SAR ADC trigger select D pulse */ 495 kXBAR_OutputAfeCh0Trg = 28|0x100U, /**< XBAR_OUT28 output assigned to AFE Channel 0 Trigger */ 496 kXBAR_OutputAfeCh1Trg = 29|0x100U, /**< XBAR_OUT29 output assigned to AFE Channel 1 Trigger */ 497 kXBAR_OutputAfeCh2Trg = 30|0x100U, /**< XBAR_OUT30 output assigned to AFE Channel 2 Trigger */ 498 kXBAR_OutputAfeCh3Trg = 31|0x100U, /**< XBAR_OUT31 output assigned to AFE Channel 3 Trigger */ 499 kXBAR_OutputEwmIn = 32|0x100U, /**< XBAR_OUT32 output assigned to EWM input (EWM_IN) */ 500 } xbar_output_signal_t; 501 502 503 /*! 504 * @} 505 */ /* end of group Mapping_Information */ 506 507 508 /* ---------------------------------------------------------------------------- 509 -- Device Peripheral Access Layer 510 ---------------------------------------------------------------------------- */ 511 512 /*! 513 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer 514 * @{ 515 */ 516 517 518 /* 519 ** Start of section using anonymous unions 520 */ 521 522 #if defined(__ARMCC_VERSION) 523 #if (__ARMCC_VERSION >= 6010050) 524 #pragma clang diagnostic push 525 #else 526 #pragma push 527 #pragma anon_unions 528 #endif 529 #elif defined(__CWCC__) 530 #pragma push 531 #pragma cpp_extensions on 532 #elif defined(__GNUC__) 533 /* anonymous unions are enabled by default */ 534 #elif defined(__IAR_SYSTEMS_ICC__) 535 #pragma language=extended 536 #else 537 #error Not supported compiler type 538 #endif 539 540 /* ---------------------------------------------------------------------------- 541 -- ADC Peripheral Access Layer 542 ---------------------------------------------------------------------------- */ 543 544 /*! 545 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer 546 * @{ 547 */ 548 549 /** ADC - Register Layout Typedef */ 550 typedef struct { 551 __IO uint32_t SC1[4]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ 552 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x10 */ 553 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0x14 */ 554 __I uint32_t R[4]; /**< ADC Data Result Register, array offset: 0x18, array step: 0x4 */ 555 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x28 */ 556 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x2C */ 557 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x30 */ 558 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x34 */ 559 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x38 */ 560 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x3C */ 561 uint8_t RESERVED_0[4]; 562 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ 563 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ 564 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ 565 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x50 */ 566 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x54 */ 567 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x58 */ 568 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x5C */ 569 } ADC_Type; 570 571 /* ---------------------------------------------------------------------------- 572 -- ADC Register Masks 573 ---------------------------------------------------------------------------- */ 574 575 /*! 576 * @addtogroup ADC_Register_Masks ADC Register Masks 577 * @{ 578 */ 579 580 /*! @name SC1 - ADC Status and Control Registers 1 */ 581 /*! @{ */ 582 583 #define ADC_SC1_ADCH_MASK (0x1FU) 584 #define ADC_SC1_ADCH_SHIFT (0U) 585 /*! ADCH - Input channel select 586 * 0b00000..AD0 is selected as input. 587 * 0b00001..AD1 is selected as input. 588 * 0b00010..AD2 is selected as input. 589 * 0b00011..AD3 is selected as input. 590 * 0b00100..AD4 is selected as input. 591 * 0b00101..AD5 is selected as input. 592 * 0b00110..AD6 is selected as input. 593 * 0b00111..AD7 is selected as input. 594 * 0b01000..AD8 is selected as input. 595 * 0b01001..AD9 is selected as input. 596 * 0b01010..AD10 is selected as input. 597 * 0b01011..AD11 is selected as input. 598 * 0b01100..AD12 is selected as input. 599 * 0b01101..AD13 is selected as input. 600 * 0b01110..AD14 is selected as input. 601 * 0b01111..AD15 is selected as input. 602 * 0b10000..AD16 is selected as input. 603 * 0b10001..AD17 is selected as input. 604 * 0b10010..AD18 is selected as input. 605 * 0b10011..AD19 is selected as input. 606 * 0b10100..AD20 is selected as input. 607 * 0b10101..AD21 is selected as input. 608 * 0b10110..AD22 is selected as input. 609 * 0b10111..AD23 is selected as input. 610 * 0b11000..Reserved. 611 * 0b11001..Reserved. 612 * 0b11010..Temp Sensor (single-ended) is selected as input. 613 * 0b11011..Bandgap (single-ended) is selected as input. 614 * 0b11100..Reserved. 615 * 0b11101..VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL]. 616 * 0b11110..VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL]. 617 * 0b11111..Module is disabled. 618 */ 619 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK) 620 621 #define ADC_SC1_AIEN_MASK (0x40U) 622 #define ADC_SC1_AIEN_SHIFT (6U) 623 /*! AIEN - Interrupt Enable 624 * 0b0..Conversion complete interrupt is disabled. 625 * 0b1..Conversion complete interrupt is enabled. 626 */ 627 #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK) 628 629 #define ADC_SC1_COCO_MASK (0x80U) 630 #define ADC_SC1_COCO_SHIFT (7U) 631 /*! COCO - Conversion Complete Flag 632 * 0b0..Conversion is not completed. 633 * 0b1..Conversion is completed. 634 */ 635 #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK) 636 /*! @} */ 637 638 /* The count of ADC_SC1 */ 639 #define ADC_SC1_COUNT (4U) 640 641 /*! @name CFG1 - ADC Configuration Register 1 */ 642 /*! @{ */ 643 644 #define ADC_CFG1_ADICLK_MASK (0x3U) 645 #define ADC_CFG1_ADICLK_SHIFT (0U) 646 /*! ADICLK - Input Clock Select 647 * 0b00..Bus clock 648 * 0b01..Bus clock divided by 2(BUSCLK/2) 649 * 0b10..Alternate clock (ALTCLK) 650 * 0b11..Asynchronous clock (ADACK) 651 */ 652 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK) 653 654 #define ADC_CFG1_MODE_MASK (0xCU) 655 #define ADC_CFG1_MODE_SHIFT (2U) 656 /*! MODE - Conversion mode selection 657 * 0b00..It is single-ended 8-bit conversion. 658 * 0b01..It is single-ended 12-bit conversion . 659 * 0b10..It is single-ended 10-bit conversion. 660 * 0b11..It is single-ended 16-bit conversion.. 661 */ 662 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK) 663 664 #define ADC_CFG1_ADLSMP_MASK (0x10U) 665 #define ADC_CFG1_ADLSMP_SHIFT (4U) 666 /*! ADLSMP - Sample Time Configuration 667 * 0b0..Short sample time. 668 * 0b1..Long sample time. 669 */ 670 #define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK) 671 672 #define ADC_CFG1_ADIV_MASK (0x60U) 673 #define ADC_CFG1_ADIV_SHIFT (5U) 674 /*! ADIV - Clock Divide Select 675 * 0b00..The divide ratio is 1 and the clock rate is input clock. 676 * 0b01..The divide ratio is 2 and the clock rate is (input clock)/2. 677 * 0b10..The divide ratio is 4 and the clock rate is (input clock)/4. 678 * 0b11..The divide ratio is 8 and the clock rate is (input clock)/8. 679 */ 680 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK) 681 682 #define ADC_CFG1_ADLPC_MASK (0x80U) 683 #define ADC_CFG1_ADLPC_SHIFT (7U) 684 /*! ADLPC - Low-Power Configuration 685 * 0b0..Normal power configuration. 686 * 0b1..Low-power configuration. The power is reduced at the expense of maximum clock speed. 687 */ 688 #define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK) 689 /*! @} */ 690 691 /*! @name CFG2 - ADC Configuration Register 2 */ 692 /*! @{ */ 693 694 #define ADC_CFG2_ADLSTS_MASK (0x3U) 695 #define ADC_CFG2_ADLSTS_SHIFT (0U) 696 /*! ADLSTS - Long Sample Time Select 697 * 0b00..Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total. 698 * 0b01..12 extra ADCK cycles; 16 ADCK cycles total sample time. 699 * 0b10..6 extra ADCK cycles; 10 ADCK cycles total sample time. 700 * 0b11..2 extra ADCK cycles; 6 ADCK cycles total sample time. 701 */ 702 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK) 703 704 #define ADC_CFG2_ADHSC_MASK (0x4U) 705 #define ADC_CFG2_ADHSC_SHIFT (2U) 706 /*! ADHSC - High-Speed Configuration 707 * 0b0..Normal conversion sequence selected. 708 * 0b1..High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time. 709 */ 710 #define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK) 711 712 #define ADC_CFG2_ADACKEN_MASK (0x8U) 713 #define ADC_CFG2_ADACKEN_SHIFT (3U) 714 /*! ADACKEN - Asynchronous Clock Output Enable 715 * 0b0..Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active. 716 * 0b1..Asynchronous clock and clock output is enabled regardless of the state of the ADC. 717 */ 718 #define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK) 719 /*! @} */ 720 721 /*! @name R - ADC Data Result Register */ 722 /*! @{ */ 723 724 #define ADC_R_D_MASK (0xFFFFU) 725 #define ADC_R_D_SHIFT (0U) 726 /*! D - Data result 727 */ 728 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK) 729 /*! @} */ 730 731 /* The count of ADC_R */ 732 #define ADC_R_COUNT (4U) 733 734 /*! @name CV1 - Compare Value Registers */ 735 /*! @{ */ 736 737 #define ADC_CV1_CV_MASK (0xFFFFU) 738 #define ADC_CV1_CV_SHIFT (0U) 739 /*! CV - Compare Value. 740 */ 741 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK) 742 /*! @} */ 743 744 /*! @name CV2 - Compare Value Registers */ 745 /*! @{ */ 746 747 #define ADC_CV2_CV_MASK (0xFFFFU) 748 #define ADC_CV2_CV_SHIFT (0U) 749 /*! CV - Compare Value. 750 */ 751 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK) 752 /*! @} */ 753 754 /*! @name SC2 - Status and Control Register 2 */ 755 /*! @{ */ 756 757 #define ADC_SC2_REFSEL_MASK (0x3U) 758 #define ADC_SC2_REFSEL_SHIFT (0U) 759 /*! REFSEL - Voltage Reference Selection 760 * 0b00..Default voltage reference pin pair, that is, external pins VREFH and VREFL 761 * 0b01..Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or 762 * internal sources depending on the MCU configuration. See the chip configuration information for details 763 * specific to this MCU 764 * 0b10..Internal bandgap reference and associated ground reference (V BGH and V BGL ). Consult the Chip 765 * Configuration information for details specific to this MCU. 766 * 0b11..Reserved 767 */ 768 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK) 769 770 #define ADC_SC2_DMAEN_MASK (0x4U) 771 #define ADC_SC2_DMAEN_SHIFT (2U) 772 /*! DMAEN - DMA Enable 773 * 0b0..DMA is disabled. 774 * 0b1..DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any 775 * of the SC1n[COCO] flags is asserted. 776 */ 777 #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK) 778 779 #define ADC_SC2_ACREN_MASK (0x8U) 780 #define ADC_SC2_ACREN_SHIFT (3U) 781 /*! ACREN - Compare Function Range Enable 782 * 0b0..Range function disabled. Only CV1 is compared. 783 * 0b1..Range function enabled. Both CV1 and CV2 are compared. 784 */ 785 #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK) 786 787 #define ADC_SC2_ACFGT_MASK (0x10U) 788 #define ADC_SC2_ACFGT_SHIFT (4U) 789 /*! ACFGT - Compare Function Greater Than Enable 790 * 0b0..Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality 791 * based on the values placed in CV1 and CV2. 792 * 0b1..Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2. 793 */ 794 #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK) 795 796 #define ADC_SC2_ACFE_MASK (0x20U) 797 #define ADC_SC2_ACFE_SHIFT (5U) 798 /*! ACFE - Compare Function Enable 799 * 0b0..Compare function disabled. 800 * 0b1..Compare function enabled. 801 */ 802 #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK) 803 804 #define ADC_SC2_ADTRG_MASK (0x40U) 805 #define ADC_SC2_ADTRG_SHIFT (6U) 806 /*! ADTRG - Conversion Trigger Select 807 * 0b0..Software trigger selected. 808 * 0b1..Hardware trigger selected. 809 */ 810 #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK) 811 812 #define ADC_SC2_ADACT_MASK (0x80U) 813 #define ADC_SC2_ADACT_SHIFT (7U) 814 /*! ADACT - Conversion Active 815 * 0b0..Conversion not in progress. 816 * 0b1..Conversion in progress. 817 */ 818 #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK) 819 /*! @} */ 820 821 /*! @name SC3 - Status and Control Register 3 */ 822 /*! @{ */ 823 824 #define ADC_SC3_AVGS_MASK (0x3U) 825 #define ADC_SC3_AVGS_SHIFT (0U) 826 /*! AVGS - Hardware Average Select 827 * 0b00..4 samples averaged. 828 * 0b01..8 samples averaged. 829 * 0b10..16 samples averaged. 830 * 0b11..32 samples averaged. 831 */ 832 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK) 833 834 #define ADC_SC3_AVGE_MASK (0x4U) 835 #define ADC_SC3_AVGE_SHIFT (2U) 836 /*! AVGE - Hardware Average Enable 837 * 0b0..Hardware average function disabled. 838 * 0b1..Hardware average function enabled. 839 */ 840 #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK) 841 842 #define ADC_SC3_ADCO_MASK (0x8U) 843 #define ADC_SC3_ADCO_SHIFT (3U) 844 /*! ADCO - Continuous Conversion Enable 845 * 0b0..One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. 846 * 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion. 847 */ 848 #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK) 849 850 #define ADC_SC3_CALF_MASK (0x40U) 851 #define ADC_SC3_CALF_SHIFT (6U) 852 /*! CALF - Calibration Failed Flag 853 * 0b0..Calibration completed normally. 854 * 0b1..Calibration failed. ADC accuracy specifications are not guaranteed. 855 */ 856 #define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK) 857 858 #define ADC_SC3_CAL_MASK (0x80U) 859 #define ADC_SC3_CAL_SHIFT (7U) 860 /*! CAL - Calibration 861 */ 862 #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK) 863 /*! @} */ 864 865 /*! @name OFS - ADC Offset Correction Register */ 866 /*! @{ */ 867 868 #define ADC_OFS_OFS_MASK (0xFFFFU) 869 #define ADC_OFS_OFS_SHIFT (0U) 870 /*! OFS - Offset Error Correction Value 871 */ 872 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) 873 /*! @} */ 874 875 /*! @name PG - ADC Plus-Side Gain Register */ 876 /*! @{ */ 877 878 #define ADC_PG_PG_MASK (0xFFFFU) 879 #define ADC_PG_PG_SHIFT (0U) 880 /*! PG - Plus-Side Gain 881 */ 882 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK) 883 /*! @} */ 884 885 /*! @name CLPD - ADC Plus-Side General Calibration Value Register */ 886 /*! @{ */ 887 888 #define ADC_CLPD_CLPD_MASK (0x3FU) 889 #define ADC_CLPD_CLPD_SHIFT (0U) 890 /*! CLPD - Calibration Value 891 */ 892 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK) 893 /*! @} */ 894 895 /*! @name CLPS - ADC Plus-Side General Calibration Value Register */ 896 /*! @{ */ 897 898 #define ADC_CLPS_CLPS_MASK (0x3FU) 899 #define ADC_CLPS_CLPS_SHIFT (0U) 900 /*! CLPS - Calibration Value 901 */ 902 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK) 903 /*! @} */ 904 905 /*! @name CLP4 - ADC Plus-Side General Calibration Value Register */ 906 /*! @{ */ 907 908 #define ADC_CLP4_CLP4_MASK (0x3FFU) 909 #define ADC_CLP4_CLP4_SHIFT (0U) 910 /*! CLP4 - Calibration Value 911 */ 912 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK) 913 /*! @} */ 914 915 /*! @name CLP3 - ADC Plus-Side General Calibration Value Register */ 916 /*! @{ */ 917 918 #define ADC_CLP3_CLP3_MASK (0x1FFU) 919 #define ADC_CLP3_CLP3_SHIFT (0U) 920 /*! CLP3 - Calibration Value 921 */ 922 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK) 923 /*! @} */ 924 925 /*! @name CLP2 - ADC Plus-Side General Calibration Value Register */ 926 /*! @{ */ 927 928 #define ADC_CLP2_CLP2_MASK (0xFFU) 929 #define ADC_CLP2_CLP2_SHIFT (0U) 930 /*! CLP2 - Calibration Value 931 */ 932 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK) 933 /*! @} */ 934 935 /*! @name CLP1 - ADC Plus-Side General Calibration Value Register */ 936 /*! @{ */ 937 938 #define ADC_CLP1_CLP1_MASK (0x7FU) 939 #define ADC_CLP1_CLP1_SHIFT (0U) 940 /*! CLP1 - Calibration Value 941 */ 942 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK) 943 /*! @} */ 944 945 /*! @name CLP0 - ADC Plus-Side General Calibration Value Register */ 946 /*! @{ */ 947 948 #define ADC_CLP0_CLP0_MASK (0x3FU) 949 #define ADC_CLP0_CLP0_SHIFT (0U) 950 /*! CLP0 - Calibration Value 951 */ 952 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK) 953 /*! @} */ 954 955 956 /*! 957 * @} 958 */ /* end of group ADC_Register_Masks */ 959 960 961 /* ADC - Peripheral instance base addresses */ 962 /** Peripheral ADC base address */ 963 #define ADC_BASE (0x4002B000u) 964 /** Peripheral ADC base pointer */ 965 #define ADC ((ADC_Type *)ADC_BASE) 966 /** Array initializer of ADC peripheral base addresses */ 967 #define ADC_BASE_ADDRS { ADC_BASE } 968 /** Array initializer of ADC peripheral base pointers */ 969 #define ADC_BASE_PTRS { ADC } 970 /** Interrupt vectors for the ADC peripheral type */ 971 #define ADC_IRQS { ADC_IRQn } 972 973 /*! 974 * @} 975 */ /* end of group ADC_Peripheral_Access_Layer */ 976 977 978 /* ---------------------------------------------------------------------------- 979 -- AFE Peripheral Access Layer 980 ---------------------------------------------------------------------------- */ 981 982 /*! 983 * @addtogroup AFE_Peripheral_Access_Layer AFE Peripheral Access Layer 984 * @{ 985 */ 986 987 /** AFE - Register Layout Typedef */ 988 typedef struct { 989 __IO uint32_t CFR[4]; /**< Channel0 Configuration Register..Channel3 Configuration Register, array offset: 0x0, array step: 0x4 */ 990 uint8_t RESERVED_0[8]; 991 __IO uint32_t CR; /**< Control Register, offset: 0x18 */ 992 __IO uint32_t CKR; /**< Clock Configuration Register, offset: 0x1C */ 993 __IO uint32_t DI; /**< DMA and Interrupt Register, offset: 0x20 */ 994 uint8_t RESERVED_1[8]; 995 __IO uint32_t DR[4]; /**< Channel0 Delay Register..Channel3 Delay Register, array offset: 0x2C, array step: 0x4 */ 996 uint8_t RESERVED_2[8]; 997 __I uint32_t RR[4]; /**< Channel0 Result Register..Channel3 Result Register, array offset: 0x44, array step: 0x4 */ 998 uint8_t RESERVED_3[8]; 999 __I uint32_t SR; /**< Status Register, offset: 0x5C */ 1000 } AFE_Type; 1001 1002 /* ---------------------------------------------------------------------------- 1003 -- AFE Register Masks 1004 ---------------------------------------------------------------------------- */ 1005 1006 /*! 1007 * @addtogroup AFE_Register_Masks AFE Register Masks 1008 * @{ 1009 */ 1010 1011 /*! @name CFR - Channel0 Configuration Register..Channel3 Configuration Register */ 1012 /*! @{ */ 1013 1014 #define AFE_CFR_HW_TRG_MASK (0x200U) 1015 #define AFE_CFR_HW_TRG_SHIFT (9U) 1016 /*! HW_TRG - Hardware Trigger Select 1017 * 0b0..Software trigger select 1018 * 0b1..Hardware trigger select 1019 */ 1020 #define AFE_CFR_HW_TRG(x) (((uint32_t)(((uint32_t)(x)) << AFE_CFR_HW_TRG_SHIFT)) & AFE_CFR_HW_TRG_MASK) 1021 1022 #define AFE_CFR_DEC_CLK_INP_SEL_MASK (0x400U) 1023 #define AFE_CFR_DEC_CLK_INP_SEL_SHIFT (10U) 1024 /*! DEC_CLK_INP_SEL - Decimator Clock Input Select 1025 * 0b0..On the chip modulator clock will be used 1026 * 0b1..External clock will be used. 1027 */ 1028 #define AFE_CFR_DEC_CLK_INP_SEL(x) (((uint32_t)(((uint32_t)(x)) << AFE_CFR_DEC_CLK_INP_SEL_SHIFT)) & AFE_CFR_DEC_CLK_INP_SEL_MASK) 1029 1030 #define AFE_CFR_DEC_CLK_EDGE_SEL_MASK (0x800U) 1031 #define AFE_CFR_DEC_CLK_EDGE_SEL_SHIFT (11U) 1032 /*! DEC_CLK_EDGE_SEL - Decimator Clock Edge Select 1033 * 0b0..Posedge will be used. 1034 * 0b1..Negedge will be used. 1035 */ 1036 #define AFE_CFR_DEC_CLK_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << AFE_CFR_DEC_CLK_EDGE_SEL_SHIFT)) & AFE_CFR_DEC_CLK_EDGE_SEL_MASK) 1037 1038 #define AFE_CFR_CC_MASK (0x1000U) 1039 #define AFE_CFR_CC_SHIFT (12U) 1040 /*! CC - Continuous Conversion/Single Conversion Mode Select 1041 * 0b0..One conversion following a triggering event 1042 * 0b1..Continuous conversions following a triggering event. 1043 */ 1044 #define AFE_CFR_CC(x) (((uint32_t)(((uint32_t)(x)) << AFE_CFR_CC_SHIFT)) & AFE_CFR_CC_MASK) 1045 1046 #define AFE_CFR_DEC_EN_MASK (0x2000U) 1047 #define AFE_CFR_DEC_EN_SHIFT (13U) 1048 /*! DEC_EN - Decimation Filter enable 1049 * 0b0..Decimation filter is disabled. 1050 * 0b1..Decimation filter is enabled. 1051 */ 1052 #define AFE_CFR_DEC_EN(x) (((uint32_t)(((uint32_t)(x)) << AFE_CFR_DEC_EN_SHIFT)) & AFE_CFR_DEC_EN_MASK) 1053 1054 #define AFE_CFR_SD_MOD_EN_MASK (0x4000U) 1055 #define AFE_CFR_SD_MOD_EN_SHIFT (14U) 1056 /*! SD_MOD_EN - Sigma Delta Modulator enable 1057 * 0b0..SD ADC1 is disabled 1058 * 0b1..SD ADC1 is enabled 1059 */ 1060 #define AFE_CFR_SD_MOD_EN(x) (((uint32_t)(((uint32_t)(x)) << AFE_CFR_SD_MOD_EN_SHIFT)) & AFE_CFR_SD_MOD_EN_MASK) 1061 1062 #define AFE_CFR_BYP_MODE_MASK (0x20000U) 1063 #define AFE_CFR_BYP_MODE_SHIFT (17U) 1064 /*! BYP_MODE - AFE Channel3 bypass mode 1065 * 0b0..Normal mode 1066 * 0b1..Bypass mode where ADC and PGA of channel0 are disabled. 1067 */ 1068 #define AFE_CFR_BYP_MODE(x) (((uint32_t)(((uint32_t)(x)) << AFE_CFR_BYP_MODE_SHIFT)) & AFE_CFR_BYP_MODE_MASK) 1069 1070 #define AFE_CFR_PGA_GAIN_SEL_MASK (0x380000U) 1071 #define AFE_CFR_PGA_GAIN_SEL_SHIFT (19U) 1072 /*! PGA_GAIN_SEL - PGA Gain Select 1073 * 0b000..reserved 1074 * 0b001..1x (default) 1075 * 0b010..2x 1076 * 0b011..4x 1077 * 0b100..8x 1078 * 0b101..16x 1079 * 0b110..32x 1080 * 0b111..reserved 1081 */ 1082 #define AFE_CFR_PGA_GAIN_SEL(x) (((uint32_t)(((uint32_t)(x)) << AFE_CFR_PGA_GAIN_SEL_SHIFT)) & AFE_CFR_PGA_GAIN_SEL_MASK) 1083 1084 #define AFE_CFR_PGA_EN_MASK (0x1000000U) 1085 #define AFE_CFR_PGA_EN_SHIFT (24U) 1086 /*! PGA_EN - PGA enable 1087 * 0b0..PGA disabled 1088 * 0b1..PGA enabled 1089 */ 1090 #define AFE_CFR_PGA_EN(x) (((uint32_t)(((uint32_t)(x)) << AFE_CFR_PGA_EN_SHIFT)) & AFE_CFR_PGA_EN_MASK) 1091 1092 #define AFE_CFR_DEC_OSR_MASK (0xE0000000U) 1093 #define AFE_CFR_DEC_OSR_SHIFT (29U) 1094 /*! DEC_OSR - Decimator OverSampling Ratio select 1095 * 0b000..64 1096 * 0b001..128 1097 * 0b010..256 1098 * 0b011..512 1099 * 0b100..1024 1100 * 0b101..2048 1101 */ 1102 #define AFE_CFR_DEC_OSR(x) (((uint32_t)(((uint32_t)(x)) << AFE_CFR_DEC_OSR_SHIFT)) & AFE_CFR_DEC_OSR_MASK) 1103 /*! @} */ 1104 1105 /* The count of AFE_CFR */ 1106 #define AFE_CFR_COUNT (4U) 1107 1108 /*! @name CR - Control Register */ 1109 /*! @{ */ 1110 1111 #define AFE_CR_STRTUP_CNT_MASK (0xFE00U) 1112 #define AFE_CR_STRTUP_CNT_SHIFT (9U) 1113 /*! STRTUP_CNT - Start up count 1114 */ 1115 #define AFE_CR_STRTUP_CNT(x) (((uint32_t)(((uint32_t)(x)) << AFE_CR_STRTUP_CNT_SHIFT)) & AFE_CR_STRTUP_CNT_MASK) 1116 1117 #define AFE_CR_RESULT_FORMAT_MASK (0x40000U) 1118 #define AFE_CR_RESULT_FORMAT_SHIFT (18U) 1119 /*! RESULT_FORMAT - Result Format 1120 * 0b0..Left justified 2's complement 32-bit : SVVVVVVVVVVVVVVVVVVVVVVV00000000 where (S= sign bit , V=valid result value, 0=zero) 1121 * 0b1..Right justified 2's complement 32-bit : SSSSSSSSSVVVVVVVVVVVVVVVVVVVVVVV where (S= sign bit , V= valid result value, 0= zero) 1122 */ 1123 #define AFE_CR_RESULT_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << AFE_CR_RESULT_FORMAT_SHIFT)) & AFE_CR_RESULT_FORMAT_MASK) 1124 1125 #define AFE_CR_DLY_OK_MASK (0x200000U) 1126 #define AFE_CR_DLY_OK_SHIFT (21U) 1127 /*! DLY_OK - Delay OK 1128 */ 1129 #define AFE_CR_DLY_OK(x) (((uint32_t)(((uint32_t)(x)) << AFE_CR_DLY_OK_SHIFT)) & AFE_CR_DLY_OK_MASK) 1130 1131 #define AFE_CR_RST_B_MASK (0x400000U) 1132 #define AFE_CR_RST_B_SHIFT (22U) 1133 /*! RST_B - Software Reset 1134 * 0b0..All ADCs, PGAs and Decimation filters are disabled. Clock Configuration bits will be reset. 1135 * 0b1...= All ADCs, PGAs and Decimation filters are enabled. 1136 */ 1137 #define AFE_CR_RST_B(x) (((uint32_t)(((uint32_t)(x)) << AFE_CR_RST_B_SHIFT)) & AFE_CR_RST_B_MASK) 1138 1139 #define AFE_CR_LPM_EN_MASK (0x2000000U) 1140 #define AFE_CR_LPM_EN_SHIFT (25U) 1141 /*! LPM_EN - Low power Mode enable 1142 * 0b0..AFE will be in normal mode 1143 * 0b1..AFE will be in low power mode. Setting this bit reduce the current consumption of ADC and Buffer 1144 * Amplifier , the max modulator clock frequency is below 1Mhz. 1145 */ 1146 #define AFE_CR_LPM_EN(x) (((uint32_t)(((uint32_t)(x)) << AFE_CR_LPM_EN_SHIFT)) & AFE_CR_LPM_EN_MASK) 1147 1148 #define AFE_CR_SOFT_TRG3_MASK (0x8000000U) 1149 #define AFE_CR_SOFT_TRG3_SHIFT (27U) 1150 /*! SOFT_TRG3 - Software Trigger3 1151 */ 1152 #define AFE_CR_SOFT_TRG3(x) (((uint32_t)(((uint32_t)(x)) << AFE_CR_SOFT_TRG3_SHIFT)) & AFE_CR_SOFT_TRG3_MASK) 1153 1154 #define AFE_CR_SOFT_TRG2_MASK (0x10000000U) 1155 #define AFE_CR_SOFT_TRG2_SHIFT (28U) 1156 /*! SOFT_TRG2 - Software Trigger2 1157 */ 1158 #define AFE_CR_SOFT_TRG2(x) (((uint32_t)(((uint32_t)(x)) << AFE_CR_SOFT_TRG2_SHIFT)) & AFE_CR_SOFT_TRG2_MASK) 1159 1160 #define AFE_CR_SOFT_TRG1_MASK (0x20000000U) 1161 #define AFE_CR_SOFT_TRG1_SHIFT (29U) 1162 /*! SOFT_TRG1 - Software Trigger1 1163 */ 1164 #define AFE_CR_SOFT_TRG1(x) (((uint32_t)(((uint32_t)(x)) << AFE_CR_SOFT_TRG1_SHIFT)) & AFE_CR_SOFT_TRG1_MASK) 1165 1166 #define AFE_CR_SOFT_TRG0_MASK (0x40000000U) 1167 #define AFE_CR_SOFT_TRG0_SHIFT (30U) 1168 /*! SOFT_TRG0 - Software Trigger0 1169 */ 1170 #define AFE_CR_SOFT_TRG0(x) (((uint32_t)(((uint32_t)(x)) << AFE_CR_SOFT_TRG0_SHIFT)) & AFE_CR_SOFT_TRG0_MASK) 1171 1172 #define AFE_CR_MSTR_EN_MASK (0x80000000U) 1173 #define AFE_CR_MSTR_EN_SHIFT (31U) 1174 /*! MSTR_EN - AFE Master Enable 1175 * 0b0..All ADCs are disabled. 1176 * 0b1..All ADCs and filters will get simultaneously enabled . 1177 */ 1178 #define AFE_CR_MSTR_EN(x) (((uint32_t)(((uint32_t)(x)) << AFE_CR_MSTR_EN_SHIFT)) & AFE_CR_MSTR_EN_MASK) 1179 /*! @} */ 1180 1181 /*! @name CKR - Clock Configuration Register */ 1182 /*! @{ */ 1183 1184 #define AFE_CKR_CLS_MASK (0x600000U) 1185 #define AFE_CKR_CLS_SHIFT (21U) 1186 /*! CLS - Clock Source Select 1187 * 0b00..mod_clk0 1188 * 0b01..mod_clk1 1189 * 0b10..mod_clk2 1190 * 0b11..mod_clk3 1191 */ 1192 #define AFE_CKR_CLS(x) (((uint32_t)(((uint32_t)(x)) << AFE_CKR_CLS_SHIFT)) & AFE_CKR_CLS_MASK) 1193 1194 #define AFE_CKR_DIV_MASK (0xF0000000U) 1195 #define AFE_CKR_DIV_SHIFT (28U) 1196 /*! DIV - Clock Divider Select 1197 * 0b0000..divide by 1 1198 * 0b0001..divide by 2 (default) 1199 * 0b0010..divide by 4 1200 * 0b0011..divide by 8 1201 * 0b0100..divide by 16 1202 * 0b0101..divide by 32 1203 * 0b0110..divide by 64 1204 * 0b0111..divide by 128 1205 * 0b1xxx..divide by 256 1206 */ 1207 #define AFE_CKR_DIV(x) (((uint32_t)(((uint32_t)(x)) << AFE_CKR_DIV_SHIFT)) & AFE_CKR_DIV_MASK) 1208 /*! @} */ 1209 1210 /*! @name DI - DMA and Interrupt Register */ 1211 /*! @{ */ 1212 1213 #define AFE_DI_INTEN3_MASK (0x800000U) 1214 #define AFE_DI_INTEN3_SHIFT (23U) 1215 /*! INTEN3 - Interrupt Enable 3 1216 */ 1217 #define AFE_DI_INTEN3(x) (((uint32_t)(((uint32_t)(x)) << AFE_DI_INTEN3_SHIFT)) & AFE_DI_INTEN3_MASK) 1218 1219 #define AFE_DI_INTEN2_MASK (0x1000000U) 1220 #define AFE_DI_INTEN2_SHIFT (24U) 1221 /*! INTEN2 - Interrupt Enable 2 1222 */ 1223 #define AFE_DI_INTEN2(x) (((uint32_t)(((uint32_t)(x)) << AFE_DI_INTEN2_SHIFT)) & AFE_DI_INTEN2_MASK) 1224 1225 #define AFE_DI_INTEN1_MASK (0x2000000U) 1226 #define AFE_DI_INTEN1_SHIFT (25U) 1227 /*! INTEN1 - Interrupt Enable 1 1228 */ 1229 #define AFE_DI_INTEN1(x) (((uint32_t)(((uint32_t)(x)) << AFE_DI_INTEN1_SHIFT)) & AFE_DI_INTEN1_MASK) 1230 1231 #define AFE_DI_INTEN0_MASK (0x4000000U) 1232 #define AFE_DI_INTEN0_SHIFT (26U) 1233 /*! INTEN0 - Interrupt Enable 0 1234 */ 1235 #define AFE_DI_INTEN0(x) (((uint32_t)(((uint32_t)(x)) << AFE_DI_INTEN0_SHIFT)) & AFE_DI_INTEN0_MASK) 1236 1237 #define AFE_DI_DMAEN3_MASK (0x10000000U) 1238 #define AFE_DI_DMAEN3_SHIFT (28U) 1239 /*! DMAEN3 - DMA Enable3 1240 */ 1241 #define AFE_DI_DMAEN3(x) (((uint32_t)(((uint32_t)(x)) << AFE_DI_DMAEN3_SHIFT)) & AFE_DI_DMAEN3_MASK) 1242 1243 #define AFE_DI_DMAEN2_MASK (0x20000000U) 1244 #define AFE_DI_DMAEN2_SHIFT (29U) 1245 /*! DMAEN2 - DMA Enable2 1246 */ 1247 #define AFE_DI_DMAEN2(x) (((uint32_t)(((uint32_t)(x)) << AFE_DI_DMAEN2_SHIFT)) & AFE_DI_DMAEN2_MASK) 1248 1249 #define AFE_DI_DMAEN1_MASK (0x40000000U) 1250 #define AFE_DI_DMAEN1_SHIFT (30U) 1251 /*! DMAEN1 - DMA Enable1 1252 */ 1253 #define AFE_DI_DMAEN1(x) (((uint32_t)(((uint32_t)(x)) << AFE_DI_DMAEN1_SHIFT)) & AFE_DI_DMAEN1_MASK) 1254 1255 #define AFE_DI_DMAEN0_MASK (0x80000000U) 1256 #define AFE_DI_DMAEN0_SHIFT (31U) 1257 /*! DMAEN0 - DMA Enable0 1258 */ 1259 #define AFE_DI_DMAEN0(x) (((uint32_t)(((uint32_t)(x)) << AFE_DI_DMAEN0_SHIFT)) & AFE_DI_DMAEN0_MASK) 1260 /*! @} */ 1261 1262 /*! @name DR - Channel0 Delay Register..Channel3 Delay Register */ 1263 /*! @{ */ 1264 1265 #define AFE_DR_DLY_MASK (0x7FFU) 1266 #define AFE_DR_DLY_SHIFT (0U) 1267 /*! DLY - Delay 1268 */ 1269 #define AFE_DR_DLY(x) (((uint32_t)(((uint32_t)(x)) << AFE_DR_DLY_SHIFT)) & AFE_DR_DLY_MASK) 1270 /*! @} */ 1271 1272 /* The count of AFE_DR */ 1273 #define AFE_DR_COUNT (4U) 1274 1275 /*! @name RR - Channel0 Result Register..Channel3 Result Register */ 1276 /*! @{ */ 1277 1278 #define AFE_RR_SDR_MASK (0x7FFFFFU) 1279 #define AFE_RR_SDR_SHIFT (0U) 1280 /*! SDR - Sample Data result 1281 */ 1282 #define AFE_RR_SDR(x) (((uint32_t)(((uint32_t)(x)) << AFE_RR_SDR_SHIFT)) & AFE_RR_SDR_MASK) 1283 1284 #define AFE_RR_SIGN_BITS_MASK (0xFF800000U) 1285 #define AFE_RR_SIGN_BITS_SHIFT (23U) 1286 /*! SIGN_BITS - Sign Bits 1287 */ 1288 #define AFE_RR_SIGN_BITS(x) (((uint32_t)(((uint32_t)(x)) << AFE_RR_SIGN_BITS_SHIFT)) & AFE_RR_SIGN_BITS_MASK) 1289 /*! @} */ 1290 1291 /* The count of AFE_RR */ 1292 #define AFE_RR_COUNT (4U) 1293 1294 /*! @name SR - Status Register */ 1295 /*! @{ */ 1296 1297 #define AFE_SR_RDY3_MASK (0x10000U) 1298 #define AFE_SR_RDY3_SHIFT (16U) 1299 /*! RDY3 - AFE Ready4 1300 * 0b0..AFE Channel3 is disabled or has not completed its start up period 1301 * 0b1..AFE Channel3 is ready to initiate conversions. 1302 */ 1303 #define AFE_SR_RDY3(x) (((uint32_t)(((uint32_t)(x)) << AFE_SR_RDY3_SHIFT)) & AFE_SR_RDY3_MASK) 1304 1305 #define AFE_SR_RDY2_MASK (0x20000U) 1306 #define AFE_SR_RDY2_SHIFT (17U) 1307 /*! RDY2 - AFE Ready3 1308 * 0b0..AFE Channel2 is disabled or has not completed its start up period 1309 * 0b1..AFE Channel2 is ready to initiate conversions. 1310 */ 1311 #define AFE_SR_RDY2(x) (((uint32_t)(((uint32_t)(x)) << AFE_SR_RDY2_SHIFT)) & AFE_SR_RDY2_MASK) 1312 1313 #define AFE_SR_RDY1_MASK (0x40000U) 1314 #define AFE_SR_RDY1_SHIFT (18U) 1315 /*! RDY1 - AFE Ready2 1316 * 0b0..AFE Channel1 is disabled or has not completed its start up period 1317 * 0b1..AFE Channel1 is ready to initiate conversions. 1318 */ 1319 #define AFE_SR_RDY1(x) (((uint32_t)(((uint32_t)(x)) << AFE_SR_RDY1_SHIFT)) & AFE_SR_RDY1_MASK) 1320 1321 #define AFE_SR_RDY0_MASK (0x80000U) 1322 #define AFE_SR_RDY0_SHIFT (19U) 1323 /*! RDY0 - AFE Ready1 1324 * 0b0..AFE Channel0 is disabled or has not completed its start up period 1325 * 0b1..AFE Channel0 is ready to initiate conversions. 1326 */ 1327 #define AFE_SR_RDY0(x) (((uint32_t)(((uint32_t)(x)) << AFE_SR_RDY0_SHIFT)) & AFE_SR_RDY0_MASK) 1328 1329 #define AFE_SR_OVR3_MASK (0x200000U) 1330 #define AFE_SR_OVR3_SHIFT (21U) 1331 /*! OVR3 - Overflow Flag 1332 */ 1333 #define AFE_SR_OVR3(x) (((uint32_t)(((uint32_t)(x)) << AFE_SR_OVR3_SHIFT)) & AFE_SR_OVR3_MASK) 1334 1335 #define AFE_SR_OVR2_MASK (0x400000U) 1336 #define AFE_SR_OVR2_SHIFT (22U) 1337 /*! OVR2 - Overflow Flag 1338 */ 1339 #define AFE_SR_OVR2(x) (((uint32_t)(((uint32_t)(x)) << AFE_SR_OVR2_SHIFT)) & AFE_SR_OVR2_MASK) 1340 1341 #define AFE_SR_OVR1_MASK (0x800000U) 1342 #define AFE_SR_OVR1_SHIFT (23U) 1343 /*! OVR1 - Overflow Flag 1344 */ 1345 #define AFE_SR_OVR1(x) (((uint32_t)(((uint32_t)(x)) << AFE_SR_OVR1_SHIFT)) & AFE_SR_OVR1_MASK) 1346 1347 #define AFE_SR_OVR0_MASK (0x1000000U) 1348 #define AFE_SR_OVR0_SHIFT (24U) 1349 /*! OVR0 - Overflow Flag 1350 */ 1351 #define AFE_SR_OVR0(x) (((uint32_t)(((uint32_t)(x)) << AFE_SR_OVR0_SHIFT)) & AFE_SR_OVR0_MASK) 1352 1353 #define AFE_SR_COC3_MASK (0x10000000U) 1354 #define AFE_SR_COC3_SHIFT (28U) 1355 /*! COC3 - Conversion Complete 1356 */ 1357 #define AFE_SR_COC3(x) (((uint32_t)(((uint32_t)(x)) << AFE_SR_COC3_SHIFT)) & AFE_SR_COC3_MASK) 1358 1359 #define AFE_SR_COC2_MASK (0x20000000U) 1360 #define AFE_SR_COC2_SHIFT (29U) 1361 /*! COC2 - Conversion Complete 1362 */ 1363 #define AFE_SR_COC2(x) (((uint32_t)(((uint32_t)(x)) << AFE_SR_COC2_SHIFT)) & AFE_SR_COC2_MASK) 1364 1365 #define AFE_SR_COC1_MASK (0x40000000U) 1366 #define AFE_SR_COC1_SHIFT (30U) 1367 /*! COC1 - Conversion Complete 1368 */ 1369 #define AFE_SR_COC1(x) (((uint32_t)(((uint32_t)(x)) << AFE_SR_COC1_SHIFT)) & AFE_SR_COC1_MASK) 1370 1371 #define AFE_SR_COC0_MASK (0x80000000U) 1372 #define AFE_SR_COC0_SHIFT (31U) 1373 /*! COC0 - Conversion Complete 1374 */ 1375 #define AFE_SR_COC0(x) (((uint32_t)(((uint32_t)(x)) << AFE_SR_COC0_SHIFT)) & AFE_SR_COC0_MASK) 1376 /*! @} */ 1377 1378 1379 /*! 1380 * @} 1381 */ /* end of group AFE_Register_Masks */ 1382 1383 1384 /* AFE - Peripheral instance base addresses */ 1385 /** Peripheral AFE base address */ 1386 #define AFE_BASE (0x40030000u) 1387 /** Peripheral AFE base pointer */ 1388 #define AFE ((AFE_Type *)AFE_BASE) 1389 /** Array initializer of AFE peripheral base addresses */ 1390 #define AFE_BASE_ADDRS { AFE_BASE } 1391 /** Array initializer of AFE peripheral base pointers */ 1392 #define AFE_BASE_PTRS { AFE } 1393 /** Interrupt vectors for the AFE peripheral type */ 1394 #define AFE_IRQS { { AFE_CH0_IRQn, AFE_CH1_IRQn, AFE_CH2_IRQn, AFE_CH3_IRQn } } 1395 1396 /*! 1397 * @} 1398 */ /* end of group AFE_Peripheral_Access_Layer */ 1399 1400 1401 /* ---------------------------------------------------------------------------- 1402 -- AIPS Peripheral Access Layer 1403 ---------------------------------------------------------------------------- */ 1404 1405 /*! 1406 * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer 1407 * @{ 1408 */ 1409 1410 /** AIPS - Register Layout Typedef */ 1411 typedef struct { 1412 uint8_t RESERVED_0[32]; 1413 __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */ 1414 __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */ 1415 uint8_t RESERVED_1[24]; 1416 __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */ 1417 __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */ 1418 __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */ 1419 __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */ 1420 __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */ 1421 __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */ 1422 __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */ 1423 __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */ 1424 __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */ 1425 __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */ 1426 __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */ 1427 __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */ 1428 } AIPS_Type; 1429 1430 /* ---------------------------------------------------------------------------- 1431 -- AIPS Register Masks 1432 ---------------------------------------------------------------------------- */ 1433 1434 /*! 1435 * @addtogroup AIPS_Register_Masks AIPS Register Masks 1436 * @{ 1437 */ 1438 1439 /*! @name PACRA - Peripheral Access Control Register */ 1440 /*! @{ */ 1441 1442 #define AIPS_PACRA_AC7_MASK (0x7U) 1443 #define AIPS_PACRA_AC7_SHIFT (0U) 1444 /*! AC7 - Attribute Check 1445 */ 1446 #define AIPS_PACRA_AC7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_AC7_SHIFT)) & AIPS_PACRA_AC7_MASK) 1447 1448 #define AIPS_PACRA_RO7_MASK (0x8U) 1449 #define AIPS_PACRA_RO7_SHIFT (3U) 1450 /*! RO7 - Read Only 1451 * 0b0..Writes to corresponding AC field are allowed. 1452 * 0b1..Writes to corresponding AC field are ignored. 1453 */ 1454 #define AIPS_PACRA_RO7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_RO7_SHIFT)) & AIPS_PACRA_RO7_MASK) 1455 1456 #define AIPS_PACRA_AC6_MASK (0x70U) 1457 #define AIPS_PACRA_AC6_SHIFT (4U) 1458 /*! AC6 - Attribute Check 1459 */ 1460 #define AIPS_PACRA_AC6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_AC6_SHIFT)) & AIPS_PACRA_AC6_MASK) 1461 1462 #define AIPS_PACRA_RO6_MASK (0x80U) 1463 #define AIPS_PACRA_RO6_SHIFT (7U) 1464 /*! RO6 - Read Only 1465 * 0b0..Writes to corresponding AC field are allowed. 1466 * 0b1..Writes to corresponding AC field are ignored. 1467 */ 1468 #define AIPS_PACRA_RO6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_RO6_SHIFT)) & AIPS_PACRA_RO6_MASK) 1469 1470 #define AIPS_PACRA_AC5_MASK (0x700U) 1471 #define AIPS_PACRA_AC5_SHIFT (8U) 1472 /*! AC5 - Attribute Check 1473 */ 1474 #define AIPS_PACRA_AC5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_AC5_SHIFT)) & AIPS_PACRA_AC5_MASK) 1475 1476 #define AIPS_PACRA_RO5_MASK (0x800U) 1477 #define AIPS_PACRA_RO5_SHIFT (11U) 1478 /*! RO5 - Read Only 1479 * 0b0..Writes to corresponding AC field are allowed. 1480 * 0b1..Writes to corresponding AC field are ignored. 1481 */ 1482 #define AIPS_PACRA_RO5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_RO5_SHIFT)) & AIPS_PACRA_RO5_MASK) 1483 1484 #define AIPS_PACRA_AC4_MASK (0x7000U) 1485 #define AIPS_PACRA_AC4_SHIFT (12U) 1486 /*! AC4 - Attribute Check 1487 */ 1488 #define AIPS_PACRA_AC4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_AC4_SHIFT)) & AIPS_PACRA_AC4_MASK) 1489 1490 #define AIPS_PACRA_RO4_MASK (0x8000U) 1491 #define AIPS_PACRA_RO4_SHIFT (15U) 1492 /*! RO4 - Read Only 1493 * 0b0..Writes to corresponding AC field are allowed. 1494 * 0b1..Writes to corresponding AC field are ignored. 1495 */ 1496 #define AIPS_PACRA_RO4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_RO4_SHIFT)) & AIPS_PACRA_RO4_MASK) 1497 1498 #define AIPS_PACRA_AC3_MASK (0x70000U) 1499 #define AIPS_PACRA_AC3_SHIFT (16U) 1500 /*! AC3 - Attribute Check 1501 */ 1502 #define AIPS_PACRA_AC3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_AC3_SHIFT)) & AIPS_PACRA_AC3_MASK) 1503 1504 #define AIPS_PACRA_RO3_MASK (0x80000U) 1505 #define AIPS_PACRA_RO3_SHIFT (19U) 1506 /*! RO3 - Read Only 1507 * 0b0..Writes to corresponding AC field are allowed. 1508 * 0b1..Writes to corresponding AC field are ignored. 1509 */ 1510 #define AIPS_PACRA_RO3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_RO3_SHIFT)) & AIPS_PACRA_RO3_MASK) 1511 1512 #define AIPS_PACRA_AC2_MASK (0x700000U) 1513 #define AIPS_PACRA_AC2_SHIFT (20U) 1514 /*! AC2 - Attribute Check 1515 */ 1516 #define AIPS_PACRA_AC2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_AC2_SHIFT)) & AIPS_PACRA_AC2_MASK) 1517 1518 #define AIPS_PACRA_RO2_MASK (0x800000U) 1519 #define AIPS_PACRA_RO2_SHIFT (23U) 1520 /*! RO2 - Read Only 1521 * 0b0..Writes to corresponding AC field are allowed. 1522 * 0b1..Writes to corresponding AC field are ignored. 1523 */ 1524 #define AIPS_PACRA_RO2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_RO2_SHIFT)) & AIPS_PACRA_RO2_MASK) 1525 1526 #define AIPS_PACRA_AC1_MASK (0x7000000U) 1527 #define AIPS_PACRA_AC1_SHIFT (24U) 1528 /*! AC1 - Attribute Check 1529 */ 1530 #define AIPS_PACRA_AC1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_AC1_SHIFT)) & AIPS_PACRA_AC1_MASK) 1531 1532 #define AIPS_PACRA_RO1_MASK (0x8000000U) 1533 #define AIPS_PACRA_RO1_SHIFT (27U) 1534 /*! RO1 - Read Only 1535 * 0b0..Writes to corresponding AC field are allowed. 1536 * 0b1..Writes to corresponding AC field are ignored. 1537 */ 1538 #define AIPS_PACRA_RO1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_RO1_SHIFT)) & AIPS_PACRA_RO1_MASK) 1539 1540 #define AIPS_PACRA_AC0_MASK (0x70000000U) 1541 #define AIPS_PACRA_AC0_SHIFT (28U) 1542 /*! AC0 - Attribute Check 1543 */ 1544 #define AIPS_PACRA_AC0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_AC0_SHIFT)) & AIPS_PACRA_AC0_MASK) 1545 1546 #define AIPS_PACRA_RO0_MASK (0x80000000U) 1547 #define AIPS_PACRA_RO0_SHIFT (31U) 1548 /*! RO0 - Read Only 1549 * 0b0..Writes to corresponding AC field are allowed. 1550 * 0b1..Writes to corresponding AC field are ignored. 1551 */ 1552 #define AIPS_PACRA_RO0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_RO0_SHIFT)) & AIPS_PACRA_RO0_MASK) 1553 /*! @} */ 1554 1555 /*! @name PACRB - Peripheral Access Control Register */ 1556 /*! @{ */ 1557 1558 #define AIPS_PACRB_AC7_MASK (0x7U) 1559 #define AIPS_PACRB_AC7_SHIFT (0U) 1560 /*! AC7 - Attribute Check 1561 */ 1562 #define AIPS_PACRB_AC7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_AC7_SHIFT)) & AIPS_PACRB_AC7_MASK) 1563 1564 #define AIPS_PACRB_RO7_MASK (0x8U) 1565 #define AIPS_PACRB_RO7_SHIFT (3U) 1566 /*! RO7 - Read Only 1567 * 0b0..Writes to corresponding AC field are allowed. 1568 * 0b1..Writes to corresponding AC field are ignored. 1569 */ 1570 #define AIPS_PACRB_RO7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_RO7_SHIFT)) & AIPS_PACRB_RO7_MASK) 1571 1572 #define AIPS_PACRB_AC6_MASK (0x70U) 1573 #define AIPS_PACRB_AC6_SHIFT (4U) 1574 /*! AC6 - Attribute Check 1575 */ 1576 #define AIPS_PACRB_AC6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_AC6_SHIFT)) & AIPS_PACRB_AC6_MASK) 1577 1578 #define AIPS_PACRB_RO6_MASK (0x80U) 1579 #define AIPS_PACRB_RO6_SHIFT (7U) 1580 /*! RO6 - Read Only 1581 * 0b0..Writes to corresponding AC field are allowed. 1582 * 0b1..Writes to corresponding AC field are ignored. 1583 */ 1584 #define AIPS_PACRB_RO6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_RO6_SHIFT)) & AIPS_PACRB_RO6_MASK) 1585 1586 #define AIPS_PACRB_AC5_MASK (0x700U) 1587 #define AIPS_PACRB_AC5_SHIFT (8U) 1588 /*! AC5 - Attribute Check 1589 */ 1590 #define AIPS_PACRB_AC5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_AC5_SHIFT)) & AIPS_PACRB_AC5_MASK) 1591 1592 #define AIPS_PACRB_RO5_MASK (0x800U) 1593 #define AIPS_PACRB_RO5_SHIFT (11U) 1594 /*! RO5 - Read Only 1595 * 0b0..Writes to corresponding AC field are allowed. 1596 * 0b1..Writes to corresponding AC field are ignored. 1597 */ 1598 #define AIPS_PACRB_RO5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_RO5_SHIFT)) & AIPS_PACRB_RO5_MASK) 1599 1600 #define AIPS_PACRB_AC4_MASK (0x7000U) 1601 #define AIPS_PACRB_AC4_SHIFT (12U) 1602 /*! AC4 - Attribute Check 1603 */ 1604 #define AIPS_PACRB_AC4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_AC4_SHIFT)) & AIPS_PACRB_AC4_MASK) 1605 1606 #define AIPS_PACRB_RO4_MASK (0x8000U) 1607 #define AIPS_PACRB_RO4_SHIFT (15U) 1608 /*! RO4 - Read Only 1609 * 0b0..Writes to corresponding AC field are allowed. 1610 * 0b1..Writes to corresponding AC field are ignored. 1611 */ 1612 #define AIPS_PACRB_RO4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_RO4_SHIFT)) & AIPS_PACRB_RO4_MASK) 1613 1614 #define AIPS_PACRB_AC3_MASK (0x70000U) 1615 #define AIPS_PACRB_AC3_SHIFT (16U) 1616 /*! AC3 - Attribute Check 1617 */ 1618 #define AIPS_PACRB_AC3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_AC3_SHIFT)) & AIPS_PACRB_AC3_MASK) 1619 1620 #define AIPS_PACRB_RO3_MASK (0x80000U) 1621 #define AIPS_PACRB_RO3_SHIFT (19U) 1622 /*! RO3 - Read Only 1623 * 0b0..Writes to corresponding AC field are allowed. 1624 * 0b1..Writes to corresponding AC field are ignored. 1625 */ 1626 #define AIPS_PACRB_RO3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_RO3_SHIFT)) & AIPS_PACRB_RO3_MASK) 1627 1628 #define AIPS_PACRB_AC2_MASK (0x700000U) 1629 #define AIPS_PACRB_AC2_SHIFT (20U) 1630 /*! AC2 - Attribute Check 1631 */ 1632 #define AIPS_PACRB_AC2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_AC2_SHIFT)) & AIPS_PACRB_AC2_MASK) 1633 1634 #define AIPS_PACRB_RO2_MASK (0x800000U) 1635 #define AIPS_PACRB_RO2_SHIFT (23U) 1636 /*! RO2 - Read Only 1637 * 0b0..Writes to corresponding AC field are allowed. 1638 * 0b1..Writes to corresponding AC field are ignored. 1639 */ 1640 #define AIPS_PACRB_RO2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_RO2_SHIFT)) & AIPS_PACRB_RO2_MASK) 1641 1642 #define AIPS_PACRB_AC1_MASK (0x7000000U) 1643 #define AIPS_PACRB_AC1_SHIFT (24U) 1644 /*! AC1 - Attribute Check 1645 */ 1646 #define AIPS_PACRB_AC1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_AC1_SHIFT)) & AIPS_PACRB_AC1_MASK) 1647 1648 #define AIPS_PACRB_RO1_MASK (0x8000000U) 1649 #define AIPS_PACRB_RO1_SHIFT (27U) 1650 /*! RO1 - Read Only 1651 * 0b0..Writes to corresponding AC field are allowed. 1652 * 0b1..Writes to corresponding AC field are ignored. 1653 */ 1654 #define AIPS_PACRB_RO1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_RO1_SHIFT)) & AIPS_PACRB_RO1_MASK) 1655 1656 #define AIPS_PACRB_AC0_MASK (0x70000000U) 1657 #define AIPS_PACRB_AC0_SHIFT (28U) 1658 /*! AC0 - Attribute Check 1659 */ 1660 #define AIPS_PACRB_AC0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_AC0_SHIFT)) & AIPS_PACRB_AC0_MASK) 1661 1662 #define AIPS_PACRB_RO0_MASK (0x80000000U) 1663 #define AIPS_PACRB_RO0_SHIFT (31U) 1664 /*! RO0 - Read Only 1665 * 0b0..Writes to corresponding AC field are allowed. 1666 * 0b1..Writes to corresponding AC field are ignored. 1667 */ 1668 #define AIPS_PACRB_RO0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_RO0_SHIFT)) & AIPS_PACRB_RO0_MASK) 1669 /*! @} */ 1670 1671 /*! @name PACRE - Peripheral Access Control Register */ 1672 /*! @{ */ 1673 1674 #define AIPS_PACRE_AC7_MASK (0x7U) 1675 #define AIPS_PACRE_AC7_SHIFT (0U) 1676 /*! AC7 - Attribute Check 1677 */ 1678 #define AIPS_PACRE_AC7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_AC7_SHIFT)) & AIPS_PACRE_AC7_MASK) 1679 1680 #define AIPS_PACRE_RO7_MASK (0x8U) 1681 #define AIPS_PACRE_RO7_SHIFT (3U) 1682 /*! RO7 - Read Only 1683 * 0b0..Writes to corresponding AC field are allowed. 1684 * 0b1..Writes to corresponding AC field are ignored. 1685 */ 1686 #define AIPS_PACRE_RO7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_RO7_SHIFT)) & AIPS_PACRE_RO7_MASK) 1687 1688 #define AIPS_PACRE_AC6_MASK (0x70U) 1689 #define AIPS_PACRE_AC6_SHIFT (4U) 1690 /*! AC6 - Attribute Check 1691 */ 1692 #define AIPS_PACRE_AC6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_AC6_SHIFT)) & AIPS_PACRE_AC6_MASK) 1693 1694 #define AIPS_PACRE_RO6_MASK (0x80U) 1695 #define AIPS_PACRE_RO6_SHIFT (7U) 1696 /*! RO6 - Read Only 1697 * 0b0..Writes to corresponding AC field are allowed. 1698 * 0b1..Writes to corresponding AC field are ignored. 1699 */ 1700 #define AIPS_PACRE_RO6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_RO6_SHIFT)) & AIPS_PACRE_RO6_MASK) 1701 1702 #define AIPS_PACRE_AC5_MASK (0x700U) 1703 #define AIPS_PACRE_AC5_SHIFT (8U) 1704 /*! AC5 - Attribute Check 1705 */ 1706 #define AIPS_PACRE_AC5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_AC5_SHIFT)) & AIPS_PACRE_AC5_MASK) 1707 1708 #define AIPS_PACRE_RO5_MASK (0x800U) 1709 #define AIPS_PACRE_RO5_SHIFT (11U) 1710 /*! RO5 - Read Only 1711 * 0b0..Writes to corresponding AC field are allowed. 1712 * 0b1..Writes to corresponding AC field are ignored. 1713 */ 1714 #define AIPS_PACRE_RO5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_RO5_SHIFT)) & AIPS_PACRE_RO5_MASK) 1715 1716 #define AIPS_PACRE_AC4_MASK (0x7000U) 1717 #define AIPS_PACRE_AC4_SHIFT (12U) 1718 /*! AC4 - Attribute Check 1719 */ 1720 #define AIPS_PACRE_AC4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_AC4_SHIFT)) & AIPS_PACRE_AC4_MASK) 1721 1722 #define AIPS_PACRE_RO4_MASK (0x8000U) 1723 #define AIPS_PACRE_RO4_SHIFT (15U) 1724 /*! RO4 - Read Only 1725 * 0b0..Writes to corresponding AC field are allowed. 1726 * 0b1..Writes to corresponding AC field are ignored. 1727 */ 1728 #define AIPS_PACRE_RO4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_RO4_SHIFT)) & AIPS_PACRE_RO4_MASK) 1729 1730 #define AIPS_PACRE_AC3_MASK (0x70000U) 1731 #define AIPS_PACRE_AC3_SHIFT (16U) 1732 /*! AC3 - Attribute Check 1733 */ 1734 #define AIPS_PACRE_AC3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_AC3_SHIFT)) & AIPS_PACRE_AC3_MASK) 1735 1736 #define AIPS_PACRE_RO3_MASK (0x80000U) 1737 #define AIPS_PACRE_RO3_SHIFT (19U) 1738 /*! RO3 - Read Only 1739 * 0b0..Writes to corresponding AC field are allowed. 1740 * 0b1..Writes to corresponding AC field are ignored. 1741 */ 1742 #define AIPS_PACRE_RO3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_RO3_SHIFT)) & AIPS_PACRE_RO3_MASK) 1743 1744 #define AIPS_PACRE_AC2_MASK (0x700000U) 1745 #define AIPS_PACRE_AC2_SHIFT (20U) 1746 /*! AC2 - Attribute Check 1747 */ 1748 #define AIPS_PACRE_AC2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_AC2_SHIFT)) & AIPS_PACRE_AC2_MASK) 1749 1750 #define AIPS_PACRE_RO2_MASK (0x800000U) 1751 #define AIPS_PACRE_RO2_SHIFT (23U) 1752 /*! RO2 - Read Only 1753 * 0b0..Writes to corresponding AC field are allowed. 1754 * 0b1..Writes to corresponding AC field are ignored. 1755 */ 1756 #define AIPS_PACRE_RO2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_RO2_SHIFT)) & AIPS_PACRE_RO2_MASK) 1757 1758 #define AIPS_PACRE_AC1_MASK (0x7000000U) 1759 #define AIPS_PACRE_AC1_SHIFT (24U) 1760 /*! AC1 - Attribute Check 1761 */ 1762 #define AIPS_PACRE_AC1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_AC1_SHIFT)) & AIPS_PACRE_AC1_MASK) 1763 1764 #define AIPS_PACRE_RO1_MASK (0x8000000U) 1765 #define AIPS_PACRE_RO1_SHIFT (27U) 1766 /*! RO1 - Read Only 1767 * 0b0..Writes to corresponding AC field are allowed. 1768 * 0b1..Writes to corresponding AC field are ignored. 1769 */ 1770 #define AIPS_PACRE_RO1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_RO1_SHIFT)) & AIPS_PACRE_RO1_MASK) 1771 1772 #define AIPS_PACRE_AC0_MASK (0x70000000U) 1773 #define AIPS_PACRE_AC0_SHIFT (28U) 1774 /*! AC0 - Attribute Check 1775 */ 1776 #define AIPS_PACRE_AC0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_AC0_SHIFT)) & AIPS_PACRE_AC0_MASK) 1777 1778 #define AIPS_PACRE_RO0_MASK (0x80000000U) 1779 #define AIPS_PACRE_RO0_SHIFT (31U) 1780 /*! RO0 - Read Only 1781 * 0b0..Writes to corresponding AC field are allowed. 1782 * 0b1..Writes to corresponding AC field are ignored. 1783 */ 1784 #define AIPS_PACRE_RO0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_RO0_SHIFT)) & AIPS_PACRE_RO0_MASK) 1785 /*! @} */ 1786 1787 /*! @name PACRF - Peripheral Access Control Register */ 1788 /*! @{ */ 1789 1790 #define AIPS_PACRF_AC7_MASK (0x7U) 1791 #define AIPS_PACRF_AC7_SHIFT (0U) 1792 /*! AC7 - Attribute Check 1793 */ 1794 #define AIPS_PACRF_AC7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_AC7_SHIFT)) & AIPS_PACRF_AC7_MASK) 1795 1796 #define AIPS_PACRF_RO7_MASK (0x8U) 1797 #define AIPS_PACRF_RO7_SHIFT (3U) 1798 /*! RO7 - Read Only 1799 * 0b0..Writes to corresponding AC field are allowed. 1800 * 0b1..Writes to corresponding AC field are ignored. 1801 */ 1802 #define AIPS_PACRF_RO7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_RO7_SHIFT)) & AIPS_PACRF_RO7_MASK) 1803 1804 #define AIPS_PACRF_AC6_MASK (0x70U) 1805 #define AIPS_PACRF_AC6_SHIFT (4U) 1806 /*! AC6 - Attribute Check 1807 */ 1808 #define AIPS_PACRF_AC6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_AC6_SHIFT)) & AIPS_PACRF_AC6_MASK) 1809 1810 #define AIPS_PACRF_RO6_MASK (0x80U) 1811 #define AIPS_PACRF_RO6_SHIFT (7U) 1812 /*! RO6 - Read Only 1813 * 0b0..Writes to corresponding AC field are allowed. 1814 * 0b1..Writes to corresponding AC field are ignored. 1815 */ 1816 #define AIPS_PACRF_RO6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_RO6_SHIFT)) & AIPS_PACRF_RO6_MASK) 1817 1818 #define AIPS_PACRF_AC5_MASK (0x700U) 1819 #define AIPS_PACRF_AC5_SHIFT (8U) 1820 /*! AC5 - Attribute Check 1821 */ 1822 #define AIPS_PACRF_AC5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_AC5_SHIFT)) & AIPS_PACRF_AC5_MASK) 1823 1824 #define AIPS_PACRF_RO5_MASK (0x800U) 1825 #define AIPS_PACRF_RO5_SHIFT (11U) 1826 /*! RO5 - Read Only 1827 * 0b0..Writes to corresponding AC field are allowed. 1828 * 0b1..Writes to corresponding AC field are ignored. 1829 */ 1830 #define AIPS_PACRF_RO5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_RO5_SHIFT)) & AIPS_PACRF_RO5_MASK) 1831 1832 #define AIPS_PACRF_AC4_MASK (0x7000U) 1833 #define AIPS_PACRF_AC4_SHIFT (12U) 1834 /*! AC4 - Attribute Check 1835 */ 1836 #define AIPS_PACRF_AC4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_AC4_SHIFT)) & AIPS_PACRF_AC4_MASK) 1837 1838 #define AIPS_PACRF_RO4_MASK (0x8000U) 1839 #define AIPS_PACRF_RO4_SHIFT (15U) 1840 /*! RO4 - Read Only 1841 * 0b0..Writes to corresponding AC field are allowed. 1842 * 0b1..Writes to corresponding AC field are ignored. 1843 */ 1844 #define AIPS_PACRF_RO4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_RO4_SHIFT)) & AIPS_PACRF_RO4_MASK) 1845 1846 #define AIPS_PACRF_AC3_MASK (0x70000U) 1847 #define AIPS_PACRF_AC3_SHIFT (16U) 1848 /*! AC3 - Attribute Check 1849 */ 1850 #define AIPS_PACRF_AC3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_AC3_SHIFT)) & AIPS_PACRF_AC3_MASK) 1851 1852 #define AIPS_PACRF_RO3_MASK (0x80000U) 1853 #define AIPS_PACRF_RO3_SHIFT (19U) 1854 /*! RO3 - Read Only 1855 * 0b0..Writes to corresponding AC field are allowed. 1856 * 0b1..Writes to corresponding AC field are ignored. 1857 */ 1858 #define AIPS_PACRF_RO3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_RO3_SHIFT)) & AIPS_PACRF_RO3_MASK) 1859 1860 #define AIPS_PACRF_AC2_MASK (0x700000U) 1861 #define AIPS_PACRF_AC2_SHIFT (20U) 1862 /*! AC2 - Attribute Check 1863 */ 1864 #define AIPS_PACRF_AC2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_AC2_SHIFT)) & AIPS_PACRF_AC2_MASK) 1865 1866 #define AIPS_PACRF_RO2_MASK (0x800000U) 1867 #define AIPS_PACRF_RO2_SHIFT (23U) 1868 /*! RO2 - Read Only 1869 * 0b0..Writes to corresponding AC field are allowed. 1870 * 0b1..Writes to corresponding AC field are ignored. 1871 */ 1872 #define AIPS_PACRF_RO2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_RO2_SHIFT)) & AIPS_PACRF_RO2_MASK) 1873 1874 #define AIPS_PACRF_AC1_MASK (0x7000000U) 1875 #define AIPS_PACRF_AC1_SHIFT (24U) 1876 /*! AC1 - Attribute Check 1877 */ 1878 #define AIPS_PACRF_AC1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_AC1_SHIFT)) & AIPS_PACRF_AC1_MASK) 1879 1880 #define AIPS_PACRF_RO1_MASK (0x8000000U) 1881 #define AIPS_PACRF_RO1_SHIFT (27U) 1882 /*! RO1 - Read Only 1883 * 0b0..Writes to corresponding AC field are allowed. 1884 * 0b1..Writes to corresponding AC field are ignored. 1885 */ 1886 #define AIPS_PACRF_RO1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_RO1_SHIFT)) & AIPS_PACRF_RO1_MASK) 1887 1888 #define AIPS_PACRF_AC0_MASK (0x70000000U) 1889 #define AIPS_PACRF_AC0_SHIFT (28U) 1890 /*! AC0 - Attribute Check 1891 */ 1892 #define AIPS_PACRF_AC0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_AC0_SHIFT)) & AIPS_PACRF_AC0_MASK) 1893 1894 #define AIPS_PACRF_RO0_MASK (0x80000000U) 1895 #define AIPS_PACRF_RO0_SHIFT (31U) 1896 /*! RO0 - Read Only 1897 * 0b0..Writes to corresponding AC field are allowed. 1898 * 0b1..Writes to corresponding AC field are ignored. 1899 */ 1900 #define AIPS_PACRF_RO0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_RO0_SHIFT)) & AIPS_PACRF_RO0_MASK) 1901 /*! @} */ 1902 1903 /*! @name PACRG - Peripheral Access Control Register */ 1904 /*! @{ */ 1905 1906 #define AIPS_PACRG_AC7_MASK (0x7U) 1907 #define AIPS_PACRG_AC7_SHIFT (0U) 1908 /*! AC7 - Attribute Check 1909 */ 1910 #define AIPS_PACRG_AC7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_AC7_SHIFT)) & AIPS_PACRG_AC7_MASK) 1911 1912 #define AIPS_PACRG_RO7_MASK (0x8U) 1913 #define AIPS_PACRG_RO7_SHIFT (3U) 1914 /*! RO7 - Read Only 1915 * 0b0..Writes to corresponding AC field are allowed. 1916 * 0b1..Writes to corresponding AC field are ignored. 1917 */ 1918 #define AIPS_PACRG_RO7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_RO7_SHIFT)) & AIPS_PACRG_RO7_MASK) 1919 1920 #define AIPS_PACRG_AC6_MASK (0x70U) 1921 #define AIPS_PACRG_AC6_SHIFT (4U) 1922 /*! AC6 - Attribute Check 1923 */ 1924 #define AIPS_PACRG_AC6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_AC6_SHIFT)) & AIPS_PACRG_AC6_MASK) 1925 1926 #define AIPS_PACRG_RO6_MASK (0x80U) 1927 #define AIPS_PACRG_RO6_SHIFT (7U) 1928 /*! RO6 - Read Only 1929 * 0b0..Writes to corresponding AC field are allowed. 1930 * 0b1..Writes to corresponding AC field are ignored. 1931 */ 1932 #define AIPS_PACRG_RO6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_RO6_SHIFT)) & AIPS_PACRG_RO6_MASK) 1933 1934 #define AIPS_PACRG_AC5_MASK (0x700U) 1935 #define AIPS_PACRG_AC5_SHIFT (8U) 1936 /*! AC5 - Attribute Check 1937 */ 1938 #define AIPS_PACRG_AC5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_AC5_SHIFT)) & AIPS_PACRG_AC5_MASK) 1939 1940 #define AIPS_PACRG_RO5_MASK (0x800U) 1941 #define AIPS_PACRG_RO5_SHIFT (11U) 1942 /*! RO5 - Read Only 1943 * 0b0..Writes to corresponding AC field are allowed. 1944 * 0b1..Writes to corresponding AC field are ignored. 1945 */ 1946 #define AIPS_PACRG_RO5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_RO5_SHIFT)) & AIPS_PACRG_RO5_MASK) 1947 1948 #define AIPS_PACRG_AC4_MASK (0x7000U) 1949 #define AIPS_PACRG_AC4_SHIFT (12U) 1950 /*! AC4 - Attribute Check 1951 */ 1952 #define AIPS_PACRG_AC4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_AC4_SHIFT)) & AIPS_PACRG_AC4_MASK) 1953 1954 #define AIPS_PACRG_RO4_MASK (0x8000U) 1955 #define AIPS_PACRG_RO4_SHIFT (15U) 1956 /*! RO4 - Read Only 1957 * 0b0..Writes to corresponding AC field are allowed. 1958 * 0b1..Writes to corresponding AC field are ignored. 1959 */ 1960 #define AIPS_PACRG_RO4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_RO4_SHIFT)) & AIPS_PACRG_RO4_MASK) 1961 1962 #define AIPS_PACRG_AC3_MASK (0x70000U) 1963 #define AIPS_PACRG_AC3_SHIFT (16U) 1964 /*! AC3 - Attribute Check 1965 */ 1966 #define AIPS_PACRG_AC3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_AC3_SHIFT)) & AIPS_PACRG_AC3_MASK) 1967 1968 #define AIPS_PACRG_RO3_MASK (0x80000U) 1969 #define AIPS_PACRG_RO3_SHIFT (19U) 1970 /*! RO3 - Read Only 1971 * 0b0..Writes to corresponding AC field are allowed. 1972 * 0b1..Writes to corresponding AC field are ignored. 1973 */ 1974 #define AIPS_PACRG_RO3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_RO3_SHIFT)) & AIPS_PACRG_RO3_MASK) 1975 1976 #define AIPS_PACRG_AC2_MASK (0x700000U) 1977 #define AIPS_PACRG_AC2_SHIFT (20U) 1978 /*! AC2 - Attribute Check 1979 */ 1980 #define AIPS_PACRG_AC2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_AC2_SHIFT)) & AIPS_PACRG_AC2_MASK) 1981 1982 #define AIPS_PACRG_RO2_MASK (0x800000U) 1983 #define AIPS_PACRG_RO2_SHIFT (23U) 1984 /*! RO2 - Read Only 1985 * 0b0..Writes to corresponding AC field are allowed. 1986 * 0b1..Writes to corresponding AC field are ignored. 1987 */ 1988 #define AIPS_PACRG_RO2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_RO2_SHIFT)) & AIPS_PACRG_RO2_MASK) 1989 1990 #define AIPS_PACRG_AC1_MASK (0x7000000U) 1991 #define AIPS_PACRG_AC1_SHIFT (24U) 1992 /*! AC1 - Attribute Check 1993 */ 1994 #define AIPS_PACRG_AC1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_AC1_SHIFT)) & AIPS_PACRG_AC1_MASK) 1995 1996 #define AIPS_PACRG_RO1_MASK (0x8000000U) 1997 #define AIPS_PACRG_RO1_SHIFT (27U) 1998 /*! RO1 - Read Only 1999 * 0b0..Writes to corresponding AC field are allowed. 2000 * 0b1..Writes to corresponding AC field are ignored. 2001 */ 2002 #define AIPS_PACRG_RO1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_RO1_SHIFT)) & AIPS_PACRG_RO1_MASK) 2003 2004 #define AIPS_PACRG_AC0_MASK (0x70000000U) 2005 #define AIPS_PACRG_AC0_SHIFT (28U) 2006 /*! AC0 - Attribute Check 2007 */ 2008 #define AIPS_PACRG_AC0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_AC0_SHIFT)) & AIPS_PACRG_AC0_MASK) 2009 2010 #define AIPS_PACRG_RO0_MASK (0x80000000U) 2011 #define AIPS_PACRG_RO0_SHIFT (31U) 2012 /*! RO0 - Read Only 2013 * 0b0..Writes to corresponding AC field are allowed. 2014 * 0b1..Writes to corresponding AC field are ignored. 2015 */ 2016 #define AIPS_PACRG_RO0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_RO0_SHIFT)) & AIPS_PACRG_RO0_MASK) 2017 /*! @} */ 2018 2019 /*! @name PACRH - Peripheral Access Control Register */ 2020 /*! @{ */ 2021 2022 #define AIPS_PACRH_AC7_MASK (0x7U) 2023 #define AIPS_PACRH_AC7_SHIFT (0U) 2024 /*! AC7 - Attribute Check 2025 */ 2026 #define AIPS_PACRH_AC7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_AC7_SHIFT)) & AIPS_PACRH_AC7_MASK) 2027 2028 #define AIPS_PACRH_RO7_MASK (0x8U) 2029 #define AIPS_PACRH_RO7_SHIFT (3U) 2030 /*! RO7 - Read Only 2031 * 0b0..Writes to corresponding AC field are allowed. 2032 * 0b1..Writes to corresponding AC field are ignored. 2033 */ 2034 #define AIPS_PACRH_RO7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_RO7_SHIFT)) & AIPS_PACRH_RO7_MASK) 2035 2036 #define AIPS_PACRH_AC6_MASK (0x70U) 2037 #define AIPS_PACRH_AC6_SHIFT (4U) 2038 /*! AC6 - Attribute Check 2039 */ 2040 #define AIPS_PACRH_AC6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_AC6_SHIFT)) & AIPS_PACRH_AC6_MASK) 2041 2042 #define AIPS_PACRH_RO6_MASK (0x80U) 2043 #define AIPS_PACRH_RO6_SHIFT (7U) 2044 /*! RO6 - Read Only 2045 * 0b0..Writes to corresponding AC field are allowed. 2046 * 0b1..Writes to corresponding AC field are ignored. 2047 */ 2048 #define AIPS_PACRH_RO6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_RO6_SHIFT)) & AIPS_PACRH_RO6_MASK) 2049 2050 #define AIPS_PACRH_AC5_MASK (0x700U) 2051 #define AIPS_PACRH_AC5_SHIFT (8U) 2052 /*! AC5 - Attribute Check 2053 */ 2054 #define AIPS_PACRH_AC5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_AC5_SHIFT)) & AIPS_PACRH_AC5_MASK) 2055 2056 #define AIPS_PACRH_RO5_MASK (0x800U) 2057 #define AIPS_PACRH_RO5_SHIFT (11U) 2058 /*! RO5 - Read Only 2059 * 0b0..Writes to corresponding AC field are allowed. 2060 * 0b1..Writes to corresponding AC field are ignored. 2061 */ 2062 #define AIPS_PACRH_RO5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_RO5_SHIFT)) & AIPS_PACRH_RO5_MASK) 2063 2064 #define AIPS_PACRH_AC4_MASK (0x7000U) 2065 #define AIPS_PACRH_AC4_SHIFT (12U) 2066 /*! AC4 - Attribute Check 2067 */ 2068 #define AIPS_PACRH_AC4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_AC4_SHIFT)) & AIPS_PACRH_AC4_MASK) 2069 2070 #define AIPS_PACRH_RO4_MASK (0x8000U) 2071 #define AIPS_PACRH_RO4_SHIFT (15U) 2072 /*! RO4 - Read Only 2073 * 0b0..Writes to corresponding AC field are allowed. 2074 * 0b1..Writes to corresponding AC field are ignored. 2075 */ 2076 #define AIPS_PACRH_RO4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_RO4_SHIFT)) & AIPS_PACRH_RO4_MASK) 2077 2078 #define AIPS_PACRH_AC3_MASK (0x70000U) 2079 #define AIPS_PACRH_AC3_SHIFT (16U) 2080 /*! AC3 - Attribute Check 2081 */ 2082 #define AIPS_PACRH_AC3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_AC3_SHIFT)) & AIPS_PACRH_AC3_MASK) 2083 2084 #define AIPS_PACRH_RO3_MASK (0x80000U) 2085 #define AIPS_PACRH_RO3_SHIFT (19U) 2086 /*! RO3 - Read Only 2087 * 0b0..Writes to corresponding AC field are allowed. 2088 * 0b1..Writes to corresponding AC field are ignored. 2089 */ 2090 #define AIPS_PACRH_RO3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_RO3_SHIFT)) & AIPS_PACRH_RO3_MASK) 2091 2092 #define AIPS_PACRH_AC2_MASK (0x700000U) 2093 #define AIPS_PACRH_AC2_SHIFT (20U) 2094 /*! AC2 - Attribute Check 2095 */ 2096 #define AIPS_PACRH_AC2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_AC2_SHIFT)) & AIPS_PACRH_AC2_MASK) 2097 2098 #define AIPS_PACRH_RO2_MASK (0x800000U) 2099 #define AIPS_PACRH_RO2_SHIFT (23U) 2100 /*! RO2 - Read Only 2101 * 0b0..Writes to corresponding AC field are allowed. 2102 * 0b1..Writes to corresponding AC field are ignored. 2103 */ 2104 #define AIPS_PACRH_RO2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_RO2_SHIFT)) & AIPS_PACRH_RO2_MASK) 2105 2106 #define AIPS_PACRH_AC1_MASK (0x7000000U) 2107 #define AIPS_PACRH_AC1_SHIFT (24U) 2108 /*! AC1 - Attribute Check 2109 */ 2110 #define AIPS_PACRH_AC1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_AC1_SHIFT)) & AIPS_PACRH_AC1_MASK) 2111 2112 #define AIPS_PACRH_RO1_MASK (0x8000000U) 2113 #define AIPS_PACRH_RO1_SHIFT (27U) 2114 /*! RO1 - Read Only 2115 * 0b0..Writes to corresponding AC field are allowed. 2116 * 0b1..Writes to corresponding AC field are ignored. 2117 */ 2118 #define AIPS_PACRH_RO1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_RO1_SHIFT)) & AIPS_PACRH_RO1_MASK) 2119 2120 #define AIPS_PACRH_AC0_MASK (0x70000000U) 2121 #define AIPS_PACRH_AC0_SHIFT (28U) 2122 /*! AC0 - Attribute Check 2123 */ 2124 #define AIPS_PACRH_AC0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_AC0_SHIFT)) & AIPS_PACRH_AC0_MASK) 2125 2126 #define AIPS_PACRH_RO0_MASK (0x80000000U) 2127 #define AIPS_PACRH_RO0_SHIFT (31U) 2128 /*! RO0 - Read Only 2129 * 0b0..Writes to corresponding AC field are allowed. 2130 * 0b1..Writes to corresponding AC field are ignored. 2131 */ 2132 #define AIPS_PACRH_RO0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_RO0_SHIFT)) & AIPS_PACRH_RO0_MASK) 2133 /*! @} */ 2134 2135 /*! @name PACRI - Peripheral Access Control Register */ 2136 /*! @{ */ 2137 2138 #define AIPS_PACRI_AC7_MASK (0x7U) 2139 #define AIPS_PACRI_AC7_SHIFT (0U) 2140 /*! AC7 - Attribute Check 2141 */ 2142 #define AIPS_PACRI_AC7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_AC7_SHIFT)) & AIPS_PACRI_AC7_MASK) 2143 2144 #define AIPS_PACRI_RO7_MASK (0x8U) 2145 #define AIPS_PACRI_RO7_SHIFT (3U) 2146 /*! RO7 - Read Only 2147 * 0b0..Writes to corresponding AC field are allowed. 2148 * 0b1..Writes to corresponding AC field are ignored. 2149 */ 2150 #define AIPS_PACRI_RO7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_RO7_SHIFT)) & AIPS_PACRI_RO7_MASK) 2151 2152 #define AIPS_PACRI_AC6_MASK (0x70U) 2153 #define AIPS_PACRI_AC6_SHIFT (4U) 2154 /*! AC6 - Attribute Check 2155 */ 2156 #define AIPS_PACRI_AC6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_AC6_SHIFT)) & AIPS_PACRI_AC6_MASK) 2157 2158 #define AIPS_PACRI_RO6_MASK (0x80U) 2159 #define AIPS_PACRI_RO6_SHIFT (7U) 2160 /*! RO6 - Read Only 2161 * 0b0..Writes to corresponding AC field are allowed. 2162 * 0b1..Writes to corresponding AC field are ignored. 2163 */ 2164 #define AIPS_PACRI_RO6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_RO6_SHIFT)) & AIPS_PACRI_RO6_MASK) 2165 2166 #define AIPS_PACRI_AC5_MASK (0x700U) 2167 #define AIPS_PACRI_AC5_SHIFT (8U) 2168 /*! AC5 - Attribute Check 2169 */ 2170 #define AIPS_PACRI_AC5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_AC5_SHIFT)) & AIPS_PACRI_AC5_MASK) 2171 2172 #define AIPS_PACRI_RO5_MASK (0x800U) 2173 #define AIPS_PACRI_RO5_SHIFT (11U) 2174 /*! RO5 - Read Only 2175 * 0b0..Writes to corresponding AC field are allowed. 2176 * 0b1..Writes to corresponding AC field are ignored. 2177 */ 2178 #define AIPS_PACRI_RO5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_RO5_SHIFT)) & AIPS_PACRI_RO5_MASK) 2179 2180 #define AIPS_PACRI_AC4_MASK (0x7000U) 2181 #define AIPS_PACRI_AC4_SHIFT (12U) 2182 /*! AC4 - Attribute Check 2183 */ 2184 #define AIPS_PACRI_AC4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_AC4_SHIFT)) & AIPS_PACRI_AC4_MASK) 2185 2186 #define AIPS_PACRI_RO4_MASK (0x8000U) 2187 #define AIPS_PACRI_RO4_SHIFT (15U) 2188 /*! RO4 - Read Only 2189 * 0b0..Writes to corresponding AC field are allowed. 2190 * 0b1..Writes to corresponding AC field are ignored. 2191 */ 2192 #define AIPS_PACRI_RO4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_RO4_SHIFT)) & AIPS_PACRI_RO4_MASK) 2193 2194 #define AIPS_PACRI_AC3_MASK (0x70000U) 2195 #define AIPS_PACRI_AC3_SHIFT (16U) 2196 /*! AC3 - Attribute Check 2197 */ 2198 #define AIPS_PACRI_AC3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_AC3_SHIFT)) & AIPS_PACRI_AC3_MASK) 2199 2200 #define AIPS_PACRI_RO3_MASK (0x80000U) 2201 #define AIPS_PACRI_RO3_SHIFT (19U) 2202 /*! RO3 - Read Only 2203 * 0b0..Writes to corresponding AC field are allowed. 2204 * 0b1..Writes to corresponding AC field are ignored. 2205 */ 2206 #define AIPS_PACRI_RO3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_RO3_SHIFT)) & AIPS_PACRI_RO3_MASK) 2207 2208 #define AIPS_PACRI_AC2_MASK (0x700000U) 2209 #define AIPS_PACRI_AC2_SHIFT (20U) 2210 /*! AC2 - Attribute Check 2211 */ 2212 #define AIPS_PACRI_AC2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_AC2_SHIFT)) & AIPS_PACRI_AC2_MASK) 2213 2214 #define AIPS_PACRI_RO2_MASK (0x800000U) 2215 #define AIPS_PACRI_RO2_SHIFT (23U) 2216 /*! RO2 - Read Only 2217 * 0b0..Writes to corresponding AC field are allowed. 2218 * 0b1..Writes to corresponding AC field are ignored. 2219 */ 2220 #define AIPS_PACRI_RO2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_RO2_SHIFT)) & AIPS_PACRI_RO2_MASK) 2221 2222 #define AIPS_PACRI_AC1_MASK (0x7000000U) 2223 #define AIPS_PACRI_AC1_SHIFT (24U) 2224 /*! AC1 - Attribute Check 2225 */ 2226 #define AIPS_PACRI_AC1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_AC1_SHIFT)) & AIPS_PACRI_AC1_MASK) 2227 2228 #define AIPS_PACRI_RO1_MASK (0x8000000U) 2229 #define AIPS_PACRI_RO1_SHIFT (27U) 2230 /*! RO1 - Read Only 2231 * 0b0..Writes to corresponding AC field are allowed. 2232 * 0b1..Writes to corresponding AC field are ignored. 2233 */ 2234 #define AIPS_PACRI_RO1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_RO1_SHIFT)) & AIPS_PACRI_RO1_MASK) 2235 2236 #define AIPS_PACRI_AC0_MASK (0x70000000U) 2237 #define AIPS_PACRI_AC0_SHIFT (28U) 2238 /*! AC0 - Attribute Check 2239 */ 2240 #define AIPS_PACRI_AC0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_AC0_SHIFT)) & AIPS_PACRI_AC0_MASK) 2241 2242 #define AIPS_PACRI_RO0_MASK (0x80000000U) 2243 #define AIPS_PACRI_RO0_SHIFT (31U) 2244 /*! RO0 - Read Only 2245 * 0b0..Writes to corresponding AC field are allowed. 2246 * 0b1..Writes to corresponding AC field are ignored. 2247 */ 2248 #define AIPS_PACRI_RO0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_RO0_SHIFT)) & AIPS_PACRI_RO0_MASK) 2249 /*! @} */ 2250 2251 /*! @name PACRJ - Peripheral Access Control Register */ 2252 /*! @{ */ 2253 2254 #define AIPS_PACRJ_AC7_MASK (0x7U) 2255 #define AIPS_PACRJ_AC7_SHIFT (0U) 2256 /*! AC7 - Attribute Check 2257 */ 2258 #define AIPS_PACRJ_AC7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_AC7_SHIFT)) & AIPS_PACRJ_AC7_MASK) 2259 2260 #define AIPS_PACRJ_RO7_MASK (0x8U) 2261 #define AIPS_PACRJ_RO7_SHIFT (3U) 2262 /*! RO7 - Read Only 2263 * 0b0..Writes to corresponding AC field are allowed. 2264 * 0b1..Writes to corresponding AC field are ignored. 2265 */ 2266 #define AIPS_PACRJ_RO7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_RO7_SHIFT)) & AIPS_PACRJ_RO7_MASK) 2267 2268 #define AIPS_PACRJ_AC6_MASK (0x70U) 2269 #define AIPS_PACRJ_AC6_SHIFT (4U) 2270 /*! AC6 - Attribute Check 2271 */ 2272 #define AIPS_PACRJ_AC6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_AC6_SHIFT)) & AIPS_PACRJ_AC6_MASK) 2273 2274 #define AIPS_PACRJ_RO6_MASK (0x80U) 2275 #define AIPS_PACRJ_RO6_SHIFT (7U) 2276 /*! RO6 - Read Only 2277 * 0b0..Writes to corresponding AC field are allowed. 2278 * 0b1..Writes to corresponding AC field are ignored. 2279 */ 2280 #define AIPS_PACRJ_RO6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_RO6_SHIFT)) & AIPS_PACRJ_RO6_MASK) 2281 2282 #define AIPS_PACRJ_AC5_MASK (0x700U) 2283 #define AIPS_PACRJ_AC5_SHIFT (8U) 2284 /*! AC5 - Attribute Check 2285 */ 2286 #define AIPS_PACRJ_AC5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_AC5_SHIFT)) & AIPS_PACRJ_AC5_MASK) 2287 2288 #define AIPS_PACRJ_RO5_MASK (0x800U) 2289 #define AIPS_PACRJ_RO5_SHIFT (11U) 2290 /*! RO5 - Read Only 2291 * 0b0..Writes to corresponding AC field are allowed. 2292 * 0b1..Writes to corresponding AC field are ignored. 2293 */ 2294 #define AIPS_PACRJ_RO5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_RO5_SHIFT)) & AIPS_PACRJ_RO5_MASK) 2295 2296 #define AIPS_PACRJ_AC4_MASK (0x7000U) 2297 #define AIPS_PACRJ_AC4_SHIFT (12U) 2298 /*! AC4 - Attribute Check 2299 */ 2300 #define AIPS_PACRJ_AC4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_AC4_SHIFT)) & AIPS_PACRJ_AC4_MASK) 2301 2302 #define AIPS_PACRJ_RO4_MASK (0x8000U) 2303 #define AIPS_PACRJ_RO4_SHIFT (15U) 2304 /*! RO4 - Read Only 2305 * 0b0..Writes to corresponding AC field are allowed. 2306 * 0b1..Writes to corresponding AC field are ignored. 2307 */ 2308 #define AIPS_PACRJ_RO4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_RO4_SHIFT)) & AIPS_PACRJ_RO4_MASK) 2309 2310 #define AIPS_PACRJ_AC3_MASK (0x70000U) 2311 #define AIPS_PACRJ_AC3_SHIFT (16U) 2312 /*! AC3 - Attribute Check 2313 */ 2314 #define AIPS_PACRJ_AC3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_AC3_SHIFT)) & AIPS_PACRJ_AC3_MASK) 2315 2316 #define AIPS_PACRJ_RO3_MASK (0x80000U) 2317 #define AIPS_PACRJ_RO3_SHIFT (19U) 2318 /*! RO3 - Read Only 2319 * 0b0..Writes to corresponding AC field are allowed. 2320 * 0b1..Writes to corresponding AC field are ignored. 2321 */ 2322 #define AIPS_PACRJ_RO3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_RO3_SHIFT)) & AIPS_PACRJ_RO3_MASK) 2323 2324 #define AIPS_PACRJ_AC2_MASK (0x700000U) 2325 #define AIPS_PACRJ_AC2_SHIFT (20U) 2326 /*! AC2 - Attribute Check 2327 */ 2328 #define AIPS_PACRJ_AC2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_AC2_SHIFT)) & AIPS_PACRJ_AC2_MASK) 2329 2330 #define AIPS_PACRJ_RO2_MASK (0x800000U) 2331 #define AIPS_PACRJ_RO2_SHIFT (23U) 2332 /*! RO2 - Read Only 2333 * 0b0..Writes to corresponding AC field are allowed. 2334 * 0b1..Writes to corresponding AC field are ignored. 2335 */ 2336 #define AIPS_PACRJ_RO2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_RO2_SHIFT)) & AIPS_PACRJ_RO2_MASK) 2337 2338 #define AIPS_PACRJ_AC1_MASK (0x7000000U) 2339 #define AIPS_PACRJ_AC1_SHIFT (24U) 2340 /*! AC1 - Attribute Check 2341 */ 2342 #define AIPS_PACRJ_AC1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_AC1_SHIFT)) & AIPS_PACRJ_AC1_MASK) 2343 2344 #define AIPS_PACRJ_RO1_MASK (0x8000000U) 2345 #define AIPS_PACRJ_RO1_SHIFT (27U) 2346 /*! RO1 - Read Only 2347 * 0b0..Writes to corresponding AC field are allowed. 2348 * 0b1..Writes to corresponding AC field are ignored. 2349 */ 2350 #define AIPS_PACRJ_RO1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_RO1_SHIFT)) & AIPS_PACRJ_RO1_MASK) 2351 2352 #define AIPS_PACRJ_AC0_MASK (0x70000000U) 2353 #define AIPS_PACRJ_AC0_SHIFT (28U) 2354 /*! AC0 - Attribute Check 2355 */ 2356 #define AIPS_PACRJ_AC0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_AC0_SHIFT)) & AIPS_PACRJ_AC0_MASK) 2357 2358 #define AIPS_PACRJ_RO0_MASK (0x80000000U) 2359 #define AIPS_PACRJ_RO0_SHIFT (31U) 2360 /*! RO0 - Read Only 2361 * 0b0..Writes to corresponding AC field are allowed. 2362 * 0b1..Writes to corresponding AC field are ignored. 2363 */ 2364 #define AIPS_PACRJ_RO0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_RO0_SHIFT)) & AIPS_PACRJ_RO0_MASK) 2365 /*! @} */ 2366 2367 /*! @name PACRK - Peripheral Access Control Register */ 2368 /*! @{ */ 2369 2370 #define AIPS_PACRK_AC7_MASK (0x7U) 2371 #define AIPS_PACRK_AC7_SHIFT (0U) 2372 /*! AC7 - Attribute Check 2373 */ 2374 #define AIPS_PACRK_AC7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_AC7_SHIFT)) & AIPS_PACRK_AC7_MASK) 2375 2376 #define AIPS_PACRK_RO7_MASK (0x8U) 2377 #define AIPS_PACRK_RO7_SHIFT (3U) 2378 /*! RO7 - Read Only 2379 * 0b0..Writes to corresponding AC field are allowed. 2380 * 0b1..Writes to corresponding AC field are ignored. 2381 */ 2382 #define AIPS_PACRK_RO7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_RO7_SHIFT)) & AIPS_PACRK_RO7_MASK) 2383 2384 #define AIPS_PACRK_AC6_MASK (0x70U) 2385 #define AIPS_PACRK_AC6_SHIFT (4U) 2386 /*! AC6 - Attribute Check 2387 */ 2388 #define AIPS_PACRK_AC6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_AC6_SHIFT)) & AIPS_PACRK_AC6_MASK) 2389 2390 #define AIPS_PACRK_RO6_MASK (0x80U) 2391 #define AIPS_PACRK_RO6_SHIFT (7U) 2392 /*! RO6 - Read Only 2393 * 0b0..Writes to corresponding AC field are allowed. 2394 * 0b1..Writes to corresponding AC field are ignored. 2395 */ 2396 #define AIPS_PACRK_RO6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_RO6_SHIFT)) & AIPS_PACRK_RO6_MASK) 2397 2398 #define AIPS_PACRK_AC5_MASK (0x700U) 2399 #define AIPS_PACRK_AC5_SHIFT (8U) 2400 /*! AC5 - Attribute Check 2401 */ 2402 #define AIPS_PACRK_AC5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_AC5_SHIFT)) & AIPS_PACRK_AC5_MASK) 2403 2404 #define AIPS_PACRK_RO5_MASK (0x800U) 2405 #define AIPS_PACRK_RO5_SHIFT (11U) 2406 /*! RO5 - Read Only 2407 * 0b0..Writes to corresponding AC field are allowed. 2408 * 0b1..Writes to corresponding AC field are ignored. 2409 */ 2410 #define AIPS_PACRK_RO5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_RO5_SHIFT)) & AIPS_PACRK_RO5_MASK) 2411 2412 #define AIPS_PACRK_AC4_MASK (0x7000U) 2413 #define AIPS_PACRK_AC4_SHIFT (12U) 2414 /*! AC4 - Attribute Check 2415 */ 2416 #define AIPS_PACRK_AC4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_AC4_SHIFT)) & AIPS_PACRK_AC4_MASK) 2417 2418 #define AIPS_PACRK_RO4_MASK (0x8000U) 2419 #define AIPS_PACRK_RO4_SHIFT (15U) 2420 /*! RO4 - Read Only 2421 * 0b0..Writes to corresponding AC field are allowed. 2422 * 0b1..Writes to corresponding AC field are ignored. 2423 */ 2424 #define AIPS_PACRK_RO4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_RO4_SHIFT)) & AIPS_PACRK_RO4_MASK) 2425 2426 #define AIPS_PACRK_AC3_MASK (0x70000U) 2427 #define AIPS_PACRK_AC3_SHIFT (16U) 2428 /*! AC3 - Attribute Check 2429 */ 2430 #define AIPS_PACRK_AC3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_AC3_SHIFT)) & AIPS_PACRK_AC3_MASK) 2431 2432 #define AIPS_PACRK_RO3_MASK (0x80000U) 2433 #define AIPS_PACRK_RO3_SHIFT (19U) 2434 /*! RO3 - Read Only 2435 * 0b0..Writes to corresponding AC field are allowed. 2436 * 0b1..Writes to corresponding AC field are ignored. 2437 */ 2438 #define AIPS_PACRK_RO3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_RO3_SHIFT)) & AIPS_PACRK_RO3_MASK) 2439 2440 #define AIPS_PACRK_AC2_MASK (0x700000U) 2441 #define AIPS_PACRK_AC2_SHIFT (20U) 2442 /*! AC2 - Attribute Check 2443 */ 2444 #define AIPS_PACRK_AC2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_AC2_SHIFT)) & AIPS_PACRK_AC2_MASK) 2445 2446 #define AIPS_PACRK_RO2_MASK (0x800000U) 2447 #define AIPS_PACRK_RO2_SHIFT (23U) 2448 /*! RO2 - Read Only 2449 * 0b0..Writes to corresponding AC field are allowed. 2450 * 0b1..Writes to corresponding AC field are ignored. 2451 */ 2452 #define AIPS_PACRK_RO2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_RO2_SHIFT)) & AIPS_PACRK_RO2_MASK) 2453 2454 #define AIPS_PACRK_AC1_MASK (0x7000000U) 2455 #define AIPS_PACRK_AC1_SHIFT (24U) 2456 /*! AC1 - Attribute Check 2457 */ 2458 #define AIPS_PACRK_AC1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_AC1_SHIFT)) & AIPS_PACRK_AC1_MASK) 2459 2460 #define AIPS_PACRK_RO1_MASK (0x8000000U) 2461 #define AIPS_PACRK_RO1_SHIFT (27U) 2462 /*! RO1 - Read Only 2463 * 0b0..Writes to corresponding AC field are allowed. 2464 * 0b1..Writes to corresponding AC field are ignored. 2465 */ 2466 #define AIPS_PACRK_RO1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_RO1_SHIFT)) & AIPS_PACRK_RO1_MASK) 2467 2468 #define AIPS_PACRK_AC0_MASK (0x70000000U) 2469 #define AIPS_PACRK_AC0_SHIFT (28U) 2470 /*! AC0 - Attribute Check 2471 */ 2472 #define AIPS_PACRK_AC0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_AC0_SHIFT)) & AIPS_PACRK_AC0_MASK) 2473 2474 #define AIPS_PACRK_RO0_MASK (0x80000000U) 2475 #define AIPS_PACRK_RO0_SHIFT (31U) 2476 /*! RO0 - Read Only 2477 * 0b0..Writes to corresponding AC field are allowed. 2478 * 0b1..Writes to corresponding AC field are ignored. 2479 */ 2480 #define AIPS_PACRK_RO0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_RO0_SHIFT)) & AIPS_PACRK_RO0_MASK) 2481 /*! @} */ 2482 2483 /*! @name PACRL - Peripheral Access Control Register */ 2484 /*! @{ */ 2485 2486 #define AIPS_PACRL_AC7_MASK (0x7U) 2487 #define AIPS_PACRL_AC7_SHIFT (0U) 2488 /*! AC7 - Attribute Check 2489 */ 2490 #define AIPS_PACRL_AC7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_AC7_SHIFT)) & AIPS_PACRL_AC7_MASK) 2491 2492 #define AIPS_PACRL_RO7_MASK (0x8U) 2493 #define AIPS_PACRL_RO7_SHIFT (3U) 2494 /*! RO7 - Read Only 2495 * 0b0..Writes to corresponding AC field are allowed. 2496 * 0b1..Writes to corresponding AC field are ignored. 2497 */ 2498 #define AIPS_PACRL_RO7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_RO7_SHIFT)) & AIPS_PACRL_RO7_MASK) 2499 2500 #define AIPS_PACRL_AC6_MASK (0x70U) 2501 #define AIPS_PACRL_AC6_SHIFT (4U) 2502 /*! AC6 - Attribute Check 2503 */ 2504 #define AIPS_PACRL_AC6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_AC6_SHIFT)) & AIPS_PACRL_AC6_MASK) 2505 2506 #define AIPS_PACRL_RO6_MASK (0x80U) 2507 #define AIPS_PACRL_RO6_SHIFT (7U) 2508 /*! RO6 - Read Only 2509 * 0b0..Writes to corresponding AC field are allowed. 2510 * 0b1..Writes to corresponding AC field are ignored. 2511 */ 2512 #define AIPS_PACRL_RO6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_RO6_SHIFT)) & AIPS_PACRL_RO6_MASK) 2513 2514 #define AIPS_PACRL_AC5_MASK (0x700U) 2515 #define AIPS_PACRL_AC5_SHIFT (8U) 2516 /*! AC5 - Attribute Check 2517 */ 2518 #define AIPS_PACRL_AC5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_AC5_SHIFT)) & AIPS_PACRL_AC5_MASK) 2519 2520 #define AIPS_PACRL_RO5_MASK (0x800U) 2521 #define AIPS_PACRL_RO5_SHIFT (11U) 2522 /*! RO5 - Read Only 2523 * 0b0..Writes to corresponding AC field are allowed. 2524 * 0b1..Writes to corresponding AC field are ignored. 2525 */ 2526 #define AIPS_PACRL_RO5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_RO5_SHIFT)) & AIPS_PACRL_RO5_MASK) 2527 2528 #define AIPS_PACRL_AC4_MASK (0x7000U) 2529 #define AIPS_PACRL_AC4_SHIFT (12U) 2530 /*! AC4 - Attribute Check 2531 */ 2532 #define AIPS_PACRL_AC4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_AC4_SHIFT)) & AIPS_PACRL_AC4_MASK) 2533 2534 #define AIPS_PACRL_RO4_MASK (0x8000U) 2535 #define AIPS_PACRL_RO4_SHIFT (15U) 2536 /*! RO4 - Read Only 2537 * 0b0..Writes to corresponding AC field are allowed. 2538 * 0b1..Writes to corresponding AC field are ignored. 2539 */ 2540 #define AIPS_PACRL_RO4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_RO4_SHIFT)) & AIPS_PACRL_RO4_MASK) 2541 2542 #define AIPS_PACRL_AC3_MASK (0x70000U) 2543 #define AIPS_PACRL_AC3_SHIFT (16U) 2544 /*! AC3 - Attribute Check 2545 */ 2546 #define AIPS_PACRL_AC3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_AC3_SHIFT)) & AIPS_PACRL_AC3_MASK) 2547 2548 #define AIPS_PACRL_RO3_MASK (0x80000U) 2549 #define AIPS_PACRL_RO3_SHIFT (19U) 2550 /*! RO3 - Read Only 2551 * 0b0..Writes to corresponding AC field are allowed. 2552 * 0b1..Writes to corresponding AC field are ignored. 2553 */ 2554 #define AIPS_PACRL_RO3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_RO3_SHIFT)) & AIPS_PACRL_RO3_MASK) 2555 2556 #define AIPS_PACRL_AC2_MASK (0x700000U) 2557 #define AIPS_PACRL_AC2_SHIFT (20U) 2558 /*! AC2 - Attribute Check 2559 */ 2560 #define AIPS_PACRL_AC2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_AC2_SHIFT)) & AIPS_PACRL_AC2_MASK) 2561 2562 #define AIPS_PACRL_RO2_MASK (0x800000U) 2563 #define AIPS_PACRL_RO2_SHIFT (23U) 2564 /*! RO2 - Read Only 2565 * 0b0..Writes to corresponding AC field are allowed. 2566 * 0b1..Writes to corresponding AC field are ignored. 2567 */ 2568 #define AIPS_PACRL_RO2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_RO2_SHIFT)) & AIPS_PACRL_RO2_MASK) 2569 2570 #define AIPS_PACRL_AC1_MASK (0x7000000U) 2571 #define AIPS_PACRL_AC1_SHIFT (24U) 2572 /*! AC1 - Attribute Check 2573 */ 2574 #define AIPS_PACRL_AC1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_AC1_SHIFT)) & AIPS_PACRL_AC1_MASK) 2575 2576 #define AIPS_PACRL_RO1_MASK (0x8000000U) 2577 #define AIPS_PACRL_RO1_SHIFT (27U) 2578 /*! RO1 - Read Only 2579 * 0b0..Writes to corresponding AC field are allowed. 2580 * 0b1..Writes to corresponding AC field are ignored. 2581 */ 2582 #define AIPS_PACRL_RO1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_RO1_SHIFT)) & AIPS_PACRL_RO1_MASK) 2583 2584 #define AIPS_PACRL_AC0_MASK (0x70000000U) 2585 #define AIPS_PACRL_AC0_SHIFT (28U) 2586 /*! AC0 - Attribute Check 2587 */ 2588 #define AIPS_PACRL_AC0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_AC0_SHIFT)) & AIPS_PACRL_AC0_MASK) 2589 2590 #define AIPS_PACRL_RO0_MASK (0x80000000U) 2591 #define AIPS_PACRL_RO0_SHIFT (31U) 2592 /*! RO0 - Read Only 2593 * 0b0..Writes to corresponding AC field are allowed. 2594 * 0b1..Writes to corresponding AC field are ignored. 2595 */ 2596 #define AIPS_PACRL_RO0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_RO0_SHIFT)) & AIPS_PACRL_RO0_MASK) 2597 /*! @} */ 2598 2599 /*! @name PACRM - Peripheral Access Control Register */ 2600 /*! @{ */ 2601 2602 #define AIPS_PACRM_AC7_MASK (0x7U) 2603 #define AIPS_PACRM_AC7_SHIFT (0U) 2604 /*! AC7 - Attribute Check 2605 */ 2606 #define AIPS_PACRM_AC7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_AC7_SHIFT)) & AIPS_PACRM_AC7_MASK) 2607 2608 #define AIPS_PACRM_RO7_MASK (0x8U) 2609 #define AIPS_PACRM_RO7_SHIFT (3U) 2610 /*! RO7 - Read Only 2611 * 0b0..Writes to corresponding AC field are allowed. 2612 * 0b1..Writes to corresponding AC field are ignored. 2613 */ 2614 #define AIPS_PACRM_RO7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_RO7_SHIFT)) & AIPS_PACRM_RO7_MASK) 2615 2616 #define AIPS_PACRM_AC6_MASK (0x70U) 2617 #define AIPS_PACRM_AC6_SHIFT (4U) 2618 /*! AC6 - Attribute Check 2619 */ 2620 #define AIPS_PACRM_AC6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_AC6_SHIFT)) & AIPS_PACRM_AC6_MASK) 2621 2622 #define AIPS_PACRM_RO6_MASK (0x80U) 2623 #define AIPS_PACRM_RO6_SHIFT (7U) 2624 /*! RO6 - Read Only 2625 * 0b0..Writes to corresponding AC field are allowed. 2626 * 0b1..Writes to corresponding AC field are ignored. 2627 */ 2628 #define AIPS_PACRM_RO6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_RO6_SHIFT)) & AIPS_PACRM_RO6_MASK) 2629 2630 #define AIPS_PACRM_AC5_MASK (0x700U) 2631 #define AIPS_PACRM_AC5_SHIFT (8U) 2632 /*! AC5 - Attribute Check 2633 */ 2634 #define AIPS_PACRM_AC5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_AC5_SHIFT)) & AIPS_PACRM_AC5_MASK) 2635 2636 #define AIPS_PACRM_RO5_MASK (0x800U) 2637 #define AIPS_PACRM_RO5_SHIFT (11U) 2638 /*! RO5 - Read Only 2639 * 0b0..Writes to corresponding AC field are allowed. 2640 * 0b1..Writes to corresponding AC field are ignored. 2641 */ 2642 #define AIPS_PACRM_RO5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_RO5_SHIFT)) & AIPS_PACRM_RO5_MASK) 2643 2644 #define AIPS_PACRM_AC4_MASK (0x7000U) 2645 #define AIPS_PACRM_AC4_SHIFT (12U) 2646 /*! AC4 - Attribute Check 2647 */ 2648 #define AIPS_PACRM_AC4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_AC4_SHIFT)) & AIPS_PACRM_AC4_MASK) 2649 2650 #define AIPS_PACRM_RO4_MASK (0x8000U) 2651 #define AIPS_PACRM_RO4_SHIFT (15U) 2652 /*! RO4 - Read Only 2653 * 0b0..Writes to corresponding AC field are allowed. 2654 * 0b1..Writes to corresponding AC field are ignored. 2655 */ 2656 #define AIPS_PACRM_RO4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_RO4_SHIFT)) & AIPS_PACRM_RO4_MASK) 2657 2658 #define AIPS_PACRM_AC3_MASK (0x70000U) 2659 #define AIPS_PACRM_AC3_SHIFT (16U) 2660 /*! AC3 - Attribute Check 2661 */ 2662 #define AIPS_PACRM_AC3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_AC3_SHIFT)) & AIPS_PACRM_AC3_MASK) 2663 2664 #define AIPS_PACRM_RO3_MASK (0x80000U) 2665 #define AIPS_PACRM_RO3_SHIFT (19U) 2666 /*! RO3 - Read Only 2667 * 0b0..Writes to corresponding AC field are allowed. 2668 * 0b1..Writes to corresponding AC field are ignored. 2669 */ 2670 #define AIPS_PACRM_RO3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_RO3_SHIFT)) & AIPS_PACRM_RO3_MASK) 2671 2672 #define AIPS_PACRM_AC2_MASK (0x700000U) 2673 #define AIPS_PACRM_AC2_SHIFT (20U) 2674 /*! AC2 - Attribute Check 2675 */ 2676 #define AIPS_PACRM_AC2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_AC2_SHIFT)) & AIPS_PACRM_AC2_MASK) 2677 2678 #define AIPS_PACRM_RO2_MASK (0x800000U) 2679 #define AIPS_PACRM_RO2_SHIFT (23U) 2680 /*! RO2 - Read Only 2681 * 0b0..Writes to corresponding AC field are allowed. 2682 * 0b1..Writes to corresponding AC field are ignored. 2683 */ 2684 #define AIPS_PACRM_RO2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_RO2_SHIFT)) & AIPS_PACRM_RO2_MASK) 2685 2686 #define AIPS_PACRM_AC1_MASK (0x7000000U) 2687 #define AIPS_PACRM_AC1_SHIFT (24U) 2688 /*! AC1 - Attribute Check 2689 */ 2690 #define AIPS_PACRM_AC1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_AC1_SHIFT)) & AIPS_PACRM_AC1_MASK) 2691 2692 #define AIPS_PACRM_RO1_MASK (0x8000000U) 2693 #define AIPS_PACRM_RO1_SHIFT (27U) 2694 /*! RO1 - Read Only 2695 * 0b0..Writes to corresponding AC field are allowed. 2696 * 0b1..Writes to corresponding AC field are ignored. 2697 */ 2698 #define AIPS_PACRM_RO1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_RO1_SHIFT)) & AIPS_PACRM_RO1_MASK) 2699 2700 #define AIPS_PACRM_AC0_MASK (0x70000000U) 2701 #define AIPS_PACRM_AC0_SHIFT (28U) 2702 /*! AC0 - Attribute Check 2703 */ 2704 #define AIPS_PACRM_AC0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_AC0_SHIFT)) & AIPS_PACRM_AC0_MASK) 2705 2706 #define AIPS_PACRM_RO0_MASK (0x80000000U) 2707 #define AIPS_PACRM_RO0_SHIFT (31U) 2708 /*! RO0 - Read Only 2709 * 0b0..Writes to corresponding AC field are allowed. 2710 * 0b1..Writes to corresponding AC field are ignored. 2711 */ 2712 #define AIPS_PACRM_RO0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_RO0_SHIFT)) & AIPS_PACRM_RO0_MASK) 2713 /*! @} */ 2714 2715 /*! @name PACRN - Peripheral Access Control Register */ 2716 /*! @{ */ 2717 2718 #define AIPS_PACRN_AC7_MASK (0x7U) 2719 #define AIPS_PACRN_AC7_SHIFT (0U) 2720 /*! AC7 - Attribute Check 2721 */ 2722 #define AIPS_PACRN_AC7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_AC7_SHIFT)) & AIPS_PACRN_AC7_MASK) 2723 2724 #define AIPS_PACRN_RO7_MASK (0x8U) 2725 #define AIPS_PACRN_RO7_SHIFT (3U) 2726 /*! RO7 - Read Only 2727 * 0b0..Writes to corresponding AC field are allowed. 2728 * 0b1..Writes to corresponding AC field are ignored. 2729 */ 2730 #define AIPS_PACRN_RO7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_RO7_SHIFT)) & AIPS_PACRN_RO7_MASK) 2731 2732 #define AIPS_PACRN_AC6_MASK (0x70U) 2733 #define AIPS_PACRN_AC6_SHIFT (4U) 2734 /*! AC6 - Attribute Check 2735 */ 2736 #define AIPS_PACRN_AC6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_AC6_SHIFT)) & AIPS_PACRN_AC6_MASK) 2737 2738 #define AIPS_PACRN_RO6_MASK (0x80U) 2739 #define AIPS_PACRN_RO6_SHIFT (7U) 2740 /*! RO6 - Read Only 2741 * 0b0..Writes to corresponding AC field are allowed. 2742 * 0b1..Writes to corresponding AC field are ignored. 2743 */ 2744 #define AIPS_PACRN_RO6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_RO6_SHIFT)) & AIPS_PACRN_RO6_MASK) 2745 2746 #define AIPS_PACRN_AC5_MASK (0x700U) 2747 #define AIPS_PACRN_AC5_SHIFT (8U) 2748 /*! AC5 - Attribute Check 2749 */ 2750 #define AIPS_PACRN_AC5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_AC5_SHIFT)) & AIPS_PACRN_AC5_MASK) 2751 2752 #define AIPS_PACRN_RO5_MASK (0x800U) 2753 #define AIPS_PACRN_RO5_SHIFT (11U) 2754 /*! RO5 - Read Only 2755 * 0b0..Writes to corresponding AC field are allowed. 2756 * 0b1..Writes to corresponding AC field are ignored. 2757 */ 2758 #define AIPS_PACRN_RO5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_RO5_SHIFT)) & AIPS_PACRN_RO5_MASK) 2759 2760 #define AIPS_PACRN_AC4_MASK (0x7000U) 2761 #define AIPS_PACRN_AC4_SHIFT (12U) 2762 /*! AC4 - Attribute Check 2763 */ 2764 #define AIPS_PACRN_AC4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_AC4_SHIFT)) & AIPS_PACRN_AC4_MASK) 2765 2766 #define AIPS_PACRN_RO4_MASK (0x8000U) 2767 #define AIPS_PACRN_RO4_SHIFT (15U) 2768 /*! RO4 - Read Only 2769 * 0b0..Writes to corresponding AC field are allowed. 2770 * 0b1..Writes to corresponding AC field are ignored. 2771 */ 2772 #define AIPS_PACRN_RO4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_RO4_SHIFT)) & AIPS_PACRN_RO4_MASK) 2773 2774 #define AIPS_PACRN_AC3_MASK (0x70000U) 2775 #define AIPS_PACRN_AC3_SHIFT (16U) 2776 /*! AC3 - Attribute Check 2777 */ 2778 #define AIPS_PACRN_AC3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_AC3_SHIFT)) & AIPS_PACRN_AC3_MASK) 2779 2780 #define AIPS_PACRN_RO3_MASK (0x80000U) 2781 #define AIPS_PACRN_RO3_SHIFT (19U) 2782 /*! RO3 - Read Only 2783 * 0b0..Writes to corresponding AC field are allowed. 2784 * 0b1..Writes to corresponding AC field are ignored. 2785 */ 2786 #define AIPS_PACRN_RO3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_RO3_SHIFT)) & AIPS_PACRN_RO3_MASK) 2787 2788 #define AIPS_PACRN_AC2_MASK (0x700000U) 2789 #define AIPS_PACRN_AC2_SHIFT (20U) 2790 /*! AC2 - Attribute Check 2791 */ 2792 #define AIPS_PACRN_AC2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_AC2_SHIFT)) & AIPS_PACRN_AC2_MASK) 2793 2794 #define AIPS_PACRN_RO2_MASK (0x800000U) 2795 #define AIPS_PACRN_RO2_SHIFT (23U) 2796 /*! RO2 - Read Only 2797 * 0b0..Writes to corresponding AC field are allowed. 2798 * 0b1..Writes to corresponding AC field are ignored. 2799 */ 2800 #define AIPS_PACRN_RO2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_RO2_SHIFT)) & AIPS_PACRN_RO2_MASK) 2801 2802 #define AIPS_PACRN_AC1_MASK (0x7000000U) 2803 #define AIPS_PACRN_AC1_SHIFT (24U) 2804 /*! AC1 - Attribute Check 2805 */ 2806 #define AIPS_PACRN_AC1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_AC1_SHIFT)) & AIPS_PACRN_AC1_MASK) 2807 2808 #define AIPS_PACRN_RO1_MASK (0x8000000U) 2809 #define AIPS_PACRN_RO1_SHIFT (27U) 2810 /*! RO1 - Read Only 2811 * 0b0..Writes to corresponding AC field are allowed. 2812 * 0b1..Writes to corresponding AC field are ignored. 2813 */ 2814 #define AIPS_PACRN_RO1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_RO1_SHIFT)) & AIPS_PACRN_RO1_MASK) 2815 2816 #define AIPS_PACRN_AC0_MASK (0x70000000U) 2817 #define AIPS_PACRN_AC0_SHIFT (28U) 2818 /*! AC0 - Attribute Check 2819 */ 2820 #define AIPS_PACRN_AC0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_AC0_SHIFT)) & AIPS_PACRN_AC0_MASK) 2821 2822 #define AIPS_PACRN_RO0_MASK (0x80000000U) 2823 #define AIPS_PACRN_RO0_SHIFT (31U) 2824 /*! RO0 - Read Only 2825 * 0b0..Writes to corresponding AC field are allowed. 2826 * 0b1..Writes to corresponding AC field are ignored. 2827 */ 2828 #define AIPS_PACRN_RO0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_RO0_SHIFT)) & AIPS_PACRN_RO0_MASK) 2829 /*! @} */ 2830 2831 /*! @name PACRO - Peripheral Access Control Register */ 2832 /*! @{ */ 2833 2834 #define AIPS_PACRO_AC7_MASK (0x7U) 2835 #define AIPS_PACRO_AC7_SHIFT (0U) 2836 /*! AC7 - Attribute Check 2837 */ 2838 #define AIPS_PACRO_AC7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_AC7_SHIFT)) & AIPS_PACRO_AC7_MASK) 2839 2840 #define AIPS_PACRO_RO7_MASK (0x8U) 2841 #define AIPS_PACRO_RO7_SHIFT (3U) 2842 /*! RO7 - Read Only 2843 * 0b0..Writes to corresponding AC field are allowed. 2844 * 0b1..Writes to corresponding AC field are ignored. 2845 */ 2846 #define AIPS_PACRO_RO7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_RO7_SHIFT)) & AIPS_PACRO_RO7_MASK) 2847 2848 #define AIPS_PACRO_AC6_MASK (0x70U) 2849 #define AIPS_PACRO_AC6_SHIFT (4U) 2850 /*! AC6 - Attribute Check 2851 */ 2852 #define AIPS_PACRO_AC6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_AC6_SHIFT)) & AIPS_PACRO_AC6_MASK) 2853 2854 #define AIPS_PACRO_RO6_MASK (0x80U) 2855 #define AIPS_PACRO_RO6_SHIFT (7U) 2856 /*! RO6 - Read Only 2857 * 0b0..Writes to corresponding AC field are allowed. 2858 * 0b1..Writes to corresponding AC field are ignored. 2859 */ 2860 #define AIPS_PACRO_RO6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_RO6_SHIFT)) & AIPS_PACRO_RO6_MASK) 2861 2862 #define AIPS_PACRO_AC5_MASK (0x700U) 2863 #define AIPS_PACRO_AC5_SHIFT (8U) 2864 /*! AC5 - Attribute Check 2865 */ 2866 #define AIPS_PACRO_AC5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_AC5_SHIFT)) & AIPS_PACRO_AC5_MASK) 2867 2868 #define AIPS_PACRO_RO5_MASK (0x800U) 2869 #define AIPS_PACRO_RO5_SHIFT (11U) 2870 /*! RO5 - Read Only 2871 * 0b0..Writes to corresponding AC field are allowed. 2872 * 0b1..Writes to corresponding AC field are ignored. 2873 */ 2874 #define AIPS_PACRO_RO5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_RO5_SHIFT)) & AIPS_PACRO_RO5_MASK) 2875 2876 #define AIPS_PACRO_AC4_MASK (0x7000U) 2877 #define AIPS_PACRO_AC4_SHIFT (12U) 2878 /*! AC4 - Attribute Check 2879 */ 2880 #define AIPS_PACRO_AC4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_AC4_SHIFT)) & AIPS_PACRO_AC4_MASK) 2881 2882 #define AIPS_PACRO_RO4_MASK (0x8000U) 2883 #define AIPS_PACRO_RO4_SHIFT (15U) 2884 /*! RO4 - Read Only 2885 * 0b0..Writes to corresponding AC field are allowed. 2886 * 0b1..Writes to corresponding AC field are ignored. 2887 */ 2888 #define AIPS_PACRO_RO4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_RO4_SHIFT)) & AIPS_PACRO_RO4_MASK) 2889 2890 #define AIPS_PACRO_AC3_MASK (0x70000U) 2891 #define AIPS_PACRO_AC3_SHIFT (16U) 2892 /*! AC3 - Attribute Check 2893 */ 2894 #define AIPS_PACRO_AC3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_AC3_SHIFT)) & AIPS_PACRO_AC3_MASK) 2895 2896 #define AIPS_PACRO_RO3_MASK (0x80000U) 2897 #define AIPS_PACRO_RO3_SHIFT (19U) 2898 /*! RO3 - Read Only 2899 * 0b0..Writes to corresponding AC field are allowed. 2900 * 0b1..Writes to corresponding AC field are ignored. 2901 */ 2902 #define AIPS_PACRO_RO3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_RO3_SHIFT)) & AIPS_PACRO_RO3_MASK) 2903 2904 #define AIPS_PACRO_AC2_MASK (0x700000U) 2905 #define AIPS_PACRO_AC2_SHIFT (20U) 2906 /*! AC2 - Attribute Check 2907 */ 2908 #define AIPS_PACRO_AC2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_AC2_SHIFT)) & AIPS_PACRO_AC2_MASK) 2909 2910 #define AIPS_PACRO_RO2_MASK (0x800000U) 2911 #define AIPS_PACRO_RO2_SHIFT (23U) 2912 /*! RO2 - Read Only 2913 * 0b0..Writes to corresponding AC field are allowed. 2914 * 0b1..Writes to corresponding AC field are ignored. 2915 */ 2916 #define AIPS_PACRO_RO2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_RO2_SHIFT)) & AIPS_PACRO_RO2_MASK) 2917 2918 #define AIPS_PACRO_AC1_MASK (0x7000000U) 2919 #define AIPS_PACRO_AC1_SHIFT (24U) 2920 /*! AC1 - Attribute Check 2921 */ 2922 #define AIPS_PACRO_AC1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_AC1_SHIFT)) & AIPS_PACRO_AC1_MASK) 2923 2924 #define AIPS_PACRO_RO1_MASK (0x8000000U) 2925 #define AIPS_PACRO_RO1_SHIFT (27U) 2926 /*! RO1 - Read Only 2927 * 0b0..Writes to corresponding AC field are allowed. 2928 * 0b1..Writes to corresponding AC field are ignored. 2929 */ 2930 #define AIPS_PACRO_RO1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_RO1_SHIFT)) & AIPS_PACRO_RO1_MASK) 2931 2932 #define AIPS_PACRO_AC0_MASK (0x70000000U) 2933 #define AIPS_PACRO_AC0_SHIFT (28U) 2934 /*! AC0 - Attribute Check 2935 */ 2936 #define AIPS_PACRO_AC0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_AC0_SHIFT)) & AIPS_PACRO_AC0_MASK) 2937 2938 #define AIPS_PACRO_RO0_MASK (0x80000000U) 2939 #define AIPS_PACRO_RO0_SHIFT (31U) 2940 /*! RO0 - Read Only 2941 * 0b0..Writes to corresponding AC field are allowed. 2942 * 0b1..Writes to corresponding AC field are ignored. 2943 */ 2944 #define AIPS_PACRO_RO0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_RO0_SHIFT)) & AIPS_PACRO_RO0_MASK) 2945 /*! @} */ 2946 2947 /*! @name PACRP - Peripheral Access Control Register */ 2948 /*! @{ */ 2949 2950 #define AIPS_PACRP_AC7_MASK (0x7U) 2951 #define AIPS_PACRP_AC7_SHIFT (0U) 2952 /*! AC7 - Attribute Check 2953 */ 2954 #define AIPS_PACRP_AC7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_AC7_SHIFT)) & AIPS_PACRP_AC7_MASK) 2955 2956 #define AIPS_PACRP_RO7_MASK (0x8U) 2957 #define AIPS_PACRP_RO7_SHIFT (3U) 2958 /*! RO7 - Read Only 2959 * 0b0..Writes to corresponding AC field are allowed. 2960 * 0b1..Writes to corresponding AC field are ignored. 2961 */ 2962 #define AIPS_PACRP_RO7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_RO7_SHIFT)) & AIPS_PACRP_RO7_MASK) 2963 2964 #define AIPS_PACRP_AC6_MASK (0x70U) 2965 #define AIPS_PACRP_AC6_SHIFT (4U) 2966 /*! AC6 - Attribute Check 2967 */ 2968 #define AIPS_PACRP_AC6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_AC6_SHIFT)) & AIPS_PACRP_AC6_MASK) 2969 2970 #define AIPS_PACRP_RO6_MASK (0x80U) 2971 #define AIPS_PACRP_RO6_SHIFT (7U) 2972 /*! RO6 - Read Only 2973 * 0b0..Writes to corresponding AC field are allowed. 2974 * 0b1..Writes to corresponding AC field are ignored. 2975 */ 2976 #define AIPS_PACRP_RO6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_RO6_SHIFT)) & AIPS_PACRP_RO6_MASK) 2977 2978 #define AIPS_PACRP_AC5_MASK (0x700U) 2979 #define AIPS_PACRP_AC5_SHIFT (8U) 2980 /*! AC5 - Attribute Check 2981 */ 2982 #define AIPS_PACRP_AC5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_AC5_SHIFT)) & AIPS_PACRP_AC5_MASK) 2983 2984 #define AIPS_PACRP_RO5_MASK (0x800U) 2985 #define AIPS_PACRP_RO5_SHIFT (11U) 2986 /*! RO5 - Read Only 2987 * 0b0..Writes to corresponding AC field are allowed. 2988 * 0b1..Writes to corresponding AC field are ignored. 2989 */ 2990 #define AIPS_PACRP_RO5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_RO5_SHIFT)) & AIPS_PACRP_RO5_MASK) 2991 2992 #define AIPS_PACRP_AC4_MASK (0x7000U) 2993 #define AIPS_PACRP_AC4_SHIFT (12U) 2994 /*! AC4 - Attribute Check 2995 */ 2996 #define AIPS_PACRP_AC4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_AC4_SHIFT)) & AIPS_PACRP_AC4_MASK) 2997 2998 #define AIPS_PACRP_RO4_MASK (0x8000U) 2999 #define AIPS_PACRP_RO4_SHIFT (15U) 3000 /*! RO4 - Read Only 3001 * 0b0..Writes to corresponding AC field are allowed. 3002 * 0b1..Writes to corresponding AC field are ignored. 3003 */ 3004 #define AIPS_PACRP_RO4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_RO4_SHIFT)) & AIPS_PACRP_RO4_MASK) 3005 3006 #define AIPS_PACRP_AC3_MASK (0x70000U) 3007 #define AIPS_PACRP_AC3_SHIFT (16U) 3008 /*! AC3 - Attribute Check 3009 */ 3010 #define AIPS_PACRP_AC3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_AC3_SHIFT)) & AIPS_PACRP_AC3_MASK) 3011 3012 #define AIPS_PACRP_RO3_MASK (0x80000U) 3013 #define AIPS_PACRP_RO3_SHIFT (19U) 3014 /*! RO3 - Read Only 3015 * 0b0..Writes to corresponding AC field are allowed. 3016 * 0b1..Writes to corresponding AC field are ignored. 3017 */ 3018 #define AIPS_PACRP_RO3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_RO3_SHIFT)) & AIPS_PACRP_RO3_MASK) 3019 3020 #define AIPS_PACRP_AC2_MASK (0x700000U) 3021 #define AIPS_PACRP_AC2_SHIFT (20U) 3022 /*! AC2 - Attribute Check 3023 */ 3024 #define AIPS_PACRP_AC2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_AC2_SHIFT)) & AIPS_PACRP_AC2_MASK) 3025 3026 #define AIPS_PACRP_RO2_MASK (0x800000U) 3027 #define AIPS_PACRP_RO2_SHIFT (23U) 3028 /*! RO2 - Read Only 3029 * 0b0..Writes to corresponding AC field are allowed. 3030 * 0b1..Writes to corresponding AC field are ignored. 3031 */ 3032 #define AIPS_PACRP_RO2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_RO2_SHIFT)) & AIPS_PACRP_RO2_MASK) 3033 3034 #define AIPS_PACRP_AC1_MASK (0x7000000U) 3035 #define AIPS_PACRP_AC1_SHIFT (24U) 3036 /*! AC1 - Attribute Check 3037 */ 3038 #define AIPS_PACRP_AC1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_AC1_SHIFT)) & AIPS_PACRP_AC1_MASK) 3039 3040 #define AIPS_PACRP_RO1_MASK (0x8000000U) 3041 #define AIPS_PACRP_RO1_SHIFT (27U) 3042 /*! RO1 - Read Only 3043 * 0b0..Writes to corresponding AC field are allowed. 3044 * 0b1..Writes to corresponding AC field are ignored. 3045 */ 3046 #define AIPS_PACRP_RO1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_RO1_SHIFT)) & AIPS_PACRP_RO1_MASK) 3047 3048 #define AIPS_PACRP_AC0_MASK (0x70000000U) 3049 #define AIPS_PACRP_AC0_SHIFT (28U) 3050 /*! AC0 - Attribute Check 3051 */ 3052 #define AIPS_PACRP_AC0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_AC0_SHIFT)) & AIPS_PACRP_AC0_MASK) 3053 3054 #define AIPS_PACRP_RO0_MASK (0x80000000U) 3055 #define AIPS_PACRP_RO0_SHIFT (31U) 3056 /*! RO0 - Read Only 3057 * 0b0..Writes to corresponding AC field are allowed. 3058 * 0b1..Writes to corresponding AC field are ignored. 3059 */ 3060 #define AIPS_PACRP_RO0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_RO0_SHIFT)) & AIPS_PACRP_RO0_MASK) 3061 /*! @} */ 3062 3063 3064 /*! 3065 * @} 3066 */ /* end of group AIPS_Register_Masks */ 3067 3068 3069 /* AIPS - Peripheral instance base addresses */ 3070 /** Peripheral AIPS base address */ 3071 #define AIPS_BASE (0x40000000u) 3072 /** Peripheral AIPS base pointer */ 3073 #define AIPS ((AIPS_Type *)AIPS_BASE) 3074 /** Array initializer of AIPS peripheral base addresses */ 3075 #define AIPS_BASE_ADDRS { AIPS_BASE } 3076 /** Array initializer of AIPS peripheral base pointers */ 3077 #define AIPS_BASE_PTRS { AIPS } 3078 3079 /*! 3080 * @} 3081 */ /* end of group AIPS_Peripheral_Access_Layer */ 3082 3083 3084 /* ---------------------------------------------------------------------------- 3085 -- CMP Peripheral Access Layer 3086 ---------------------------------------------------------------------------- */ 3087 3088 /*! 3089 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer 3090 * @{ 3091 */ 3092 3093 /** CMP - Register Layout Typedef */ 3094 typedef struct { 3095 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ 3096 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ 3097 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ 3098 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ 3099 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ 3100 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ 3101 } CMP_Type; 3102 3103 /* ---------------------------------------------------------------------------- 3104 -- CMP Register Masks 3105 ---------------------------------------------------------------------------- */ 3106 3107 /*! 3108 * @addtogroup CMP_Register_Masks CMP Register Masks 3109 * @{ 3110 */ 3111 3112 /*! @name CR0 - CMP Control Register 0 */ 3113 /*! @{ */ 3114 3115 #define CMP_CR0_HYSTCTR_MASK (0x3U) 3116 #define CMP_CR0_HYSTCTR_SHIFT (0U) 3117 /*! HYSTCTR - Comparator hard block hysteresis control 3118 * 0b00..Level 0 3119 * 0b01..Level 1 3120 * 0b10..Level 2 3121 * 0b11..Level 3 3122 */ 3123 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK) 3124 3125 #define CMP_CR0_FILTER_CNT_MASK (0x70U) 3126 #define CMP_CR0_FILTER_CNT_SHIFT (4U) 3127 /*! FILTER_CNT - Filter Sample Count 3128 * 0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA. 3129 * 0b001..One sample must agree. The comparator output is simply sampled. 3130 * 0b010..2 consecutive samples must agree. 3131 * 0b011..3 consecutive samples must agree. 3132 * 0b100..4 consecutive samples must agree. 3133 * 0b101..5 consecutive samples must agree. 3134 * 0b110..6 consecutive samples must agree. 3135 * 0b111..7 consecutive samples must agree. 3136 */ 3137 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK) 3138 /*! @} */ 3139 3140 /*! @name CR1 - CMP Control Register 1 */ 3141 /*! @{ */ 3142 3143 #define CMP_CR1_EN_MASK (0x1U) 3144 #define CMP_CR1_EN_SHIFT (0U) 3145 /*! EN - Comparator Module Enable 3146 * 0b0..Analog Comparator is disabled. 3147 * 0b1..Analog Comparator is enabled. 3148 */ 3149 #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK) 3150 3151 #define CMP_CR1_OPE_MASK (0x2U) 3152 #define CMP_CR1_OPE_SHIFT (1U) 3153 /*! OPE - Comparator Output Pin Enable 3154 * 0b0..CMPO is not available on the associated CMPO output pin. 3155 * 0b1..CMPO is available on the associated CMPO output pin. 3156 */ 3157 #define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK) 3158 3159 #define CMP_CR1_COS_MASK (0x4U) 3160 #define CMP_CR1_COS_SHIFT (2U) 3161 /*! COS - Comparator Output Select 3162 * 0b0..Set the filtered comparator output (CMPO) to equal COUT. 3163 * 0b1..Set the unfiltered comparator output (CMPO) to equal COUTA. 3164 */ 3165 #define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK) 3166 3167 #define CMP_CR1_INV_MASK (0x8U) 3168 #define CMP_CR1_INV_SHIFT (3U) 3169 /*! INV - Comparator INVERT 3170 * 0b0..Does not invert the comparator output. 3171 * 0b1..Inverts the comparator output. 3172 */ 3173 #define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK) 3174 3175 #define CMP_CR1_PMODE_MASK (0x10U) 3176 #define CMP_CR1_PMODE_SHIFT (4U) 3177 /*! PMODE - Power Mode Select 3178 * 0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. 3179 * 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. 3180 */ 3181 #define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK) 3182 3183 #define CMP_CR1_TRIGM_MASK (0x20U) 3184 #define CMP_CR1_TRIGM_SHIFT (5U) 3185 /*! TRIGM - Trigger Mode Enable 3186 * 0b0..Trigger mode is disabled. 3187 * 0b1..Trigger mode is enabled. 3188 */ 3189 #define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK) 3190 3191 #define CMP_CR1_WE_MASK (0x40U) 3192 #define CMP_CR1_WE_SHIFT (6U) 3193 /*! WE - Windowing Enable 3194 * 0b0..Windowing mode is not selected. 3195 * 0b1..Windowing mode is selected. 3196 */ 3197 #define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK) 3198 3199 #define CMP_CR1_SE_MASK (0x80U) 3200 #define CMP_CR1_SE_SHIFT (7U) 3201 /*! SE - Sample Enable 3202 * 0b0..Sampling mode is not selected. 3203 * 0b1..Sampling mode is selected. 3204 */ 3205 #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK) 3206 /*! @} */ 3207 3208 /*! @name FPR - CMP Filter Period Register */ 3209 /*! @{ */ 3210 3211 #define CMP_FPR_FILT_PER_MASK (0xFFU) 3212 #define CMP_FPR_FILT_PER_SHIFT (0U) 3213 /*! FILT_PER - Filter Sample Period 3214 */ 3215 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK) 3216 /*! @} */ 3217 3218 /*! @name SCR - CMP Status and Control Register */ 3219 /*! @{ */ 3220 3221 #define CMP_SCR_COUT_MASK (0x1U) 3222 #define CMP_SCR_COUT_SHIFT (0U) 3223 /*! COUT - Analog Comparator Output 3224 */ 3225 #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK) 3226 3227 #define CMP_SCR_CFF_MASK (0x2U) 3228 #define CMP_SCR_CFF_SHIFT (1U) 3229 /*! CFF - Analog Comparator Flag Falling 3230 * 0b0..Falling-edge on COUT has not been detected. 3231 * 0b1..Falling-edge on COUT has occurred. 3232 */ 3233 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK) 3234 3235 #define CMP_SCR_CFR_MASK (0x4U) 3236 #define CMP_SCR_CFR_SHIFT (2U) 3237 /*! CFR - Analog Comparator Flag Rising 3238 * 0b0..Rising-edge on COUT has not been detected. 3239 * 0b1..Rising-edge on COUT has occurred. 3240 */ 3241 #define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK) 3242 3243 #define CMP_SCR_IEF_MASK (0x8U) 3244 #define CMP_SCR_IEF_SHIFT (3U) 3245 /*! IEF - Comparator Interrupt Enable Falling 3246 * 0b0..Interrupt is disabled. 3247 * 0b1..Interrupt is enabled. 3248 */ 3249 #define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK) 3250 3251 #define CMP_SCR_IER_MASK (0x10U) 3252 #define CMP_SCR_IER_SHIFT (4U) 3253 /*! IER - Comparator Interrupt Enable Rising 3254 * 0b0..Interrupt is disabled. 3255 * 0b1..Interrupt is enabled. 3256 */ 3257 #define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK) 3258 3259 #define CMP_SCR_DMAEN_MASK (0x40U) 3260 #define CMP_SCR_DMAEN_SHIFT (6U) 3261 /*! DMAEN - DMA Enable Control 3262 * 0b0..DMA is disabled. 3263 * 0b1..DMA is enabled. 3264 */ 3265 #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK) 3266 /*! @} */ 3267 3268 /*! @name DACCR - DAC Control Register */ 3269 /*! @{ */ 3270 3271 #define CMP_DACCR_VOSEL_MASK (0x3FU) 3272 #define CMP_DACCR_VOSEL_SHIFT (0U) 3273 /*! VOSEL - DAC Output Voltage Select 3274 */ 3275 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK) 3276 3277 #define CMP_DACCR_VRSEL_MASK (0x40U) 3278 #define CMP_DACCR_VRSEL_SHIFT (6U) 3279 /*! VRSEL - Supply Voltage Reference Source Select 3280 * 0b0..Vin1 is selected as resistor ladder network supply reference. 3281 * 0b1..Vin2 is selected as resistor ladder network supply reference. 3282 */ 3283 #define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK) 3284 3285 #define CMP_DACCR_DACEN_MASK (0x80U) 3286 #define CMP_DACCR_DACEN_SHIFT (7U) 3287 /*! DACEN - DAC Enable 3288 * 0b0..DAC is disabled. 3289 * 0b1..DAC is enabled. 3290 */ 3291 #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK) 3292 /*! @} */ 3293 3294 /*! @name MUXCR - MUX Control Register */ 3295 /*! @{ */ 3296 3297 #define CMP_MUXCR_MSEL_MASK (0x7U) 3298 #define CMP_MUXCR_MSEL_SHIFT (0U) 3299 /*! MSEL - Minus Input Mux Control 3300 * 0b000..IN0 3301 * 0b001..IN1 3302 * 0b010..IN2 3303 * 0b011..IN3 3304 * 0b100..IN4 3305 * 0b101..IN5 3306 * 0b110..IN6 3307 * 0b111..IN7 3308 */ 3309 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK) 3310 3311 #define CMP_MUXCR_PSEL_MASK (0x38U) 3312 #define CMP_MUXCR_PSEL_SHIFT (3U) 3313 /*! PSEL - Plus Input Mux Control 3314 * 0b000..IN0 3315 * 0b001..IN1 3316 * 0b010..IN2 3317 * 0b011..IN3 3318 * 0b100..IN4 3319 * 0b101..IN5 3320 * 0b110..IN6 3321 * 0b111..IN7 3322 */ 3323 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) 3324 /*! @} */ 3325 3326 3327 /*! 3328 * @} 3329 */ /* end of group CMP_Register_Masks */ 3330 3331 3332 /* CMP - Peripheral instance base addresses */ 3333 /** Peripheral CMP0 base address */ 3334 #define CMP0_BASE (0x40072000u) 3335 /** Peripheral CMP0 base pointer */ 3336 #define CMP0 ((CMP_Type *)CMP0_BASE) 3337 /** Peripheral CMP1 base address */ 3338 #define CMP1_BASE (0x40072008u) 3339 /** Peripheral CMP1 base pointer */ 3340 #define CMP1 ((CMP_Type *)CMP1_BASE) 3341 /** Array initializer of CMP peripheral base addresses */ 3342 #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE } 3343 /** Array initializer of CMP peripheral base pointers */ 3344 #define CMP_BASE_PTRS { CMP0, CMP1 } 3345 /** Interrupt vectors for the CMP peripheral type */ 3346 #define CMP_IRQS { CMP0_CMP1_IRQn, CMP0_CMP1_IRQn } 3347 3348 /*! 3349 * @} 3350 */ /* end of group CMP_Peripheral_Access_Layer */ 3351 3352 3353 /* ---------------------------------------------------------------------------- 3354 -- CRC Peripheral Access Layer 3355 ---------------------------------------------------------------------------- */ 3356 3357 /*! 3358 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer 3359 * @{ 3360 */ 3361 3362 /** CRC - Register Layout Typedef */ 3363 typedef struct { 3364 union { /* offset: 0x0 */ 3365 struct { /* offset: 0x0 */ 3366 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */ 3367 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */ 3368 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */ 3369 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */ 3370 } ACCESS8BIT; 3371 struct { /* offset: 0x0 */ 3372 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */ 3373 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */ 3374 } ACCESS16BIT; 3375 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */ 3376 }; 3377 union { /* offset: 0x4 */ 3378 struct { /* offset: 0x4 */ 3379 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */ 3380 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */ 3381 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */ 3382 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */ 3383 } GPOLY_ACCESS8BIT; 3384 struct { /* offset: 0x4 */ 3385 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */ 3386 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */ 3387 } GPOLY_ACCESS16BIT; 3388 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */ 3389 }; 3390 union { /* offset: 0x8 */ 3391 struct { /* offset: 0x8 */ 3392 uint8_t RESERVED_0[3]; 3393 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */ 3394 } CTRL_ACCESS8BIT; 3395 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */ 3396 }; 3397 } CRC_Type; 3398 3399 /* ---------------------------------------------------------------------------- 3400 -- CRC Register Masks 3401 ---------------------------------------------------------------------------- */ 3402 3403 /*! 3404 * @addtogroup CRC_Register_Masks CRC Register Masks 3405 * @{ 3406 */ 3407 3408 /*! @name DATALL - CRC_DATALL register. */ 3409 /*! @{ */ 3410 3411 #define CRC_DATALL_DATALL_MASK (0xFFU) 3412 #define CRC_DATALL_DATALL_SHIFT (0U) 3413 /*! DATALL - CRCLL stores the first 8 bits of the 32 bit DATA 3414 */ 3415 #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK) 3416 /*! @} */ 3417 3418 /*! @name DATALU - CRC_DATALU register. */ 3419 /*! @{ */ 3420 3421 #define CRC_DATALU_DATALU_MASK (0xFFU) 3422 #define CRC_DATALU_DATALU_SHIFT (0U) 3423 /*! DATALU - DATALL stores the second 8 bits of the 32 bit CRC 3424 */ 3425 #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK) 3426 /*! @} */ 3427 3428 /*! @name DATAHL - CRC_DATAHL register. */ 3429 /*! @{ */ 3430 3431 #define CRC_DATAHL_DATAHL_MASK (0xFFU) 3432 #define CRC_DATAHL_DATAHL_SHIFT (0U) 3433 /*! DATAHL - DATAHL stores the third 8 bits of the 32 bit CRC 3434 */ 3435 #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK) 3436 /*! @} */ 3437 3438 /*! @name DATAHU - CRC_DATAHU register. */ 3439 /*! @{ */ 3440 3441 #define CRC_DATAHU_DATAHU_MASK (0xFFU) 3442 #define CRC_DATAHU_DATAHU_SHIFT (0U) 3443 /*! DATAHU - DATAHU stores the fourth 8 bits of the 32 bit CRC 3444 */ 3445 #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK) 3446 /*! @} */ 3447 3448 /*! @name DATAL - CRC_DATAL register. */ 3449 /*! @{ */ 3450 3451 #define CRC_DATAL_DATAL_MASK (0xFFFFU) 3452 #define CRC_DATAL_DATAL_SHIFT (0U) 3453 /*! DATAL - DATAL stores the lower 16 bits of the 16/32 bit CRC 3454 */ 3455 #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK) 3456 /*! @} */ 3457 3458 /*! @name DATAH - CRC_DATAH register. */ 3459 /*! @{ */ 3460 3461 #define CRC_DATAH_DATAH_MASK (0xFFFFU) 3462 #define CRC_DATAH_DATAH_SHIFT (0U) 3463 /*! DATAH - DATAH stores the high 16 bits of the 16/32 bit CRC 3464 */ 3465 #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK) 3466 /*! @} */ 3467 3468 /*! @name DATA - CRC Data register */ 3469 /*! @{ */ 3470 3471 #define CRC_DATA_LL_MASK (0xFFU) 3472 #define CRC_DATA_LL_SHIFT (0U) 3473 /*! LL - CRC Low Lower Byte 3474 */ 3475 #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK) 3476 3477 #define CRC_DATA_LU_MASK (0xFF00U) 3478 #define CRC_DATA_LU_SHIFT (8U) 3479 /*! LU - CRC Low Upper Byte 3480 */ 3481 #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK) 3482 3483 #define CRC_DATA_HL_MASK (0xFF0000U) 3484 #define CRC_DATA_HL_SHIFT (16U) 3485 /*! HL - CRC High Lower Byte 3486 */ 3487 #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK) 3488 3489 #define CRC_DATA_HU_MASK (0xFF000000U) 3490 #define CRC_DATA_HU_SHIFT (24U) 3491 /*! HU - CRC High Upper Byte 3492 */ 3493 #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK) 3494 /*! @} */ 3495 3496 /*! @name GPOLYLL - CRC_GPOLYLL register. */ 3497 /*! @{ */ 3498 3499 #define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU) 3500 #define CRC_GPOLYLL_GPOLYLL_SHIFT (0U) 3501 /*! GPOLYLL - POLYLL stores the first 8 bits of the 32 bit CRC 3502 */ 3503 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK) 3504 /*! @} */ 3505 3506 /*! @name GPOLYLU - CRC_GPOLYLU register. */ 3507 /*! @{ */ 3508 3509 #define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU) 3510 #define CRC_GPOLYLU_GPOLYLU_SHIFT (0U) 3511 /*! GPOLYLU - POLYLL stores the second 8 bits of the 32 bit CRC 3512 */ 3513 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK) 3514 /*! @} */ 3515 3516 /*! @name GPOLYHL - CRC_GPOLYHL register. */ 3517 /*! @{ */ 3518 3519 #define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU) 3520 #define CRC_GPOLYHL_GPOLYHL_SHIFT (0U) 3521 /*! GPOLYHL - POLYHL stores the third 8 bits of the 32 bit CRC 3522 */ 3523 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK) 3524 /*! @} */ 3525 3526 /*! @name GPOLYHU - CRC_GPOLYHU register. */ 3527 /*! @{ */ 3528 3529 #define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU) 3530 #define CRC_GPOLYHU_GPOLYHU_SHIFT (0U) 3531 /*! GPOLYHU - POLYHU stores the fourth 8 bits of the 32 bit CRC 3532 */ 3533 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK) 3534 /*! @} */ 3535 3536 /*! @name GPOLYL - CRC_GPOLYL register. */ 3537 /*! @{ */ 3538 3539 #define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU) 3540 #define CRC_GPOLYL_GPOLYL_SHIFT (0U) 3541 /*! GPOLYL - POLYL stores the lower 16 bits of the 16/32 bit CRC polynomial value 3542 */ 3543 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK) 3544 /*! @} */ 3545 3546 /*! @name GPOLYH - CRC_GPOLYH register. */ 3547 /*! @{ */ 3548 3549 #define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU) 3550 #define CRC_GPOLYH_GPOLYH_SHIFT (0U) 3551 /*! GPOLYH - POLYH stores the high 16 bits of the 16/32 bit CRC polynomial value 3552 */ 3553 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) 3554 /*! @} */ 3555 3556 /*! @name GPOLY - CRC Polynomial register */ 3557 /*! @{ */ 3558 3559 #define CRC_GPOLY_LOW_MASK (0xFFFFU) 3560 #define CRC_GPOLY_LOW_SHIFT (0U) 3561 /*! LOW - Low Polynominal Half-word 3562 */ 3563 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) 3564 3565 #define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) 3566 #define CRC_GPOLY_HIGH_SHIFT (16U) 3567 /*! HIGH - High Polynominal Half-word 3568 */ 3569 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) 3570 /*! @} */ 3571 3572 /*! @name CTRLHU - CRC_CTRLHU register. */ 3573 /*! @{ */ 3574 3575 #define CRC_CTRLHU_TCRC_MASK (0x1U) 3576 #define CRC_CTRLHU_TCRC_SHIFT (0U) 3577 /*! TCRC 3578 * 0b0..16-bit CRC protocol. 3579 * 0b1..32-bit CRC protocol. 3580 */ 3581 #define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) 3582 3583 #define CRC_CTRLHU_WAS_MASK (0x2U) 3584 #define CRC_CTRLHU_WAS_SHIFT (1U) 3585 /*! WAS 3586 * 0b0..Writes to CRC data register are data values. 3587 * 0b1..Writes to CRC data reguster are seed values. 3588 */ 3589 #define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK) 3590 3591 #define CRC_CTRLHU_FXOR_MASK (0x4U) 3592 #define CRC_CTRLHU_FXOR_SHIFT (2U) 3593 /*! FXOR 3594 * 0b0..No XOR on reading. 3595 * 0b1..Invert or complement the read value of CRC data register. 3596 */ 3597 #define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) 3598 3599 #define CRC_CTRLHU_TOTR_MASK (0x30U) 3600 #define CRC_CTRLHU_TOTR_SHIFT (4U) 3601 /*! TOTR 3602 * 0b00..No Transposition. 3603 * 0b01..Bits in bytes are transposed, bytes are not transposed. 3604 * 0b10..Both bits in bytes and bytes are transposed. 3605 * 0b11..Only bytes are transposed; no bits in a byte are transposed. 3606 */ 3607 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) 3608 3609 #define CRC_CTRLHU_TOT_MASK (0xC0U) 3610 #define CRC_CTRLHU_TOT_SHIFT (6U) 3611 /*! TOT 3612 * 0b00..No Transposition. 3613 * 0b01..Bits in bytes are transposed, bytes are not transposed. 3614 * 0b10..Both bits in bytes and bytes are transposed. 3615 * 0b11..Only bytes are transposed; no bits in a byte are transposed. 3616 */ 3617 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) 3618 /*! @} */ 3619 3620 /*! @name CTRL - CRC Control register */ 3621 /*! @{ */ 3622 3623 #define CRC_CTRL_TCRC_MASK (0x1000000U) 3624 #define CRC_CTRL_TCRC_SHIFT (24U) 3625 /*! TCRC 3626 * 0b0..16-bit CRC protocol. 3627 * 0b1..32-bit CRC protocol. 3628 */ 3629 #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) 3630 3631 #define CRC_CTRL_WAS_MASK (0x2000000U) 3632 #define CRC_CTRL_WAS_SHIFT (25U) 3633 /*! WAS - Write CRC Data Register As Seed 3634 * 0b0..Writes to the CRC data register are data values. 3635 * 0b1..Writes to the CRC data register are seed values. 3636 */ 3637 #define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) 3638 3639 #define CRC_CTRL_FXOR_MASK (0x4000000U) 3640 #define CRC_CTRL_FXOR_SHIFT (26U) 3641 /*! FXOR - Complement Read Of CRC Data Register 3642 * 0b0..No XOR on reading. 3643 * 0b1..Invert or complement the read value of the CRC Data register. 3644 */ 3645 #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) 3646 3647 #define CRC_CTRL_TOTR_MASK (0x30000000U) 3648 #define CRC_CTRL_TOTR_SHIFT (28U) 3649 /*! TOTR - Type Of Transpose For Read 3650 * 0b00..No transposition. 3651 * 0b01..Bits in bytes are transposed; bytes are not transposed. 3652 * 0b10..Both bits in bytes and bytes are transposed. 3653 * 0b11..Only bytes are transposed; no bits in a byte are transposed. 3654 */ 3655 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) 3656 3657 #define CRC_CTRL_TOT_MASK (0xC0000000U) 3658 #define CRC_CTRL_TOT_SHIFT (30U) 3659 /*! TOT - Type Of Transpose For Writes 3660 * 0b00..No transposition. 3661 * 0b01..Bits in bytes are transposed; bytes are not transposed. 3662 * 0b10..Both bits in bytes and bytes are transposed. 3663 * 0b11..Only bytes are transposed; no bits in a byte are transposed. 3664 */ 3665 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) 3666 /*! @} */ 3667 3668 3669 /*! 3670 * @} 3671 */ /* end of group CRC_Register_Masks */ 3672 3673 3674 /* CRC - Peripheral instance base addresses */ 3675 /** Peripheral CRC base address */ 3676 #define CRC_BASE (0x40034000u) 3677 /** Peripheral CRC base pointer */ 3678 #define CRC0 ((CRC_Type *)CRC_BASE) 3679 /** Array initializer of CRC peripheral base addresses */ 3680 #define CRC_BASE_ADDRS { CRC_BASE } 3681 /** Array initializer of CRC peripheral base pointers */ 3682 #define CRC_BASE_PTRS { CRC0 } 3683 3684 /*! 3685 * @} 3686 */ /* end of group CRC_Peripheral_Access_Layer */ 3687 3688 3689 /* ---------------------------------------------------------------------------- 3690 -- DMA Peripheral Access Layer 3691 ---------------------------------------------------------------------------- */ 3692 3693 /*! 3694 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer 3695 * @{ 3696 */ 3697 3698 /** DMA - Register Layout Typedef */ 3699 typedef struct { 3700 uint8_t RESERVED_0[256]; 3701 struct { /* offset: 0x100, array step: 0x10 */ 3702 __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */ 3703 __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */ 3704 union { /* offset: 0x108, array step: 0x10 */ 3705 struct { /* offset: 0x108, array step: 0x10 */ 3706 uint8_t RESERVED_0[3]; 3707 uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */ 3708 } DMA_DSR_ACCESS8BIT; 3709 __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */ 3710 }; 3711 __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */ 3712 } DMA[4]; 3713 } DMA_Type; 3714 3715 /* ---------------------------------------------------------------------------- 3716 -- DMA Register Masks 3717 ---------------------------------------------------------------------------- */ 3718 3719 /*! 3720 * @addtogroup DMA_Register_Masks DMA Register Masks 3721 * @{ 3722 */ 3723 3724 /*! @name SAR - Source Address Register */ 3725 /*! @{ */ 3726 3727 #define DMA_SAR_SAR_MASK (0xFFFFFFFFU) 3728 #define DMA_SAR_SAR_SHIFT (0U) 3729 /*! SAR - SAR 3730 */ 3731 #define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SAR_SAR_SHIFT)) & DMA_SAR_SAR_MASK) 3732 /*! @} */ 3733 3734 /* The count of DMA_SAR */ 3735 #define DMA_SAR_COUNT (4U) 3736 3737 /*! @name DAR - Destination Address Register */ 3738 /*! @{ */ 3739 3740 #define DMA_DAR_DAR_MASK (0xFFFFFFFFU) 3741 #define DMA_DAR_DAR_SHIFT (0U) 3742 /*! DAR - DAR 3743 */ 3744 #define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DAR_DAR_SHIFT)) & DMA_DAR_DAR_MASK) 3745 /*! @} */ 3746 3747 /* The count of DMA_DAR */ 3748 #define DMA_DAR_COUNT (4U) 3749 3750 /* The count of DMA_DSR */ 3751 #define DMA_DSR_COUNT (4U) 3752 3753 /*! @name DSR_BCR - DMA Status Register / Byte Count Register */ 3754 /*! @{ */ 3755 3756 #define DMA_DSR_BCR_BCR_MASK (0xFFFFFFU) 3757 #define DMA_DSR_BCR_BCR_SHIFT (0U) 3758 /*! BCR - BCR 3759 */ 3760 #define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BCR_SHIFT)) & DMA_DSR_BCR_BCR_MASK) 3761 3762 #define DMA_DSR_BCR_DONE_MASK (0x1000000U) 3763 #define DMA_DSR_BCR_DONE_SHIFT (24U) 3764 /*! DONE - Transactions Done 3765 * 0b0..DMA transfer is not yet complete. Writing a 0 has no effect. 3766 * 0b1..DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an 3767 * interrupt service routine to clear the DMA interrupt and error bits. 3768 */ 3769 #define DMA_DSR_BCR_DONE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_DONE_SHIFT)) & DMA_DSR_BCR_DONE_MASK) 3770 3771 #define DMA_DSR_BCR_BSY_MASK (0x2000000U) 3772 #define DMA_DSR_BCR_BSY_SHIFT (25U) 3773 /*! BSY - Busy 3774 * 0b0..DMA channel is inactive. Cleared when the DMA has finished the last transaction. 3775 * 0b1..BSY is set the first time the channel is enabled after a transfer is initiated. 3776 */ 3777 #define DMA_DSR_BCR_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BSY_SHIFT)) & DMA_DSR_BCR_BSY_MASK) 3778 3779 #define DMA_DSR_BCR_REQ_MASK (0x4000000U) 3780 #define DMA_DSR_BCR_REQ_SHIFT (26U) 3781 /*! REQ - Request 3782 * 0b0..No request is pending or the channel is currently active. Cleared when the channel is selected. 3783 * 0b1..The DMA channel has a transfer remaining and the channel is not selected. 3784 */ 3785 #define DMA_DSR_BCR_REQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_REQ_SHIFT)) & DMA_DSR_BCR_REQ_MASK) 3786 3787 #define DMA_DSR_BCR_BED_MASK (0x10000000U) 3788 #define DMA_DSR_BCR_BED_SHIFT (28U) 3789 /*! BED - Bus Error on Destination 3790 * 0b0..No bus error occurred. 3791 * 0b1..The DMA channel terminated with a bus error during the write portion of a transfer. 3792 */ 3793 #define DMA_DSR_BCR_BED(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BED_SHIFT)) & DMA_DSR_BCR_BED_MASK) 3794 3795 #define DMA_DSR_BCR_BES_MASK (0x20000000U) 3796 #define DMA_DSR_BCR_BES_SHIFT (29U) 3797 /*! BES - Bus Error on Source 3798 * 0b0..No bus error occurred. 3799 * 0b1..The DMA channel terminated with a bus error during the read portion of a transfer. 3800 */ 3801 #define DMA_DSR_BCR_BES(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_BES_SHIFT)) & DMA_DSR_BCR_BES_MASK) 3802 3803 #define DMA_DSR_BCR_CE_MASK (0x40000000U) 3804 #define DMA_DSR_BCR_CE_SHIFT (30U) 3805 /*! CE - Configuration Error 3806 * 0b0..No configuration error exists. 3807 * 0b1..A configuration error has occurred. 3808 */ 3809 #define DMA_DSR_BCR_CE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DSR_BCR_CE_SHIFT)) & DMA_DSR_BCR_CE_MASK) 3810 /*! @} */ 3811 3812 /* The count of DMA_DSR_BCR */ 3813 #define DMA_DSR_BCR_COUNT (4U) 3814 3815 /*! @name DCR - DMA Control Register */ 3816 /*! @{ */ 3817 3818 #define DMA_DCR_LCH2_MASK (0x3U) 3819 #define DMA_DCR_LCH2_SHIFT (0U) 3820 /*! LCH2 - Link Channel 2 3821 * 0b00..DMA Channel 0 3822 * 0b01..DMA Channel 1 3823 * 0b10..DMA Channel 2 3824 * 0b11..DMA Channel 3 3825 */ 3826 #define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LCH2_SHIFT)) & DMA_DCR_LCH2_MASK) 3827 3828 #define DMA_DCR_LCH1_MASK (0xCU) 3829 #define DMA_DCR_LCH1_SHIFT (2U) 3830 /*! LCH1 - Link Channel 1 3831 * 0b00..DMA Channel 0 3832 * 0b01..DMA Channel 1 3833 * 0b10..DMA Channel 2 3834 * 0b11..DMA Channel 3 3835 */ 3836 #define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LCH1_SHIFT)) & DMA_DCR_LCH1_MASK) 3837 3838 #define DMA_DCR_LINKCC_MASK (0x30U) 3839 #define DMA_DCR_LINKCC_SHIFT (4U) 3840 /*! LINKCC - Link Channel Control 3841 * 0b00..No channel-to-channel linking 3842 * 0b01..Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0. 3843 * 0b10..Perform a link to channel LCH1 after each cycle-steal transfer 3844 * 0b11..Perform a link to channel LCH1 after the BCR decrements to 0. 3845 */ 3846 #define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_LINKCC_SHIFT)) & DMA_DCR_LINKCC_MASK) 3847 3848 #define DMA_DCR_D_REQ_MASK (0x80U) 3849 #define DMA_DCR_D_REQ_SHIFT (7U) 3850 /*! D_REQ - Disable Request 3851 * 0b0..ERQ bit is not affected. 3852 * 0b1..ERQ bit is cleared when the BCR is exhausted. 3853 */ 3854 #define DMA_DCR_D_REQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_D_REQ_SHIFT)) & DMA_DCR_D_REQ_MASK) 3855 3856 #define DMA_DCR_DMOD_MASK (0xF00U) 3857 #define DMA_DCR_DMOD_SHIFT (8U) 3858 /*! DMOD - Destination Address Modulo 3859 * 0b0000..Buffer disabled 3860 * 0b0001..Circular buffer size is 16 bytes 3861 * 0b0010..Circular buffer size is 32 bytes 3862 * 0b0011..Circular buffer size is 64 bytes 3863 * 0b0100..Circular buffer size is 128 bytes 3864 * 0b0101..Circular buffer size is 256 bytes 3865 * 0b0110..Circular buffer size is 512 bytes 3866 * 0b0111..Circular buffer size is 1 KB 3867 * 0b1000..Circular buffer size is 2 KB 3868 * 0b1001..Circular buffer size is 4 KB 3869 * 0b1010..Circular buffer size is 8 KB 3870 * 0b1011..Circular buffer size is 16 KB 3871 * 0b1100..Circular buffer size is 32 KB 3872 * 0b1101..Circular buffer size is 64 KB 3873 * 0b1110..Circular buffer size is 128 KB 3874 * 0b1111..Circular buffer size is 256 KB 3875 */ 3876 #define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DMOD_SHIFT)) & DMA_DCR_DMOD_MASK) 3877 3878 #define DMA_DCR_SMOD_MASK (0xF000U) 3879 #define DMA_DCR_SMOD_SHIFT (12U) 3880 /*! SMOD - Source Address Modulo 3881 * 0b0000..Buffer disabled 3882 * 0b0001..Circular buffer size is 16 bytes. 3883 * 0b0010..Circular buffer size is 32 bytes. 3884 * 0b0011..Circular buffer size is 64 bytes. 3885 * 0b0100..Circular buffer size is 128 bytes. 3886 * 0b0101..Circular buffer size is 256 bytes. 3887 * 0b0110..Circular buffer size is 512 bytes. 3888 * 0b0111..Circular buffer size is 1 KB. 3889 * 0b1000..Circular buffer size is 2 KB. 3890 * 0b1001..Circular buffer size is 4 KB. 3891 * 0b1010..Circular buffer size is 8 KB. 3892 * 0b1011..Circular buffer size is 16 KB. 3893 * 0b1100..Circular buffer size is 32 KB. 3894 * 0b1101..Circular buffer size is 64 KB. 3895 * 0b1110..Circular buffer size is 128 KB. 3896 * 0b1111..Circular buffer size is 256 KB. 3897 */ 3898 #define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SMOD_SHIFT)) & DMA_DCR_SMOD_MASK) 3899 3900 #define DMA_DCR_START_MASK (0x10000U) 3901 #define DMA_DCR_START_SHIFT (16U) 3902 /*! START - Start Transfer 3903 * 0b0..DMA inactive 3904 * 0b1..The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after 3905 * one module clock and always reads as logic 0. 3906 */ 3907 #define DMA_DCR_START(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_START_SHIFT)) & DMA_DCR_START_MASK) 3908 3909 #define DMA_DCR_DSIZE_MASK (0x60000U) 3910 #define DMA_DCR_DSIZE_SHIFT (17U) 3911 /*! DSIZE - Destination Size 3912 * 0b00..32-bit 3913 * 0b01..8-bit 3914 * 0b10..16-bit 3915 * 0b11..Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation) 3916 */ 3917 #define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DSIZE_SHIFT)) & DMA_DCR_DSIZE_MASK) 3918 3919 #define DMA_DCR_DINC_MASK (0x80000U) 3920 #define DMA_DCR_DINC_SHIFT (19U) 3921 /*! DINC - Destination Increment 3922 * 0b0..No change to the DAR after a successful transfer. 3923 * 0b1..The DAR increments by 1, 2, 4 depending upon the size of the transfer. 3924 */ 3925 #define DMA_DCR_DINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_DINC_SHIFT)) & DMA_DCR_DINC_MASK) 3926 3927 #define DMA_DCR_SSIZE_MASK (0x300000U) 3928 #define DMA_DCR_SSIZE_SHIFT (20U) 3929 /*! SSIZE - Source Size 3930 * 0b00..32-bit 3931 * 0b01..8-bit 3932 * 0b10..16-bit 3933 * 0b11..Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation) 3934 */ 3935 #define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SSIZE_SHIFT)) & DMA_DCR_SSIZE_MASK) 3936 3937 #define DMA_DCR_SINC_MASK (0x400000U) 3938 #define DMA_DCR_SINC_SHIFT (22U) 3939 /*! SINC - Source Increment 3940 * 0b0..No change to SAR after a successful transfer. 3941 * 0b1..The SAR increments by 1, 2, 4 as determined by the transfer size. 3942 */ 3943 #define DMA_DCR_SINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_SINC_SHIFT)) & DMA_DCR_SINC_MASK) 3944 3945 #define DMA_DCR_EADREQ_MASK (0x800000U) 3946 #define DMA_DCR_EADREQ_SHIFT (23U) 3947 /*! EADREQ - Enable asynchronous DMA requests 3948 * 0b0..Disabled 3949 * 0b1..Enabled 3950 */ 3951 #define DMA_DCR_EADREQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_EADREQ_SHIFT)) & DMA_DCR_EADREQ_MASK) 3952 3953 #define DMA_DCR_UMNSM_MASK (0x3000000U) 3954 #define DMA_DCR_UMNSM_SHIFT (24U) 3955 /*! UMNSM - User Mode, Nonsecure Mode 3956 * 0b00..Channel attributes are set to the current mode. 3957 * 0b01..If the current mode is privileged and secure, then attributes are set to {privileged, secure}. 3958 * Otherwise, writing this value terminates in an error. 3959 * 0b10..If the current mode is privileged and secure or if the current mode is user and secure, then attributes 3960 * are set to {user, secure}. Otherwise, writing this value terminates in an error. 3961 * 0b11..If the current mode is privileged and secure, user and secure, or user and nonsecure, then attributes are set to {user, nonsecure}. 3962 */ 3963 #define DMA_DCR_UMNSM(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_UMNSM_SHIFT)) & DMA_DCR_UMNSM_MASK) 3964 3965 #define DMA_DCR_CHACR_MASK (0xC000000U) 3966 #define DMA_DCR_CHACR_SHIFT (26U) 3967 /*! CHACR - Channel Access Control 3968 */ 3969 #define DMA_DCR_CHACR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_CHACR_SHIFT)) & DMA_DCR_CHACR_MASK) 3970 3971 #define DMA_DCR_AA_MASK (0x10000000U) 3972 #define DMA_DCR_AA_SHIFT (28U) 3973 /*! AA - Auto-align 3974 * 0b0..Auto-align disabled 3975 * 0b1..If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, 3976 * destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If 3977 * auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC. 3978 */ 3979 #define DMA_DCR_AA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_AA_SHIFT)) & DMA_DCR_AA_MASK) 3980 3981 #define DMA_DCR_CS_MASK (0x20000000U) 3982 #define DMA_DCR_CS_SHIFT (29U) 3983 /*! CS - Cycle Steal 3984 * 0b0..DMA continuously makes read/write transfers until the BCR decrements to 0. 3985 * 0b1..Forces a single read/write transfer per request. 3986 */ 3987 #define DMA_DCR_CS(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_CS_SHIFT)) & DMA_DCR_CS_MASK) 3988 3989 #define DMA_DCR_ERQ_MASK (0x40000000U) 3990 #define DMA_DCR_ERQ_SHIFT (30U) 3991 /*! ERQ - Enable Peripheral Request 3992 * 0b0..Peripheral request is ignored. 3993 * 0b1..Enables peripheral request to initiate transfer. A software-initiated request (setting START) is always enabled. 3994 */ 3995 #define DMA_DCR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_ERQ_SHIFT)) & DMA_DCR_ERQ_MASK) 3996 3997 #define DMA_DCR_EINT_MASK (0x80000000U) 3998 #define DMA_DCR_EINT_SHIFT (31U) 3999 /*! EINT - Enable Interrupt on Completion of Transfer 4000 * 0b0..No interrupt is generated. 4001 * 0b1..Interrupt signal is enabled. 4002 */ 4003 #define DMA_DCR_EINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_DCR_EINT_SHIFT)) & DMA_DCR_EINT_MASK) 4004 /*! @} */ 4005 4006 /* The count of DMA_DCR */ 4007 #define DMA_DCR_COUNT (4U) 4008 4009 4010 /*! 4011 * @} 4012 */ /* end of group DMA_Register_Masks */ 4013 4014 4015 /* DMA - Peripheral instance base addresses */ 4016 /** Peripheral DMA base address */ 4017 #define DMA_BASE (0x40008000u) 4018 /** Peripheral DMA base pointer */ 4019 #define DMA0 ((DMA_Type *)DMA_BASE) 4020 /** Array initializer of DMA peripheral base addresses */ 4021 #define DMA_BASE_ADDRS { DMA_BASE } 4022 /** Array initializer of DMA peripheral base pointers */ 4023 #define DMA_BASE_PTRS { DMA0 } 4024 /** Interrupt vectors for the DMA peripheral type */ 4025 #define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } } 4026 4027 /*! 4028 * @} 4029 */ /* end of group DMA_Peripheral_Access_Layer */ 4030 4031 4032 /* ---------------------------------------------------------------------------- 4033 -- DMAMUX Peripheral Access Layer 4034 ---------------------------------------------------------------------------- */ 4035 4036 /*! 4037 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer 4038 * @{ 4039 */ 4040 4041 /** DMAMUX - Register Layout Typedef */ 4042 typedef struct { 4043 __IO uint8_t CHCFG[1]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */ 4044 } DMAMUX_Type; 4045 4046 /* ---------------------------------------------------------------------------- 4047 -- DMAMUX Register Masks 4048 ---------------------------------------------------------------------------- */ 4049 4050 /*! 4051 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks 4052 * @{ 4053 */ 4054 4055 /*! @name CHCFG - Channel Configuration register */ 4056 /*! @{ */ 4057 4058 #define DMAMUX_CHCFG_SOURCE_MASK (0x3FU) 4059 #define DMAMUX_CHCFG_SOURCE_SHIFT (0U) 4060 /*! SOURCE - DMA Channel Source (Slot) 4061 */ 4062 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) 4063 4064 #define DMAMUX_CHCFG_TRIG_MASK (0x40U) 4065 #define DMAMUX_CHCFG_TRIG_SHIFT (6U) 4066 /*! TRIG - DMA Channel Trigger Enable 4067 * 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the 4068 * specified source to the DMA channel. (Normal mode) 4069 * 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. 4070 */ 4071 #define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) 4072 4073 #define DMAMUX_CHCFG_ENBL_MASK (0x80U) 4074 #define DMAMUX_CHCFG_ENBL_SHIFT (7U) 4075 /*! ENBL - DMA Channel Enable 4076 * 0b0..DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has 4077 * separate channel enables/disables, which should be used to disable or reconfigure a DMA channel. 4078 * 0b1..DMA channel is enabled 4079 */ 4080 #define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) 4081 /*! @} */ 4082 4083 /* The count of DMAMUX_CHCFG */ 4084 #define DMAMUX_CHCFG_COUNT (1U) 4085 4086 4087 /*! 4088 * @} 4089 */ /* end of group DMAMUX_Register_Masks */ 4090 4091 4092 /* DMAMUX - Peripheral instance base addresses */ 4093 /** Peripheral DMAMUX0 base address */ 4094 #define DMAMUX0_BASE (0x40021000u) 4095 /** Peripheral DMAMUX0 base pointer */ 4096 #define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE) 4097 /** Peripheral DMAMUX1 base address */ 4098 #define DMAMUX1_BASE (0x40022000u) 4099 /** Peripheral DMAMUX1 base pointer */ 4100 #define DMAMUX1 ((DMAMUX_Type *)DMAMUX1_BASE) 4101 /** Peripheral DMAMUX2 base address */ 4102 #define DMAMUX2_BASE (0x40023000u) 4103 /** Peripheral DMAMUX2 base pointer */ 4104 #define DMAMUX2 ((DMAMUX_Type *)DMAMUX2_BASE) 4105 /** Peripheral DMAMUX3 base address */ 4106 #define DMAMUX3_BASE (0x40024000u) 4107 /** Peripheral DMAMUX3 base pointer */ 4108 #define DMAMUX3 ((DMAMUX_Type *)DMAMUX3_BASE) 4109 /** Array initializer of DMAMUX peripheral base addresses */ 4110 #define DMAMUX_BASE_ADDRS { DMAMUX0_BASE, DMAMUX1_BASE, DMAMUX2_BASE, DMAMUX3_BASE } 4111 /** Array initializer of DMAMUX peripheral base pointers */ 4112 #define DMAMUX_BASE_PTRS { DMAMUX0, DMAMUX1, DMAMUX2, DMAMUX3 } 4113 4114 /*! 4115 * @} 4116 */ /* end of group DMAMUX_Peripheral_Access_Layer */ 4117 4118 4119 /* ---------------------------------------------------------------------------- 4120 -- EWM Peripheral Access Layer 4121 ---------------------------------------------------------------------------- */ 4122 4123 /*! 4124 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer 4125 * @{ 4126 */ 4127 4128 /** EWM - Register Layout Typedef */ 4129 typedef struct { 4130 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */ 4131 __O uint8_t SERV; /**< Service Register, offset: 0x1 */ 4132 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */ 4133 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */ 4134 } EWM_Type; 4135 4136 /* ---------------------------------------------------------------------------- 4137 -- EWM Register Masks 4138 ---------------------------------------------------------------------------- */ 4139 4140 /*! 4141 * @addtogroup EWM_Register_Masks EWM Register Masks 4142 * @{ 4143 */ 4144 4145 /*! @name CTRL - Control Register */ 4146 /*! @{ */ 4147 4148 #define EWM_CTRL_EWMEN_MASK (0x1U) 4149 #define EWM_CTRL_EWMEN_SHIFT (0U) 4150 /*! EWMEN - EWM enable. 4151 */ 4152 #define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) 4153 4154 #define EWM_CTRL_ASSIN_MASK (0x2U) 4155 #define EWM_CTRL_ASSIN_SHIFT (1U) 4156 /*! ASSIN - EWM_in's Assertion State Select. 4157 */ 4158 #define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK) 4159 4160 #define EWM_CTRL_INEN_MASK (0x4U) 4161 #define EWM_CTRL_INEN_SHIFT (2U) 4162 /*! INEN - Input Enable. 4163 */ 4164 #define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK) 4165 4166 #define EWM_CTRL_INTEN_MASK (0x8U) 4167 #define EWM_CTRL_INTEN_SHIFT (3U) 4168 /*! INTEN - Interrupt Enable. 4169 */ 4170 #define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) 4171 /*! @} */ 4172 4173 /*! @name SERV - Service Register */ 4174 /*! @{ */ 4175 4176 #define EWM_SERV_SERVICE_MASK (0xFFU) 4177 #define EWM_SERV_SERVICE_SHIFT (0U) 4178 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK) 4179 /*! @} */ 4180 4181 /*! @name CMPL - Compare Low Register */ 4182 /*! @{ */ 4183 4184 #define EWM_CMPL_COMPAREL_MASK (0xFFU) 4185 #define EWM_CMPL_COMPAREL_SHIFT (0U) 4186 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK) 4187 /*! @} */ 4188 4189 /*! @name CMPH - Compare High Register */ 4190 /*! @{ */ 4191 4192 #define EWM_CMPH_COMPAREH_MASK (0xFFU) 4193 #define EWM_CMPH_COMPAREH_SHIFT (0U) 4194 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK) 4195 /*! @} */ 4196 4197 4198 /*! 4199 * @} 4200 */ /* end of group EWM_Register_Masks */ 4201 4202 4203 /* EWM - Peripheral instance base addresses */ 4204 /** Peripheral EWM base address */ 4205 #define EWM_BASE (0x40061000u) 4206 /** Peripheral EWM base pointer */ 4207 #define EWM ((EWM_Type *)EWM_BASE) 4208 /** Array initializer of EWM peripheral base addresses */ 4209 #define EWM_BASE_ADDRS { EWM_BASE } 4210 /** Array initializer of EWM peripheral base pointers */ 4211 #define EWM_BASE_PTRS { EWM } 4212 /** Interrupt vectors for the EWM peripheral type */ 4213 #define EWM_IRQS { EWM_IRQn } 4214 4215 /*! 4216 * @} 4217 */ /* end of group EWM_Peripheral_Access_Layer */ 4218 4219 4220 /* ---------------------------------------------------------------------------- 4221 -- FTFA Peripheral Access Layer 4222 ---------------------------------------------------------------------------- */ 4223 4224 /*! 4225 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer 4226 * @{ 4227 */ 4228 4229 /** FTFA - Register Layout Typedef */ 4230 typedef struct { 4231 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */ 4232 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */ 4233 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */ 4234 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */ 4235 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */ 4236 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */ 4237 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */ 4238 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */ 4239 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */ 4240 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */ 4241 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */ 4242 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */ 4243 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */ 4244 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */ 4245 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */ 4246 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */ 4247 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */ 4248 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */ 4249 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */ 4250 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */ 4251 } FTFA_Type; 4252 4253 /* ---------------------------------------------------------------------------- 4254 -- FTFA Register Masks 4255 ---------------------------------------------------------------------------- */ 4256 4257 /*! 4258 * @addtogroup FTFA_Register_Masks FTFA Register Masks 4259 * @{ 4260 */ 4261 4262 /*! @name FSTAT - Flash Status Register */ 4263 /*! @{ */ 4264 4265 #define FTFA_FSTAT_MGSTAT0_MASK (0x1U) 4266 #define FTFA_FSTAT_MGSTAT0_SHIFT (0U) 4267 /*! MGSTAT0 - Memory Controller Command Completion Status Flag 4268 */ 4269 #define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK) 4270 4271 #define FTFA_FSTAT_FPVIOL_MASK (0x10U) 4272 #define FTFA_FSTAT_FPVIOL_SHIFT (4U) 4273 /*! FPVIOL - Flash Protection Violation Flag 4274 * 0b0..No protection violation detected 4275 * 0b1..Protection violation detected 4276 */ 4277 #define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK) 4278 4279 #define FTFA_FSTAT_ACCERR_MASK (0x20U) 4280 #define FTFA_FSTAT_ACCERR_SHIFT (5U) 4281 /*! ACCERR - Flash Access Error Flag 4282 * 0b0..No access error detected 4283 * 0b1..Access error detected 4284 */ 4285 #define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK) 4286 4287 #define FTFA_FSTAT_RDCOLERR_MASK (0x40U) 4288 #define FTFA_FSTAT_RDCOLERR_SHIFT (6U) 4289 /*! RDCOLERR - Flash Read Collision Error Flag 4290 * 0b0..No collision error detected 4291 * 0b1..Collision error detected 4292 */ 4293 #define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK) 4294 4295 #define FTFA_FSTAT_CCIF_MASK (0x80U) 4296 #define FTFA_FSTAT_CCIF_SHIFT (7U) 4297 /*! CCIF - Command Complete Interrupt Flag 4298 * 0b0..Flash command in progress 4299 * 0b1..Flash command has completed 4300 */ 4301 #define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK) 4302 /*! @} */ 4303 4304 /*! @name FCNFG - Flash Configuration Register */ 4305 /*! @{ */ 4306 4307 #define FTFA_FCNFG_ERSSUSP_MASK (0x10U) 4308 #define FTFA_FCNFG_ERSSUSP_SHIFT (4U) 4309 /*! ERSSUSP - Erase Suspend 4310 * 0b0..No suspend requested 4311 * 0b1..Suspend the current Erase Flash Sector command execution. 4312 */ 4313 #define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK) 4314 4315 #define FTFA_FCNFG_ERSAREQ_MASK (0x20U) 4316 #define FTFA_FCNFG_ERSAREQ_SHIFT (5U) 4317 /*! ERSAREQ - Erase All Request 4318 * 0b0..No request or request complete 4319 * 0b1..Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the 4320 * Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to 4321 * the unsecure state. 4322 */ 4323 #define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK) 4324 4325 #define FTFA_FCNFG_RDCOLLIE_MASK (0x40U) 4326 #define FTFA_FCNFG_RDCOLLIE_SHIFT (6U) 4327 /*! RDCOLLIE - Read Collision Error Interrupt Enable 4328 * 0b0..Read collision error interrupt disabled 4329 * 0b1..Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read 4330 * collision error is detected (see the description of FSTAT[RDCOLERR]). 4331 */ 4332 #define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK) 4333 4334 #define FTFA_FCNFG_CCIE_MASK (0x80U) 4335 #define FTFA_FCNFG_CCIE_SHIFT (7U) 4336 /*! CCIE - Command Complete Interrupt Enable 4337 * 0b0..Command complete interrupt disabled 4338 * 0b1..Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. 4339 */ 4340 #define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK) 4341 /*! @} */ 4342 4343 /*! @name FSEC - Flash Security Register */ 4344 /*! @{ */ 4345 4346 #define FTFA_FSEC_SEC_MASK (0x3U) 4347 #define FTFA_FSEC_SEC_SHIFT (0U) 4348 /*! SEC - Flash Security 4349 * 0b00..MCU security status is secure. 4350 * 0b01..MCU security status is secure. 4351 * 0b10..MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.) 4352 * 0b11..MCU security status is secure. 4353 */ 4354 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK) 4355 4356 #define FTFA_FSEC_FSLACC_MASK (0xCU) 4357 #define FTFA_FSEC_FSLACC_SHIFT (2U) 4358 /*! FSLACC - Factory Security Level Access Code 4359 * 0b00..NXP factory access granted 4360 * 0b01..NXP factory access denied 4361 * 0b10..NXP factory access denied 4362 * 0b11..NXP factory access granted 4363 */ 4364 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK) 4365 4366 #define FTFA_FSEC_MEEN_MASK (0x30U) 4367 #define FTFA_FSEC_MEEN_SHIFT (4U) 4368 /*! MEEN - Mass Erase Enable 4369 * 0b00..Mass erase is enabled 4370 * 0b01..Mass erase is enabled 4371 * 0b10..Mass erase is disabled 4372 * 0b11..Mass erase is enabled 4373 */ 4374 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK) 4375 4376 #define FTFA_FSEC_KEYEN_MASK (0xC0U) 4377 #define FTFA_FSEC_KEYEN_SHIFT (6U) 4378 /*! KEYEN - Backdoor Key Security Enable 4379 * 0b00..Backdoor key access disabled 4380 * 0b01..Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) 4381 * 0b10..Backdoor key access enabled 4382 * 0b11..Backdoor key access disabled 4383 */ 4384 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK) 4385 /*! @} */ 4386 4387 /*! @name FOPT - Flash Option Register */ 4388 /*! @{ */ 4389 4390 #define FTFA_FOPT_OPT_MASK (0xFFU) 4391 #define FTFA_FOPT_OPT_SHIFT (0U) 4392 /*! OPT - Nonvolatile Option 4393 */ 4394 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK) 4395 /*! @} */ 4396 4397 /*! @name FCCOB3 - Flash Common Command Object Registers */ 4398 /*! @{ */ 4399 4400 #define FTFA_FCCOB3_CCOBn_MASK (0xFFU) 4401 #define FTFA_FCCOB3_CCOBn_SHIFT (0U) 4402 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK) 4403 /*! @} */ 4404 4405 /*! @name FCCOB2 - Flash Common Command Object Registers */ 4406 /*! @{ */ 4407 4408 #define FTFA_FCCOB2_CCOBn_MASK (0xFFU) 4409 #define FTFA_FCCOB2_CCOBn_SHIFT (0U) 4410 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK) 4411 /*! @} */ 4412 4413 /*! @name FCCOB1 - Flash Common Command Object Registers */ 4414 /*! @{ */ 4415 4416 #define FTFA_FCCOB1_CCOBn_MASK (0xFFU) 4417 #define FTFA_FCCOB1_CCOBn_SHIFT (0U) 4418 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK) 4419 /*! @} */ 4420 4421 /*! @name FCCOB0 - Flash Common Command Object Registers */ 4422 /*! @{ */ 4423 4424 #define FTFA_FCCOB0_CCOBn_MASK (0xFFU) 4425 #define FTFA_FCCOB0_CCOBn_SHIFT (0U) 4426 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK) 4427 /*! @} */ 4428 4429 /*! @name FCCOB7 - Flash Common Command Object Registers */ 4430 /*! @{ */ 4431 4432 #define FTFA_FCCOB7_CCOBn_MASK (0xFFU) 4433 #define FTFA_FCCOB7_CCOBn_SHIFT (0U) 4434 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK) 4435 /*! @} */ 4436 4437 /*! @name FCCOB6 - Flash Common Command Object Registers */ 4438 /*! @{ */ 4439 4440 #define FTFA_FCCOB6_CCOBn_MASK (0xFFU) 4441 #define FTFA_FCCOB6_CCOBn_SHIFT (0U) 4442 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK) 4443 /*! @} */ 4444 4445 /*! @name FCCOB5 - Flash Common Command Object Registers */ 4446 /*! @{ */ 4447 4448 #define FTFA_FCCOB5_CCOBn_MASK (0xFFU) 4449 #define FTFA_FCCOB5_CCOBn_SHIFT (0U) 4450 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK) 4451 /*! @} */ 4452 4453 /*! @name FCCOB4 - Flash Common Command Object Registers */ 4454 /*! @{ */ 4455 4456 #define FTFA_FCCOB4_CCOBn_MASK (0xFFU) 4457 #define FTFA_FCCOB4_CCOBn_SHIFT (0U) 4458 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK) 4459 /*! @} */ 4460 4461 /*! @name FCCOBB - Flash Common Command Object Registers */ 4462 /*! @{ */ 4463 4464 #define FTFA_FCCOBB_CCOBn_MASK (0xFFU) 4465 #define FTFA_FCCOBB_CCOBn_SHIFT (0U) 4466 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK) 4467 /*! @} */ 4468 4469 /*! @name FCCOBA - Flash Common Command Object Registers */ 4470 /*! @{ */ 4471 4472 #define FTFA_FCCOBA_CCOBn_MASK (0xFFU) 4473 #define FTFA_FCCOBA_CCOBn_SHIFT (0U) 4474 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK) 4475 /*! @} */ 4476 4477 /*! @name FCCOB9 - Flash Common Command Object Registers */ 4478 /*! @{ */ 4479 4480 #define FTFA_FCCOB9_CCOBn_MASK (0xFFU) 4481 #define FTFA_FCCOB9_CCOBn_SHIFT (0U) 4482 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK) 4483 /*! @} */ 4484 4485 /*! @name FCCOB8 - Flash Common Command Object Registers */ 4486 /*! @{ */ 4487 4488 #define FTFA_FCCOB8_CCOBn_MASK (0xFFU) 4489 #define FTFA_FCCOB8_CCOBn_SHIFT (0U) 4490 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK) 4491 /*! @} */ 4492 4493 /*! @name FPROT3 - Program Flash Protection Registers */ 4494 /*! @{ */ 4495 4496 #define FTFA_FPROT3_PROT_MASK (0xFFU) 4497 #define FTFA_FPROT3_PROT_SHIFT (0U) 4498 /*! PROT - Program Flash Region Protect 4499 * 0b00000000..Program flash region is protected. 4500 * 0b00000001..Program flash region is not protected 4501 */ 4502 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK) 4503 /*! @} */ 4504 4505 /*! @name FPROT2 - Program Flash Protection Registers */ 4506 /*! @{ */ 4507 4508 #define FTFA_FPROT2_PROT_MASK (0xFFU) 4509 #define FTFA_FPROT2_PROT_SHIFT (0U) 4510 /*! PROT - Program Flash Region Protect 4511 * 0b00000000..Program flash region is protected. 4512 * 0b00000001..Program flash region is not protected 4513 */ 4514 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK) 4515 /*! @} */ 4516 4517 /*! @name FPROT1 - Program Flash Protection Registers */ 4518 /*! @{ */ 4519 4520 #define FTFA_FPROT1_PROT_MASK (0xFFU) 4521 #define FTFA_FPROT1_PROT_SHIFT (0U) 4522 /*! PROT - Program Flash Region Protect 4523 * 0b00000000..Program flash region is protected. 4524 * 0b00000001..Program flash region is not protected 4525 */ 4526 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK) 4527 /*! @} */ 4528 4529 /*! @name FPROT0 - Program Flash Protection Registers */ 4530 /*! @{ */ 4531 4532 #define FTFA_FPROT0_PROT_MASK (0xFFU) 4533 #define FTFA_FPROT0_PROT_SHIFT (0U) 4534 /*! PROT - Program Flash Region Protect 4535 * 0b00000000..Program flash region is protected. 4536 * 0b00000001..Program flash region is not protected 4537 */ 4538 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK) 4539 /*! @} */ 4540 4541 4542 /*! 4543 * @} 4544 */ /* end of group FTFA_Register_Masks */ 4545 4546 4547 /* FTFA - Peripheral instance base addresses */ 4548 /** Peripheral FTFA base address */ 4549 #define FTFA_BASE (0x40020000u) 4550 /** Peripheral FTFA base pointer */ 4551 #define FTFA ((FTFA_Type *)FTFA_BASE) 4552 /** Array initializer of FTFA peripheral base addresses */ 4553 #define FTFA_BASE_ADDRS { FTFA_BASE } 4554 /** Array initializer of FTFA peripheral base pointers */ 4555 #define FTFA_BASE_PTRS { FTFA } 4556 /** Interrupt vectors for the FTFA peripheral type */ 4557 #define FTFA_COMMAND_COMPLETE_IRQS { FTFA_IRQn } 4558 4559 /*! 4560 * @} 4561 */ /* end of group FTFA_Peripheral_Access_Layer */ 4562 4563 4564 /* ---------------------------------------------------------------------------- 4565 -- GPIO Peripheral Access Layer 4566 ---------------------------------------------------------------------------- */ 4567 4568 /*! 4569 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer 4570 * @{ 4571 */ 4572 4573 /** GPIO - Register Layout Typedef */ 4574 typedef struct { 4575 __IO uint8_t PDOR; /**< Port Data Output Register, offset: 0x0 */ 4576 uint8_t RESERVED_0[15]; 4577 __I uint8_t PDIR; /**< Port Data Input Register, offset: 0x10 */ 4578 uint8_t RESERVED_1[3]; 4579 __IO uint8_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ 4580 uint8_t RESERVED_2[7]; 4581 __IO uint8_t GACR; /**< GPIO Attribute Checker Register, offset: 0x1C */ 4582 } GPIO_Type; 4583 4584 /* ---------------------------------------------------------------------------- 4585 -- GPIO Register Masks 4586 ---------------------------------------------------------------------------- */ 4587 4588 /*! 4589 * @addtogroup GPIO_Register_Masks GPIO Register Masks 4590 * @{ 4591 */ 4592 4593 /*! @name PDOR - Port Data Output Register */ 4594 /*! @{ */ 4595 4596 #define GPIO_PDOR_PDO_MASK (0xFFU) 4597 #define GPIO_PDOR_PDO_SHIFT (0U) 4598 /*! PDO - Port Data Output 4599 * 0b00000000..Logic level 0 is driven on pin, provided pin is configured for general-purpose output. 4600 * 0b00000001..Logic level 1 is driven on pin, provided pin is configured for general-purpose output. 4601 */ 4602 #define GPIO_PDOR_PDO(x) (((uint8_t)(((uint8_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK) 4603 /*! @} */ 4604 4605 /*! @name PDIR - Port Data Input Register */ 4606 /*! @{ */ 4607 4608 #define GPIO_PDIR_PDI_MASK (0xFFU) 4609 #define GPIO_PDIR_PDI_SHIFT (0U) 4610 /*! PDI - Port Data Input 4611 * 0b00000000..Pin logic level is logic 0, or is not configured for use by digital function. 4612 * 0b00000001..Pin logic level is logic 1. 4613 */ 4614 #define GPIO_PDIR_PDI(x) (((uint8_t)(((uint8_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK) 4615 /*! @} */ 4616 4617 /*! @name PDDR - Port Data Direction Register */ 4618 /*! @{ */ 4619 4620 #define GPIO_PDDR_PDD_MASK (0xFFU) 4621 #define GPIO_PDDR_PDD_SHIFT (0U) 4622 /*! PDD - Port Data Direction 4623 * 0b00000000..Pin is configured as general-purpose input, for the GPIO function. 4624 * 0b00000001..Pin is configured as general-purpose output, for the GPIO function. 4625 */ 4626 #define GPIO_PDDR_PDD(x) (((uint8_t)(((uint8_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK) 4627 /*! @} */ 4628 4629 /*! @name GACR - GPIO Attribute Checker Register */ 4630 /*! @{ */ 4631 4632 #define GPIO_GACR_ACB_MASK (0x7U) 4633 #define GPIO_GACR_ACB_SHIFT (0U) 4634 /*! ACB - Attribute Check Byte 4635 * 0b000..User nonsecure: Read + Write; User Secure: Read + Write; Privileged Secure: Read + Write 4636 * 0b001..User nonsecure: Read; User Secure: Read + Write; Privileged Secure: Read + Write 4637 * 0b010..User nonsecure: None; User Secure: Read + Write; Privileged Secure: Read + Write 4638 * 0b011..User nonsecure: Read; User Secure: Read; Privileged Secure: Read + Write 4639 * 0b100..User nonsecure: None; User Secure: Read; Privileged Secure: Read + Write 4640 * 0b101..User nonsecure: None; User Secure: None; Privileged Secure: Read + Write 4641 * 0b110..User nonsecure: None; User Secure: None; Privileged Secure: Read 4642 * 0b111..User nonsecure: None; User Secure: None; Privileged Secure: None 4643 */ 4644 #define GPIO_GACR_ACB(x) (((uint8_t)(((uint8_t)(x)) << GPIO_GACR_ACB_SHIFT)) & GPIO_GACR_ACB_MASK) 4645 4646 #define GPIO_GACR_ROB_MASK (0x80U) 4647 #define GPIO_GACR_ROB_SHIFT (7U) 4648 /*! ROB - Read-Only Byte 4649 * 0b0..Writes to the ACB are allowed. 4650 * 0b1..Writes to the ACB are ignored. 4651 */ 4652 #define GPIO_GACR_ROB(x) (((uint8_t)(((uint8_t)(x)) << GPIO_GACR_ROB_SHIFT)) & GPIO_GACR_ROB_MASK) 4653 /*! @} */ 4654 4655 4656 /*! 4657 * @} 4658 */ /* end of group GPIO_Register_Masks */ 4659 4660 4661 /* GPIO - Peripheral instance base addresses */ 4662 /** Peripheral GPIOA base address */ 4663 #define GPIOA_BASE (0x400FF000u) 4664 /** Peripheral GPIOA base pointer */ 4665 #define GPIOA ((GPIO_Type *)GPIOA_BASE) 4666 /** Peripheral GPIOB base address */ 4667 #define GPIOB_BASE (0x400FF001u) 4668 /** Peripheral GPIOB base pointer */ 4669 #define GPIOB ((GPIO_Type *)GPIOB_BASE) 4670 /** Peripheral GPIOC base address */ 4671 #define GPIOC_BASE (0x400FF002u) 4672 /** Peripheral GPIOC base pointer */ 4673 #define GPIOC ((GPIO_Type *)GPIOC_BASE) 4674 /** Peripheral GPIOD base address */ 4675 #define GPIOD_BASE (0x400FF003u) 4676 /** Peripheral GPIOD base pointer */ 4677 #define GPIOD ((GPIO_Type *)GPIOD_BASE) 4678 /** Peripheral GPIOE base address */ 4679 #define GPIOE_BASE (0x400FF040u) 4680 /** Peripheral GPIOE base pointer */ 4681 #define GPIOE ((GPIO_Type *)GPIOE_BASE) 4682 /** Peripheral GPIOF base address */ 4683 #define GPIOF_BASE (0x400FF041u) 4684 /** Peripheral GPIOF base pointer */ 4685 #define GPIOF ((GPIO_Type *)GPIOF_BASE) 4686 /** Peripheral GPIOG base address */ 4687 #define GPIOG_BASE (0x400FF042u) 4688 /** Peripheral GPIOG base pointer */ 4689 #define GPIOG ((GPIO_Type *)GPIOG_BASE) 4690 /** Peripheral GPIOH base address */ 4691 #define GPIOH_BASE (0x400FF043u) 4692 /** Peripheral GPIOH base pointer */ 4693 #define GPIOH ((GPIO_Type *)GPIOH_BASE) 4694 /** Peripheral GPIOI base address */ 4695 #define GPIOI_BASE (0x400FF080u) 4696 /** Peripheral GPIOI base pointer */ 4697 #define GPIOI ((GPIO_Type *)GPIOI_BASE) 4698 /** Array initializer of GPIO peripheral base addresses */ 4699 #define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE, GPIOF_BASE, GPIOG_BASE, GPIOH_BASE, GPIOI_BASE } 4700 /** Array initializer of GPIO peripheral base pointers */ 4701 #define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH, GPIOI } 4702 4703 /*! 4704 * @} 4705 */ /* end of group GPIO_Peripheral_Access_Layer */ 4706 4707 4708 /* ---------------------------------------------------------------------------- 4709 -- I2C Peripheral Access Layer 4710 ---------------------------------------------------------------------------- */ 4711 4712 /*! 4713 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer 4714 * @{ 4715 */ 4716 4717 /** I2C - Register Layout Typedef */ 4718 typedef struct { 4719 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */ 4720 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */ 4721 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */ 4722 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */ 4723 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */ 4724 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */ 4725 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter Register, offset: 0x6 */ 4726 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */ 4727 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */ 4728 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */ 4729 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */ 4730 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */ 4731 } I2C_Type; 4732 4733 /* ---------------------------------------------------------------------------- 4734 -- I2C Register Masks 4735 ---------------------------------------------------------------------------- */ 4736 4737 /*! 4738 * @addtogroup I2C_Register_Masks I2C Register Masks 4739 * @{ 4740 */ 4741 4742 /*! @name A1 - I2C Address Register 1 */ 4743 /*! @{ */ 4744 4745 #define I2C_A1_AD_MASK (0xFEU) 4746 #define I2C_A1_AD_SHIFT (1U) 4747 /*! AD - Address 4748 */ 4749 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK) 4750 /*! @} */ 4751 4752 /*! @name F - I2C Frequency Divider register */ 4753 /*! @{ */ 4754 4755 #define I2C_F_ICR_MASK (0x3FU) 4756 #define I2C_F_ICR_SHIFT (0U) 4757 /*! ICR - ClockRate 4758 */ 4759 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK) 4760 4761 #define I2C_F_MULT_MASK (0xC0U) 4762 #define I2C_F_MULT_SHIFT (6U) 4763 /*! MULT - Multiplier Factor 4764 * 0b00..mul = 1 4765 * 0b01..mul = 2 4766 * 0b10..mul = 4 4767 * 0b11..Reserved 4768 */ 4769 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK) 4770 /*! @} */ 4771 4772 /*! @name C1 - I2C Control Register 1 */ 4773 /*! @{ */ 4774 4775 #define I2C_C1_DMAEN_MASK (0x1U) 4776 #define I2C_C1_DMAEN_SHIFT (0U) 4777 /*! DMAEN - DMA Enable 4778 * 0b0..All DMA signalling disabled. 4779 * 0b1..DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data 4780 * byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received 4781 * matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] 4782 * are set. If the direction of transfer is known from master to slave, then it is not required to check 4783 * S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from 4784 * the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be 4785 * used. When FACK = 1, an address or a data byte is transmitted. 4786 */ 4787 #define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK) 4788 4789 #define I2C_C1_WUEN_MASK (0x2U) 4790 #define I2C_C1_WUEN_SHIFT (1U) 4791 /*! WUEN - Wakeup Enable 4792 * 0b0..Normal operation. No interrupt generated when address matching in low power mode. 4793 * 0b1..Enables the wakeup function in low power mode. 4794 */ 4795 #define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK) 4796 4797 #define I2C_C1_RSTA_MASK (0x4U) 4798 #define I2C_C1_RSTA_SHIFT (2U) 4799 /*! RSTA - Repeat START 4800 */ 4801 #define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK) 4802 4803 #define I2C_C1_TXAK_MASK (0x8U) 4804 #define I2C_C1_TXAK_SHIFT (3U) 4805 /*! TXAK - Transmit Acknowledge Enable 4806 * 0b0..An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the 4807 * current receiving byte (if FACK is set). 4808 * 0b1..No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the 4809 * current receiving data byte (if FACK is set). 4810 */ 4811 #define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK) 4812 4813 #define I2C_C1_TX_MASK (0x10U) 4814 #define I2C_C1_TX_SHIFT (4U) 4815 /*! TX - Transmit Mode Select 4816 * 0b0..Receive 4817 * 0b1..Transmit 4818 */ 4819 #define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK) 4820 4821 #define I2C_C1_MST_MASK (0x20U) 4822 #define I2C_C1_MST_SHIFT (5U) 4823 /*! MST - Master Mode Select 4824 * 0b0..Slave mode 4825 * 0b1..Master mode 4826 */ 4827 #define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK) 4828 4829 #define I2C_C1_IICIE_MASK (0x40U) 4830 #define I2C_C1_IICIE_SHIFT (6U) 4831 /*! IICIE - I2C Interrupt Enable 4832 * 0b0..Disabled 4833 * 0b1..Enabled 4834 */ 4835 #define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK) 4836 4837 #define I2C_C1_IICEN_MASK (0x80U) 4838 #define I2C_C1_IICEN_SHIFT (7U) 4839 /*! IICEN - I2C Enable 4840 * 0b0..Disabled 4841 * 0b1..Enabled 4842 */ 4843 #define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK) 4844 /*! @} */ 4845 4846 /*! @name S - I2C Status register */ 4847 /*! @{ */ 4848 4849 #define I2C_S_RXAK_MASK (0x1U) 4850 #define I2C_S_RXAK_SHIFT (0U) 4851 /*! RXAK - Receive Acknowledge 4852 * 0b0..Acknowledge signal was received after the completion of one byte of data transmission on the bus 4853 * 0b1..No acknowledge signal detected 4854 */ 4855 #define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK) 4856 4857 #define I2C_S_IICIF_MASK (0x2U) 4858 #define I2C_S_IICIF_SHIFT (1U) 4859 /*! IICIF - Interrupt Flag 4860 * 0b0..No interrupt pending 4861 * 0b1..Interrupt pending 4862 */ 4863 #define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK) 4864 4865 #define I2C_S_SRW_MASK (0x4U) 4866 #define I2C_S_SRW_SHIFT (2U) 4867 /*! SRW - Slave Read/Write 4868 * 0b0..Slave receive, master writing to slave 4869 * 0b1..Slave transmit, master reading from slave 4870 */ 4871 #define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK) 4872 4873 #define I2C_S_RAM_MASK (0x8U) 4874 #define I2C_S_RAM_SHIFT (3U) 4875 /*! RAM - Range Address Match 4876 * 0b0..Not addressed 4877 * 0b1..Addressed as a slave 4878 */ 4879 #define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK) 4880 4881 #define I2C_S_ARBL_MASK (0x10U) 4882 #define I2C_S_ARBL_SHIFT (4U) 4883 /*! ARBL - Arbitration Lost 4884 * 0b0..Standard bus operation. 4885 * 0b1..Loss of arbitration. 4886 */ 4887 #define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK) 4888 4889 #define I2C_S_BUSY_MASK (0x20U) 4890 #define I2C_S_BUSY_SHIFT (5U) 4891 /*! BUSY - Bus Busy 4892 * 0b0..Bus is idle 4893 * 0b1..Bus is busy 4894 */ 4895 #define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK) 4896 4897 #define I2C_S_IAAS_MASK (0x40U) 4898 #define I2C_S_IAAS_SHIFT (6U) 4899 /*! IAAS - Addressed As A Slave 4900 * 0b0..Not addressed 4901 * 0b1..Addressed as a slave 4902 */ 4903 #define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK) 4904 4905 #define I2C_S_TCF_MASK (0x80U) 4906 #define I2C_S_TCF_SHIFT (7U) 4907 /*! TCF - Transfer Complete Flag 4908 * 0b0..Transfer in progress 4909 * 0b1..Transfer complete 4910 */ 4911 #define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK) 4912 /*! @} */ 4913 4914 /*! @name D - I2C Data I/O register */ 4915 /*! @{ */ 4916 4917 #define I2C_D_DATA_MASK (0xFFU) 4918 #define I2C_D_DATA_SHIFT (0U) 4919 /*! DATA - Data 4920 */ 4921 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK) 4922 /*! @} */ 4923 4924 /*! @name C2 - I2C Control Register 2 */ 4925 /*! @{ */ 4926 4927 #define I2C_C2_AD_MASK (0x7U) 4928 #define I2C_C2_AD_SHIFT (0U) 4929 /*! AD - Slave Address 4930 */ 4931 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK) 4932 4933 #define I2C_C2_RMEN_MASK (0x8U) 4934 #define I2C_C2_RMEN_SHIFT (3U) 4935 /*! RMEN - Range Address Matching Enable 4936 * 0b0..Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers. 4937 * 0b1..Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers. 4938 */ 4939 #define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK) 4940 4941 #define I2C_C2_SBRC_MASK (0x10U) 4942 #define I2C_C2_SBRC_SHIFT (4U) 4943 /*! SBRC - Slave Baud Rate Control 4944 * 0b0..The slave baud rate follows the master baud rate and clock stretching may occur 4945 * 0b1..Slave baud rate is independent of the master baud rate 4946 */ 4947 #define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK) 4948 4949 #define I2C_C2_HDRS_MASK (0x20U) 4950 #define I2C_C2_HDRS_SHIFT (5U) 4951 /*! HDRS - High Drive Select 4952 * 0b0..Normal drive mode 4953 * 0b1..High drive mode 4954 */ 4955 #define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK) 4956 4957 #define I2C_C2_ADEXT_MASK (0x40U) 4958 #define I2C_C2_ADEXT_SHIFT (6U) 4959 /*! ADEXT - Address Extension 4960 * 0b0..7-bit address scheme 4961 * 0b1..10-bit address scheme 4962 */ 4963 #define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK) 4964 4965 #define I2C_C2_GCAEN_MASK (0x80U) 4966 #define I2C_C2_GCAEN_SHIFT (7U) 4967 /*! GCAEN - General Call Address Enable 4968 * 0b0..Disabled 4969 * 0b1..Enabled 4970 */ 4971 #define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK) 4972 /*! @} */ 4973 4974 /*! @name FLT - I2C Programmable Input Glitch Filter Register */ 4975 /*! @{ */ 4976 4977 #define I2C_FLT_FLT_MASK (0xFU) 4978 #define I2C_FLT_FLT_SHIFT (0U) 4979 /*! FLT - I2C Programmable Filter Factor 4980 * 0b0000..No filter/bypass 4981 */ 4982 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK) 4983 4984 #define I2C_FLT_STARTF_MASK (0x10U) 4985 #define I2C_FLT_STARTF_SHIFT (4U) 4986 /*! STARTF - I2C Bus Start Detect Flag 4987 * 0b0..No start happens on I2C bus 4988 * 0b1..Start detected on I2C bus 4989 */ 4990 #define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK) 4991 4992 #define I2C_FLT_SSIE_MASK (0x20U) 4993 #define I2C_FLT_SSIE_SHIFT (5U) 4994 /*! SSIE - I2C Bus Stop or Start Interrupt Enable 4995 * 0b0..Stop or start detection interrupt is disabled 4996 * 0b1..Stop or start detection interrupt is enabled 4997 */ 4998 #define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK) 4999 5000 #define I2C_FLT_STOPF_MASK (0x40U) 5001 #define I2C_FLT_STOPF_SHIFT (6U) 5002 /*! STOPF - I2C Bus Stop Detect Flag 5003 * 0b0..No stop happens on I2C bus 5004 * 0b1..Stop detected on I2C bus 5005 */ 5006 #define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK) 5007 5008 #define I2C_FLT_SHEN_MASK (0x80U) 5009 #define I2C_FLT_SHEN_SHIFT (7U) 5010 /*! SHEN - Stop Hold Enable 5011 * 0b0..Stop holdoff is disabled. The MCU's entry to stop mode is not gated. 5012 * 0b1..Stop holdoff is enabled. 5013 */ 5014 #define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK) 5015 /*! @} */ 5016 5017 /*! @name RA - I2C Range Address register */ 5018 /*! @{ */ 5019 5020 #define I2C_RA_RAD_MASK (0xFEU) 5021 #define I2C_RA_RAD_SHIFT (1U) 5022 /*! RAD - Range Slave Address 5023 */ 5024 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK) 5025 /*! @} */ 5026 5027 /*! @name SMB - I2C SMBus Control and Status register */ 5028 /*! @{ */ 5029 5030 #define I2C_SMB_SHTF2IE_MASK (0x1U) 5031 #define I2C_SMB_SHTF2IE_SHIFT (0U) 5032 /*! SHTF2IE - SHTF2 Interrupt Enable 5033 * 0b0..SHTF2 interrupt is disabled 5034 * 0b1..SHTF2 interrupt is enabled 5035 */ 5036 #define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK) 5037 5038 #define I2C_SMB_SHTF2_MASK (0x2U) 5039 #define I2C_SMB_SHTF2_SHIFT (1U) 5040 /*! SHTF2 - SCL High Timeout Flag 2 5041 * 0b0..No SCL high and SDA low timeout occurs 5042 * 0b1..SCL high and SDA low timeout occurs 5043 */ 5044 #define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK) 5045 5046 #define I2C_SMB_SHTF1_MASK (0x4U) 5047 #define I2C_SMB_SHTF1_SHIFT (2U) 5048 /*! SHTF1 - SCL High Timeout Flag 1 5049 * 0b0..No SCL high and SDA high timeout occurs 5050 * 0b1..SCL high and SDA high timeout occurs 5051 */ 5052 #define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK) 5053 5054 #define I2C_SMB_SLTF_MASK (0x8U) 5055 #define I2C_SMB_SLTF_SHIFT (3U) 5056 /*! SLTF - SCL Low Timeout Flag 5057 * 0b0..No low timeout occurs 5058 * 0b1..Low timeout occurs 5059 */ 5060 #define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK) 5061 5062 #define I2C_SMB_TCKSEL_MASK (0x10U) 5063 #define I2C_SMB_TCKSEL_SHIFT (4U) 5064 /*! TCKSEL - Timeout Counter Clock Select 5065 * 0b0..Timeout counter counts at the frequency of the I2C module clock / 64 5066 * 0b1..Timeout counter counts at the frequency of the I2C module clock 5067 */ 5068 #define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK) 5069 5070 #define I2C_SMB_SIICAEN_MASK (0x20U) 5071 #define I2C_SMB_SIICAEN_SHIFT (5U) 5072 /*! SIICAEN - Second I2C Address Enable 5073 * 0b0..I2C address register 2 matching is disabled 5074 * 0b1..I2C address register 2 matching is enabled 5075 */ 5076 #define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK) 5077 5078 #define I2C_SMB_ALERTEN_MASK (0x40U) 5079 #define I2C_SMB_ALERTEN_SHIFT (6U) 5080 /*! ALERTEN - SMBus Alert Response Address Enable 5081 * 0b0..SMBus alert response address matching is disabled 5082 * 0b1..SMBus alert response address matching is enabled 5083 */ 5084 #define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK) 5085 5086 #define I2C_SMB_FACK_MASK (0x80U) 5087 #define I2C_SMB_FACK_SHIFT (7U) 5088 /*! FACK - Fast NACK/ACK Enable 5089 * 0b0..An ACK or NACK is sent on the following receiving data byte 5090 * 0b1..Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. 5091 */ 5092 #define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK) 5093 /*! @} */ 5094 5095 /*! @name A2 - I2C Address Register 2 */ 5096 /*! @{ */ 5097 5098 #define I2C_A2_SAD_MASK (0xFEU) 5099 #define I2C_A2_SAD_SHIFT (1U) 5100 /*! SAD - SMBus Address 5101 */ 5102 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK) 5103 /*! @} */ 5104 5105 /*! @name SLTH - I2C SCL Low Timeout Register High */ 5106 /*! @{ */ 5107 5108 #define I2C_SLTH_SSLT_MASK (0xFFU) 5109 #define I2C_SLTH_SSLT_SHIFT (0U) 5110 /*! SSLT - SSLT[15:8] 5111 */ 5112 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK) 5113 /*! @} */ 5114 5115 /*! @name SLTL - I2C SCL Low Timeout Register Low */ 5116 /*! @{ */ 5117 5118 #define I2C_SLTL_SSLT_MASK (0xFFU) 5119 #define I2C_SLTL_SSLT_SHIFT (0U) 5120 /*! SSLT - SSLT[7:0] 5121 */ 5122 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK) 5123 /*! @} */ 5124 5125 5126 /*! 5127 * @} 5128 */ /* end of group I2C_Register_Masks */ 5129 5130 5131 /* I2C - Peripheral instance base addresses */ 5132 /** Peripheral I2C0 base address */ 5133 #define I2C0_BASE (0x40067000u) 5134 /** Peripheral I2C0 base pointer */ 5135 #define I2C0 ((I2C_Type *)I2C0_BASE) 5136 /** Peripheral I2C1 base address */ 5137 #define I2C1_BASE (0x40068000u) 5138 /** Peripheral I2C1 base pointer */ 5139 #define I2C1 ((I2C_Type *)I2C1_BASE) 5140 /** Array initializer of I2C peripheral base addresses */ 5141 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE } 5142 /** Array initializer of I2C peripheral base pointers */ 5143 #define I2C_BASE_PTRS { I2C0, I2C1 } 5144 /** Interrupt vectors for the I2C peripheral type */ 5145 #define I2C_IRQS { I2C0_I2C1_IRQn, I2C0_I2C1_IRQn } 5146 5147 /*! 5148 * @} 5149 */ /* end of group I2C_Peripheral_Access_Layer */ 5150 5151 5152 /* ---------------------------------------------------------------------------- 5153 -- LLWU Peripheral Access Layer 5154 ---------------------------------------------------------------------------- */ 5155 5156 /*! 5157 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer 5158 * @{ 5159 */ 5160 5161 /** LLWU - Register Layout Typedef */ 5162 typedef struct { 5163 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ 5164 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */ 5165 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */ 5166 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */ 5167 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */ 5168 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */ 5169 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */ 5170 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */ 5171 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */ 5172 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */ 5173 } LLWU_Type; 5174 5175 /* ---------------------------------------------------------------------------- 5176 -- LLWU Register Masks 5177 ---------------------------------------------------------------------------- */ 5178 5179 /*! 5180 * @addtogroup LLWU_Register_Masks LLWU Register Masks 5181 * @{ 5182 */ 5183 5184 /*! @name PE1 - LLWU Pin Enable 1 register */ 5185 /*! @{ */ 5186 5187 #define LLWU_PE1_WUPE0_MASK (0x3U) 5188 #define LLWU_PE1_WUPE0_SHIFT (0U) 5189 /*! WUPE0 - Wakeup Pin Enable For LLWU_P0 5190 * 0b00..External input pin disabled as wakeup input 5191 * 0b01..External input pin enabled with rising edge detection 5192 * 0b10..External input pin enabled with falling edge detection 5193 * 0b11..External input pin enabled with any change detection 5194 */ 5195 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK) 5196 5197 #define LLWU_PE1_WUPE1_MASK (0xCU) 5198 #define LLWU_PE1_WUPE1_SHIFT (2U) 5199 /*! WUPE1 - Wakeup Pin Enable For LLWU_P1 5200 * 0b00..External input pin disabled as wakeup input 5201 * 0b01..External input pin enabled with rising edge detection 5202 * 0b10..External input pin enabled with falling edge detection 5203 * 0b11..External input pin enabled with any change detection 5204 */ 5205 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK) 5206 5207 #define LLWU_PE1_WUPE2_MASK (0x30U) 5208 #define LLWU_PE1_WUPE2_SHIFT (4U) 5209 /*! WUPE2 - Wakeup Pin Enable For LLWU_P2 5210 * 0b00..External input pin disabled as wakeup input 5211 * 0b01..External input pin enabled with rising edge detection 5212 * 0b10..External input pin enabled with falling edge detection 5213 * 0b11..External input pin enabled with any change detection 5214 */ 5215 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK) 5216 5217 #define LLWU_PE1_WUPE3_MASK (0xC0U) 5218 #define LLWU_PE1_WUPE3_SHIFT (6U) 5219 /*! WUPE3 - Wakeup Pin Enable For LLWU_P3 5220 * 0b00..External input pin disabled as wakeup input 5221 * 0b01..External input pin enabled with rising edge detection 5222 * 0b10..External input pin enabled with falling edge detection 5223 * 0b11..External input pin enabled with any change detection 5224 */ 5225 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK) 5226 /*! @} */ 5227 5228 /*! @name PE2 - LLWU Pin Enable 2 register */ 5229 /*! @{ */ 5230 5231 #define LLWU_PE2_WUPE4_MASK (0x3U) 5232 #define LLWU_PE2_WUPE4_SHIFT (0U) 5233 /*! WUPE4 - Wakeup Pin Enable For LLWU_P4 5234 * 0b00..External input pin disabled as wakeup input 5235 * 0b01..External input pin enabled with rising edge detection 5236 * 0b10..External input pin enabled with falling edge detection 5237 * 0b11..External input pin enabled with any change detection 5238 */ 5239 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK) 5240 5241 #define LLWU_PE2_WUPE5_MASK (0xCU) 5242 #define LLWU_PE2_WUPE5_SHIFT (2U) 5243 /*! WUPE5 - Wakeup Pin Enable For LLWU_P5 5244 * 0b00..External input pin disabled as wakeup input 5245 * 0b01..External input pin enabled with rising edge detection 5246 * 0b10..External input pin enabled with falling edge detection 5247 * 0b11..External input pin enabled with any change detection 5248 */ 5249 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK) 5250 5251 #define LLWU_PE2_WUPE6_MASK (0x30U) 5252 #define LLWU_PE2_WUPE6_SHIFT (4U) 5253 /*! WUPE6 - Wakeup Pin Enable For LLWU_P6 5254 * 0b00..External input pin disabled as wakeup input 5255 * 0b01..External input pin enabled with rising edge detection 5256 * 0b10..External input pin enabled with falling edge detection 5257 * 0b11..External input pin enabled with any change detection 5258 */ 5259 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK) 5260 5261 #define LLWU_PE2_WUPE7_MASK (0xC0U) 5262 #define LLWU_PE2_WUPE7_SHIFT (6U) 5263 /*! WUPE7 - Wakeup Pin Enable For LLWU_P7 5264 * 0b00..External input pin disabled as wakeup input 5265 * 0b01..External input pin enabled with rising edge detection 5266 * 0b10..External input pin enabled with falling edge detection 5267 * 0b11..External input pin enabled with any change detection 5268 */ 5269 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK) 5270 /*! @} */ 5271 5272 /*! @name PE3 - LLWU Pin Enable 3 register */ 5273 /*! @{ */ 5274 5275 #define LLWU_PE3_WUPE8_MASK (0x3U) 5276 #define LLWU_PE3_WUPE8_SHIFT (0U) 5277 /*! WUPE8 - Wakeup Pin Enable For LLWU_P8 5278 * 0b00..External input pin disabled as wakeup input 5279 * 0b01..External input pin enabled with rising edge detection 5280 * 0b10..External input pin enabled with falling edge detection 5281 * 0b11..External input pin enabled with any change detection 5282 */ 5283 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK) 5284 5285 #define LLWU_PE3_WUPE9_MASK (0xCU) 5286 #define LLWU_PE3_WUPE9_SHIFT (2U) 5287 /*! WUPE9 - Wakeup Pin Enable For LLWU_P9 5288 * 0b00..External input pin disabled as wakeup input 5289 * 0b01..External input pin enabled with rising edge detection 5290 * 0b10..External input pin enabled with falling edge detection 5291 * 0b11..External input pin enabled with any change detection 5292 */ 5293 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK) 5294 5295 #define LLWU_PE3_WUPE10_MASK (0x30U) 5296 #define LLWU_PE3_WUPE10_SHIFT (4U) 5297 /*! WUPE10 - Wakeup Pin Enable For LLWU_P10 5298 * 0b00..External input pin disabled as wakeup input 5299 * 0b01..External input pin enabled with rising edge detection 5300 * 0b10..External input pin enabled with falling edge detection 5301 * 0b11..External input pin enabled with any change detection 5302 */ 5303 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK) 5304 5305 #define LLWU_PE3_WUPE11_MASK (0xC0U) 5306 #define LLWU_PE3_WUPE11_SHIFT (6U) 5307 /*! WUPE11 - Wakeup Pin Enable For LLWU_P11 5308 * 0b00..External input pin disabled as wakeup input 5309 * 0b01..External input pin enabled with rising edge detection 5310 * 0b10..External input pin enabled with falling edge detection 5311 * 0b11..External input pin enabled with any change detection 5312 */ 5313 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK) 5314 /*! @} */ 5315 5316 /*! @name PE4 - LLWU Pin Enable 4 register */ 5317 /*! @{ */ 5318 5319 #define LLWU_PE4_WUPE12_MASK (0x3U) 5320 #define LLWU_PE4_WUPE12_SHIFT (0U) 5321 /*! WUPE12 - Wakeup Pin Enable For LLWU_P12 5322 * 0b00..External input pin disabled as wakeup input 5323 * 0b01..External input pin enabled with rising edge detection 5324 * 0b10..External input pin enabled with falling edge detection 5325 * 0b11..External input pin enabled with any change detection 5326 */ 5327 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK) 5328 5329 #define LLWU_PE4_WUPE13_MASK (0xCU) 5330 #define LLWU_PE4_WUPE13_SHIFT (2U) 5331 /*! WUPE13 - Wakeup Pin Enable For LLWU_P13 5332 * 0b00..External input pin disabled as wakeup input 5333 * 0b01..External input pin enabled with rising edge detection 5334 * 0b10..External input pin enabled with falling edge detection 5335 * 0b11..External input pin enabled with any change detection 5336 */ 5337 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK) 5338 5339 #define LLWU_PE4_WUPE14_MASK (0x30U) 5340 #define LLWU_PE4_WUPE14_SHIFT (4U) 5341 /*! WUPE14 - Wakeup Pin Enable For LLWU_P14 5342 * 0b00..External input pin disabled as wakeup input 5343 * 0b01..External input pin enabled with rising edge detection 5344 * 0b10..External input pin enabled with falling edge detection 5345 * 0b11..External input pin enabled with any change detection 5346 */ 5347 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK) 5348 5349 #define LLWU_PE4_WUPE15_MASK (0xC0U) 5350 #define LLWU_PE4_WUPE15_SHIFT (6U) 5351 /*! WUPE15 - Wakeup Pin Enable For LLWU_P15 5352 * 0b00..External input pin disabled as wakeup input 5353 * 0b01..External input pin enabled with rising edge detection 5354 * 0b10..External input pin enabled with falling edge detection 5355 * 0b11..External input pin enabled with any change detection 5356 */ 5357 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK) 5358 /*! @} */ 5359 5360 /*! @name ME - LLWU Module Enable register */ 5361 /*! @{ */ 5362 5363 #define LLWU_ME_WUME0_MASK (0x1U) 5364 #define LLWU_ME_WUME0_SHIFT (0U) 5365 /*! WUME0 - Wakeup Module Enable For Module 0 5366 * 0b0..Internal module flag not used as wakeup source 5367 * 0b1..Internal module flag used as wakeup source 5368 */ 5369 #define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK) 5370 5371 #define LLWU_ME_WUME1_MASK (0x2U) 5372 #define LLWU_ME_WUME1_SHIFT (1U) 5373 /*! WUME1 - Wakeup Module Enable for Module 1 5374 * 0b0..Internal module flag not used as wakeup source 5375 * 0b1..Internal module flag used as wakeup source 5376 */ 5377 #define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK) 5378 5379 #define LLWU_ME_WUME2_MASK (0x4U) 5380 #define LLWU_ME_WUME2_SHIFT (2U) 5381 /*! WUME2 - Wakeup Module Enable For Module 2 5382 * 0b0..Internal module flag not used as wakeup source 5383 * 0b1..Internal module flag used as wakeup source 5384 */ 5385 #define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK) 5386 5387 #define LLWU_ME_WUME3_MASK (0x8U) 5388 #define LLWU_ME_WUME3_SHIFT (3U) 5389 /*! WUME3 - Wakeup Module Enable For Module 3 5390 * 0b0..Internal module flag not used as wakeup source 5391 * 0b1..Internal module flag used as wakeup source 5392 */ 5393 #define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK) 5394 5395 #define LLWU_ME_WUME4_MASK (0x10U) 5396 #define LLWU_ME_WUME4_SHIFT (4U) 5397 /*! WUME4 - Wakeup Module Enable For Module 4 5398 * 0b0..Internal module flag not used as wakeup source 5399 * 0b1..Internal module flag used as wakeup source 5400 */ 5401 #define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK) 5402 5403 #define LLWU_ME_WUME5_MASK (0x20U) 5404 #define LLWU_ME_WUME5_SHIFT (5U) 5405 /*! WUME5 - Wakeup Module Enable For Module 5 5406 * 0b0..Internal module flag not used as wakeup source 5407 * 0b1..Internal module flag used as wakeup source 5408 */ 5409 #define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK) 5410 5411 #define LLWU_ME_WUME6_MASK (0x40U) 5412 #define LLWU_ME_WUME6_SHIFT (6U) 5413 /*! WUME6 - Wakeup Module Enable For Module 6 5414 * 0b0..Internal module flag not used as wakeup source 5415 * 0b1..Internal module flag used as wakeup source 5416 */ 5417 #define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK) 5418 5419 #define LLWU_ME_WUME7_MASK (0x80U) 5420 #define LLWU_ME_WUME7_SHIFT (7U) 5421 /*! WUME7 - Wakeup Module Enable For Module 7 5422 * 0b0..Internal module flag not used as wakeup source 5423 * 0b1..Internal module flag used as wakeup source 5424 */ 5425 #define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK) 5426 /*! @} */ 5427 5428 /*! @name F1 - LLWU Flag 1 register */ 5429 /*! @{ */ 5430 5431 #define LLWU_F1_WUF0_MASK (0x1U) 5432 #define LLWU_F1_WUF0_SHIFT (0U) 5433 /*! WUF0 - Wakeup Flag For LLWU_P0 5434 * 0b0..LLWU_P0 input was not a wakeup source 5435 * 0b1..LLWU_P0 input was a wakeup source 5436 */ 5437 #define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK) 5438 5439 #define LLWU_F1_WUF1_MASK (0x2U) 5440 #define LLWU_F1_WUF1_SHIFT (1U) 5441 /*! WUF1 - Wakeup Flag For LLWU_P1 5442 * 0b0..LLWU_P1 input was not a wakeup source 5443 * 0b1..LLWU_P1 input was a wakeup source 5444 */ 5445 #define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK) 5446 5447 #define LLWU_F1_WUF2_MASK (0x4U) 5448 #define LLWU_F1_WUF2_SHIFT (2U) 5449 /*! WUF2 - Wakeup Flag For LLWU_P2 5450 * 0b0..LLWU_P2 input was not a wakeup source 5451 * 0b1..LLWU_P2 input was a wakeup source 5452 */ 5453 #define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK) 5454 5455 #define LLWU_F1_WUF3_MASK (0x8U) 5456 #define LLWU_F1_WUF3_SHIFT (3U) 5457 /*! WUF3 - Wakeup Flag For LLWU_P3 5458 * 0b0..LLWU_P3 input was not a wake-up source 5459 * 0b1..LLWU_P3 input was a wake-up source 5460 */ 5461 #define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK) 5462 5463 #define LLWU_F1_WUF4_MASK (0x10U) 5464 #define LLWU_F1_WUF4_SHIFT (4U) 5465 /*! WUF4 - Wakeup Flag For LLWU_P4 5466 * 0b0..LLWU_P4 input was not a wakeup source 5467 * 0b1..LLWU_P4 input was a wakeup source 5468 */ 5469 #define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK) 5470 5471 #define LLWU_F1_WUF5_MASK (0x20U) 5472 #define LLWU_F1_WUF5_SHIFT (5U) 5473 /*! WUF5 - Wakeup Flag For LLWU_P5 5474 * 0b0..LLWU_P5 input was not a wakeup source 5475 * 0b1..LLWU_P5 input was a wakeup source 5476 */ 5477 #define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK) 5478 5479 #define LLWU_F1_WUF6_MASK (0x40U) 5480 #define LLWU_F1_WUF6_SHIFT (6U) 5481 /*! WUF6 - Wakeup Flag For LLWU_P6 5482 * 0b0..LLWU_P6 input was not a wakeup source 5483 * 0b1..LLWU_P6 input was a wakeup source 5484 */ 5485 #define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK) 5486 5487 #define LLWU_F1_WUF7_MASK (0x80U) 5488 #define LLWU_F1_WUF7_SHIFT (7U) 5489 /*! WUF7 - Wakeup Flag For LLWU_P7 5490 * 0b0..LLWU_P7 input was not a wakeup source 5491 * 0b1..LLWU_P7 input was a wakeup source 5492 */ 5493 #define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK) 5494 /*! @} */ 5495 5496 /*! @name F2 - LLWU Flag 2 register */ 5497 /*! @{ */ 5498 5499 #define LLWU_F2_WUF8_MASK (0x1U) 5500 #define LLWU_F2_WUF8_SHIFT (0U) 5501 /*! WUF8 - Wakeup Flag For LLWU_P8 5502 * 0b0..LLWU_P8 input was not a wakeup source 5503 * 0b1..LLWU_P8 input was a wakeup source 5504 */ 5505 #define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK) 5506 5507 #define LLWU_F2_WUF9_MASK (0x2U) 5508 #define LLWU_F2_WUF9_SHIFT (1U) 5509 /*! WUF9 - Wakeup Flag For LLWU_P9 5510 * 0b0..LLWU_P9 input was not a wakeup source 5511 * 0b1..LLWU_P9 input was a wakeup source 5512 */ 5513 #define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK) 5514 5515 #define LLWU_F2_WUF10_MASK (0x4U) 5516 #define LLWU_F2_WUF10_SHIFT (2U) 5517 /*! WUF10 - Wakeup Flag For LLWU_P10 5518 * 0b0..LLWU_P10 input was not a wakeup source 5519 * 0b1..LLWU_P10 input was a wakeup source 5520 */ 5521 #define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK) 5522 5523 #define LLWU_F2_WUF11_MASK (0x8U) 5524 #define LLWU_F2_WUF11_SHIFT (3U) 5525 /*! WUF11 - Wakeup Flag For LLWU_P11 5526 * 0b0..LLWU_P11 input was not a wakeup source 5527 * 0b1..LLWU_P11 input was a wakeup source 5528 */ 5529 #define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK) 5530 5531 #define LLWU_F2_WUF12_MASK (0x10U) 5532 #define LLWU_F2_WUF12_SHIFT (4U) 5533 /*! WUF12 - Wakeup Flag For LLWU_P12 5534 * 0b0..LLWU_P12 input was not a wakeup source 5535 * 0b1..LLWU_P12 input was a wakeup source 5536 */ 5537 #define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK) 5538 5539 #define LLWU_F2_WUF13_MASK (0x20U) 5540 #define LLWU_F2_WUF13_SHIFT (5U) 5541 /*! WUF13 - Wakeup Flag For LLWU_P13 5542 * 0b0..LLWU_P13 input was not a wakeup source 5543 * 0b1..LLWU_P13 input was a wakeup source 5544 */ 5545 #define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK) 5546 5547 #define LLWU_F2_WUF14_MASK (0x40U) 5548 #define LLWU_F2_WUF14_SHIFT (6U) 5549 /*! WUF14 - Wakeup Flag For LLWU_P14 5550 * 0b0..LLWU_P14 input was not a wakeup source 5551 * 0b1..LLWU_P14 input was a wakeup source 5552 */ 5553 #define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK) 5554 5555 #define LLWU_F2_WUF15_MASK (0x80U) 5556 #define LLWU_F2_WUF15_SHIFT (7U) 5557 /*! WUF15 - Wakeup Flag For LLWU_P15 5558 * 0b0..LLWU_P15 input was not a wakeup source 5559 * 0b1..LLWU_P15 input was a wakeup source 5560 */ 5561 #define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK) 5562 /*! @} */ 5563 5564 /*! @name F3 - LLWU Flag 3 register */ 5565 /*! @{ */ 5566 5567 #define LLWU_F3_MWUF0_MASK (0x1U) 5568 #define LLWU_F3_MWUF0_SHIFT (0U) 5569 /*! MWUF0 - Wakeup flag For module 0 5570 * 0b0..Module 0 input was not a wakeup source 5571 * 0b1..Module 0 input was a wakeup source 5572 */ 5573 #define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK) 5574 5575 #define LLWU_F3_MWUF1_MASK (0x2U) 5576 #define LLWU_F3_MWUF1_SHIFT (1U) 5577 /*! MWUF1 - Wakeup flag For module 1 5578 * 0b0..Module 1 input was not a wakeup source 5579 * 0b1..Module 1 input was a wakeup source 5580 */ 5581 #define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK) 5582 5583 #define LLWU_F3_MWUF2_MASK (0x4U) 5584 #define LLWU_F3_MWUF2_SHIFT (2U) 5585 /*! MWUF2 - Wakeup flag For module 2 5586 * 0b0..Module 2 input was not a wakeup source 5587 * 0b1..Module 2 input was a wakeup source 5588 */ 5589 #define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK) 5590 5591 #define LLWU_F3_MWUF3_MASK (0x8U) 5592 #define LLWU_F3_MWUF3_SHIFT (3U) 5593 /*! MWUF3 - Wakeup flag For module 3 5594 * 0b0..Module 3 input was not a wakeup source 5595 * 0b1..Module 3 input was a wakeup source 5596 */ 5597 #define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK) 5598 5599 #define LLWU_F3_MWUF4_MASK (0x10U) 5600 #define LLWU_F3_MWUF4_SHIFT (4U) 5601 /*! MWUF4 - Wakeup flag For module 4 5602 * 0b0..Module 4 input was not a wakeup source 5603 * 0b1..Module 4 input was a wakeup source 5604 */ 5605 #define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK) 5606 5607 #define LLWU_F3_MWUF5_MASK (0x20U) 5608 #define LLWU_F3_MWUF5_SHIFT (5U) 5609 /*! MWUF5 - Wakeup flag For module 5 5610 * 0b0..Module 5 input was not a wakeup source 5611 * 0b1..Module 5 input was a wakeup source 5612 */ 5613 #define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK) 5614 5615 #define LLWU_F3_MWUF6_MASK (0x40U) 5616 #define LLWU_F3_MWUF6_SHIFT (6U) 5617 /*! MWUF6 - Wakeup flag For module 6 5618 * 0b0..Module 6 input was not a wakeup source 5619 * 0b1..Module 6 input was a wakeup source 5620 */ 5621 #define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK) 5622 5623 #define LLWU_F3_MWUF7_MASK (0x80U) 5624 #define LLWU_F3_MWUF7_SHIFT (7U) 5625 /*! MWUF7 - Wakeup flag For module 7 5626 * 0b0..Module 7 input was not a wakeup source 5627 * 0b1..Module 7 input was a wakeup source 5628 */ 5629 #define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK) 5630 /*! @} */ 5631 5632 /*! @name FILT1 - LLWU Pin Filter 1 register */ 5633 /*! @{ */ 5634 5635 #define LLWU_FILT1_FILTSEL_MASK (0xFU) 5636 #define LLWU_FILT1_FILTSEL_SHIFT (0U) 5637 /*! FILTSEL - Filter Pin Select 5638 * 0b0000..Select LLWU_P0 for filter 5639 * 0b1111..Select LLWU_P15 for filter 5640 */ 5641 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK) 5642 5643 #define LLWU_FILT1_FILTE_MASK (0x60U) 5644 #define LLWU_FILT1_FILTE_SHIFT (5U) 5645 /*! FILTE - Digital Filter On External Pin 5646 * 0b00..Filter disabled 5647 * 0b01..Filter posedge detect enabled 5648 * 0b10..Filter negedge detect enabled 5649 * 0b11..Filter any edge detect enabled 5650 */ 5651 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK) 5652 5653 #define LLWU_FILT1_FILTF_MASK (0x80U) 5654 #define LLWU_FILT1_FILTF_SHIFT (7U) 5655 /*! FILTF - Filter Detect Flag 5656 * 0b0..Pin Filter 1 was not a wakeup source 5657 * 0b1..Pin Filter 1 was a wakeup source 5658 */ 5659 #define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK) 5660 /*! @} */ 5661 5662 /*! @name FILT2 - LLWU Pin Filter 2 register */ 5663 /*! @{ */ 5664 5665 #define LLWU_FILT2_FILTSEL_MASK (0xFU) 5666 #define LLWU_FILT2_FILTSEL_SHIFT (0U) 5667 /*! FILTSEL - Filter Pin Select 5668 * 0b0000..Select LLWU_P0 for filter 5669 * 0b1111..Select LLWU_P15 for filter 5670 */ 5671 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK) 5672 5673 #define LLWU_FILT2_FILTE_MASK (0x60U) 5674 #define LLWU_FILT2_FILTE_SHIFT (5U) 5675 /*! FILTE - Digital Filter On External Pin 5676 * 0b00..Filter disabled 5677 * 0b01..Filter posedge detect enabled 5678 * 0b10..Filter negedge detect enabled 5679 * 0b11..Filter any edge detect enabled 5680 */ 5681 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK) 5682 5683 #define LLWU_FILT2_FILTF_MASK (0x80U) 5684 #define LLWU_FILT2_FILTF_SHIFT (7U) 5685 /*! FILTF - Filter Detect Flag 5686 * 0b0..Pin Filter 2 was not a wakeup source 5687 * 0b1..Pin Filter 2 was a wakeup source 5688 */ 5689 #define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK) 5690 /*! @} */ 5691 5692 5693 /*! 5694 * @} 5695 */ /* end of group LLWU_Register_Masks */ 5696 5697 5698 /* LLWU - Peripheral instance base addresses */ 5699 /** Peripheral LLWU base address */ 5700 #define LLWU_BASE (0x4007C000u) 5701 /** Peripheral LLWU base pointer */ 5702 #define LLWU ((LLWU_Type *)LLWU_BASE) 5703 /** Array initializer of LLWU peripheral base addresses */ 5704 #define LLWU_BASE_ADDRS { LLWU_BASE } 5705 /** Array initializer of LLWU peripheral base pointers */ 5706 #define LLWU_BASE_PTRS { LLWU } 5707 /** Interrupt vectors for the LLWU peripheral type */ 5708 #define LLWU_IRQS { LLWU_IRQn } 5709 5710 /*! 5711 * @} 5712 */ /* end of group LLWU_Peripheral_Access_Layer */ 5713 5714 5715 /* ---------------------------------------------------------------------------- 5716 -- LPTMR Peripheral Access Layer 5717 ---------------------------------------------------------------------------- */ 5718 5719 /*! 5720 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer 5721 * @{ 5722 */ 5723 5724 /** LPTMR - Register Layout Typedef */ 5725 typedef struct { 5726 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */ 5727 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */ 5728 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */ 5729 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */ 5730 } LPTMR_Type; 5731 5732 /* ---------------------------------------------------------------------------- 5733 -- LPTMR Register Masks 5734 ---------------------------------------------------------------------------- */ 5735 5736 /*! 5737 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks 5738 * @{ 5739 */ 5740 5741 /*! @name CSR - Low Power Timer Control Status Register */ 5742 /*! @{ */ 5743 5744 #define LPTMR_CSR_TEN_MASK (0x1U) 5745 #define LPTMR_CSR_TEN_SHIFT (0U) 5746 /*! TEN - Timer Enable 5747 * 0b0..LPTMR is disabled and internal logic is reset. 5748 * 0b1..LPTMR is enabled. 5749 */ 5750 #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) 5751 5752 #define LPTMR_CSR_TMS_MASK (0x2U) 5753 #define LPTMR_CSR_TMS_SHIFT (1U) 5754 /*! TMS - Timer Mode Select 5755 * 0b0..Time Counter mode. 5756 * 0b1..Pulse Counter mode. 5757 */ 5758 #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) 5759 5760 #define LPTMR_CSR_TFC_MASK (0x4U) 5761 #define LPTMR_CSR_TFC_SHIFT (2U) 5762 /*! TFC - Timer Free-Running Counter 5763 * 0b0..CNR is reset whenever TCF is set. 5764 * 0b1..CNR is reset on overflow. 5765 */ 5766 #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) 5767 5768 #define LPTMR_CSR_TPP_MASK (0x8U) 5769 #define LPTMR_CSR_TPP_SHIFT (3U) 5770 /*! TPP - Timer Pin Polarity 5771 * 0b0..Pulse Counter input source is active-high, and the CNR will increment on the rising-edge. 5772 * 0b1..Pulse Counter input source is active-low, and the CNR will increment on the falling-edge. 5773 */ 5774 #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) 5775 5776 #define LPTMR_CSR_TPS_MASK (0x30U) 5777 #define LPTMR_CSR_TPS_SHIFT (4U) 5778 /*! TPS - Timer Pin Select 5779 * 0b00..Pulse counter input 0 is selected. 5780 * 0b01..Pulse counter input 1 is selected. 5781 * 0b10..Pulse counter input 2 is selected. 5782 * 0b11..Pulse counter input 3 is selected. 5783 */ 5784 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) 5785 5786 #define LPTMR_CSR_TIE_MASK (0x40U) 5787 #define LPTMR_CSR_TIE_SHIFT (6U) 5788 /*! TIE - Timer Interrupt Enable 5789 * 0b0..Timer interrupt disabled. 5790 * 0b1..Timer interrupt enabled. 5791 */ 5792 #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) 5793 5794 #define LPTMR_CSR_TCF_MASK (0x80U) 5795 #define LPTMR_CSR_TCF_SHIFT (7U) 5796 /*! TCF - Timer Compare Flag 5797 * 0b0..The value of CNR is not equal to CMR and increments. 5798 * 0b1..The value of CNR is equal to CMR and increments. 5799 */ 5800 #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) 5801 /*! @} */ 5802 5803 /*! @name PSR - Low Power Timer Prescale Register */ 5804 /*! @{ */ 5805 5806 #define LPTMR_PSR_PCS_MASK (0x3U) 5807 #define LPTMR_PSR_PCS_SHIFT (0U) 5808 /*! PCS - Prescaler Clock Select 5809 * 0b00..Prescaler/glitch filter clock 0 selected. 5810 * 0b01..Prescaler/glitch filter clock 1 selected. 5811 * 0b10..Prescaler/glitch filter clock 2 selected. 5812 * 0b11..Prescaler/glitch filter clock 3 selected. 5813 */ 5814 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) 5815 5816 #define LPTMR_PSR_PBYP_MASK (0x4U) 5817 #define LPTMR_PSR_PBYP_SHIFT (2U) 5818 /*! PBYP - Prescaler Bypass 5819 * 0b0..Prescaler/glitch filter is enabled. 5820 * 0b1..Prescaler/glitch filter is bypassed. 5821 */ 5822 #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) 5823 5824 #define LPTMR_PSR_PRESCALE_MASK (0x78U) 5825 #define LPTMR_PSR_PRESCALE_SHIFT (3U) 5826 /*! PRESCALE - Prescale Value 5827 * 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. 5828 * 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. 5829 * 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. 5830 * 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. 5831 * 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. 5832 * 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. 5833 * 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. 5834 * 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. 5835 * 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. 5836 * 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. 5837 * 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. 5838 * 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. 5839 * 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. 5840 * 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. 5841 * 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. 5842 * 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges. 5843 */ 5844 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) 5845 /*! @} */ 5846 5847 /*! @name CMR - Low Power Timer Compare Register */ 5848 /*! @{ */ 5849 5850 #define LPTMR_CMR_COMPARE_MASK (0xFFFFU) 5851 #define LPTMR_CMR_COMPARE_SHIFT (0U) 5852 /*! COMPARE - Compare Value 5853 */ 5854 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) 5855 /*! @} */ 5856 5857 /*! @name CNR - Low Power Timer Counter Register */ 5858 /*! @{ */ 5859 5860 #define LPTMR_CNR_COUNTER_MASK (0xFFFFU) 5861 #define LPTMR_CNR_COUNTER_SHIFT (0U) 5862 /*! COUNTER - Counter Value 5863 */ 5864 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) 5865 /*! @} */ 5866 5867 5868 /*! 5869 * @} 5870 */ /* end of group LPTMR_Register_Masks */ 5871 5872 5873 /* LPTMR - Peripheral instance base addresses */ 5874 /** Peripheral LPTMR base address */ 5875 #define LPTMR_BASE (0x4003C000u) 5876 /** Peripheral LPTMR base pointer */ 5877 #define LPTMR ((LPTMR_Type *)LPTMR_BASE) 5878 /** Array initializer of LPTMR peripheral base addresses */ 5879 #define LPTMR_BASE_ADDRS { LPTMR_BASE } 5880 /** Array initializer of LPTMR peripheral base pointers */ 5881 #define LPTMR_BASE_PTRS { LPTMR } 5882 /** Interrupt vectors for the LPTMR peripheral type */ 5883 #define LPTMR_IRQS { LPTMR_IRQn } 5884 5885 /*! 5886 * @} 5887 */ /* end of group LPTMR_Peripheral_Access_Layer */ 5888 5889 5890 /* ---------------------------------------------------------------------------- 5891 -- MCG Peripheral Access Layer 5892 ---------------------------------------------------------------------------- */ 5893 5894 /*! 5895 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer 5896 * @{ 5897 */ 5898 5899 /** MCG - Register Layout Typedef */ 5900 typedef struct { 5901 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */ 5902 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */ 5903 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */ 5904 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */ 5905 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */ 5906 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */ 5907 __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */ 5908 uint8_t RESERVED_0[1]; 5909 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */ 5910 uint8_t RESERVED_1[1]; 5911 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */ 5912 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */ 5913 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */ 5914 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */ 5915 __I uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */ 5916 } MCG_Type; 5917 5918 /* ---------------------------------------------------------------------------- 5919 -- MCG Register Masks 5920 ---------------------------------------------------------------------------- */ 5921 5922 /*! 5923 * @addtogroup MCG_Register_Masks MCG Register Masks 5924 * @{ 5925 */ 5926 5927 /*! @name C1 - MCG Control 1 Register */ 5928 /*! @{ */ 5929 5930 #define MCG_C1_IREFSTEN_MASK (0x1U) 5931 #define MCG_C1_IREFSTEN_SHIFT (0U) 5932 /*! IREFSTEN - Internal Reference Stop Enable 5933 * 0b0..Internal reference clock is disabled in Stop mode. 5934 * 0b1..Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode. 5935 */ 5936 #define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK) 5937 5938 #define MCG_C1_IRCLKEN_MASK (0x2U) 5939 #define MCG_C1_IRCLKEN_SHIFT (1U) 5940 /*! IRCLKEN - Internal Reference Clock Enable 5941 * 0b0..MCGIRCLK inactive. 5942 * 0b1..MCGIRCLK active. 5943 */ 5944 #define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK) 5945 5946 #define MCG_C1_IREFS_MASK (0x4U) 5947 #define MCG_C1_IREFS_SHIFT (2U) 5948 /*! IREFS - Internal Reference Select 5949 * 0b0..External reference clock is selected. 5950 * 0b1..The slow internal reference clock is selected. 5951 */ 5952 #define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK) 5953 5954 #define MCG_C1_FRDIV_MASK (0x38U) 5955 #define MCG_C1_FRDIV_SHIFT (3U) 5956 /*! FRDIV - FLL External Reference Divider 5957 * 0b000..If RANGE = 0 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32. 5958 * 0b001..If RANGE = 0 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64. 5959 * 0b010..If RANGE = 0 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128. 5960 * 0b011..If RANGE = 0 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256. 5961 * 0b100..If RANGE = 0 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512. 5962 * 0b101..If RANGE = 0 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024. 5963 * 0b110..If RANGE = 0 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 . 5964 * 0b111..If RANGE = 0 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 . 5965 */ 5966 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK) 5967 5968 #define MCG_C1_CLKS_MASK (0xC0U) 5969 #define MCG_C1_CLKS_SHIFT (6U) 5970 /*! CLKS - Clock Source Select 5971 * 0b00..Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control bit). 5972 * 0b01..Encoding 1 - Internal reference clock is selected. 5973 * 0b10..Encoding 2 - External reference clock is selected. 5974 * 0b11..Encoding 3 - Reserved. 5975 */ 5976 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK) 5977 /*! @} */ 5978 5979 /*! @name C2 - MCG Control 2 Register */ 5980 /*! @{ */ 5981 5982 #define MCG_C2_IRCS_MASK (0x1U) 5983 #define MCG_C2_IRCS_SHIFT (0U) 5984 /*! IRCS - Internal Reference Clock Select 5985 * 0b0..Slow internal reference clock selected. 5986 * 0b1..Fast internal reference clock selected. 5987 */ 5988 #define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK) 5989 5990 #define MCG_C2_LP_MASK (0x2U) 5991 #define MCG_C2_LP_SHIFT (1U) 5992 /*! LP - Low Power Select 5993 * 0b0..FLL or PLL is not disabled in bypass modes. 5994 * 0b1..FLL or PLL is disabled in bypass modes (lower power) 5995 */ 5996 #define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK) 5997 5998 #define MCG_C2_EREFS0_MASK (0x4U) 5999 #define MCG_C2_EREFS0_SHIFT (2U) 6000 /*! EREFS0 - External Reference Select 6001 * 0b0..External reference clock requested. 6002 * 0b1..Oscillator requested. 6003 */ 6004 #define MCG_C2_EREFS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS0_SHIFT)) & MCG_C2_EREFS0_MASK) 6005 6006 #define MCG_C2_HGO0_MASK (0x8U) 6007 #define MCG_C2_HGO0_SHIFT (3U) 6008 /*! HGO0 - High Gain Oscillator Select 6009 * 0b0..Configure crystal oscillator for low-power operation. 6010 * 0b1..Configure crystal oscillator for high-gain operation. 6011 */ 6012 #define MCG_C2_HGO0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO0_SHIFT)) & MCG_C2_HGO0_MASK) 6013 6014 #define MCG_C2_RANGE0_MASK (0x30U) 6015 #define MCG_C2_RANGE0_SHIFT (4U) 6016 /*! RANGE0 - Frequency Range Select 6017 * 0b00..Encoding 0 - Low frequency range selected for the crystal oscillator . 6018 * 0b01..Encoding 1 - High frequency range selected for the crystal oscillator . 6019 * 0b1x..Encoding 2 - Very high frequency range selected for the crystal oscillator . 6020 */ 6021 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE0_SHIFT)) & MCG_C2_RANGE0_MASK) 6022 6023 #define MCG_C2_LOCRE0_MASK (0x80U) 6024 #define MCG_C2_LOCRE0_SHIFT (7U) 6025 /*! LOCRE0 - Loss of Clock Reset Enable 6026 * 0b0..Interrupt request is generated on a loss of OSC external reference clock. 6027 * 0b1..Generate a reset request on a loss of OSC external reference clock. 6028 */ 6029 #define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK) 6030 /*! @} */ 6031 6032 /*! @name C3 - MCG Control 3 Register */ 6033 /*! @{ */ 6034 6035 #define MCG_C3_SCTRIM_MASK (0xFFU) 6036 #define MCG_C3_SCTRIM_SHIFT (0U) 6037 /*! SCTRIM - Slow Internal Reference Clock Trim Setting 6038 */ 6039 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK) 6040 /*! @} */ 6041 6042 /*! @name C4 - MCG Control 4 Register */ 6043 /*! @{ */ 6044 6045 #define MCG_C4_SCFTRIM_MASK (0x1U) 6046 #define MCG_C4_SCFTRIM_SHIFT (0U) 6047 /*! SCFTRIM - Slow Internal Reference Clock Fine Trim 6048 */ 6049 #define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK) 6050 6051 #define MCG_C4_FCTRIM_MASK (0x1EU) 6052 #define MCG_C4_FCTRIM_SHIFT (1U) 6053 /*! FCTRIM - Fast Internal Reference Clock Trim Setting 6054 */ 6055 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK) 6056 6057 #define MCG_C4_DRST_DRS_MASK (0x60U) 6058 #define MCG_C4_DRST_DRS_SHIFT (5U) 6059 /*! DRST_DRS - DCO Range Select 6060 * 0b00..Encoding 0 - Low range (reset default). 6061 * 0b01..Encoding 1 - Mid range. 6062 * 0b10..Encoding 2 - Mid-high range. 6063 * 0b11..Encoding 3 - High range. 6064 */ 6065 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK) 6066 6067 #define MCG_C4_DMX32_MASK (0x80U) 6068 #define MCG_C4_DMX32_SHIFT (7U) 6069 /*! DMX32 - DCO Maximum Frequency with 32.768 kHz Reference 6070 * 0b0..DCO has a default range of 25%. 6071 * 0b1..DCO is fine-tuned for maximum frequency with 32.768 kHz reference. 6072 */ 6073 #define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK) 6074 /*! @} */ 6075 6076 /*! @name C5 - MCG Control 5 Register */ 6077 /*! @{ */ 6078 6079 #define MCG_C5_PLLSTEN0_MASK (0x20U) 6080 #define MCG_C5_PLLSTEN0_SHIFT (5U) 6081 /*! PLLSTEN0 - PLL Stop Enable 6082 * 0b0..MCGPLLCLK is disabled in any of the Stop modes. 6083 * 0b1..MCGPLLCLK is enabled if system is in Normal Stop mode. 6084 */ 6085 #define MCG_C5_PLLSTEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK) 6086 6087 #define MCG_C5_PLLCLKEN0_MASK (0x40U) 6088 #define MCG_C5_PLLCLKEN0_SHIFT (6U) 6089 /*! PLLCLKEN0 - PLL Clock Enable 6090 * 0b0..MCGPLLCLK is inactive. 6091 * 0b1..MCGPLLCLK is active. 6092 */ 6093 #define MCG_C5_PLLCLKEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK) 6094 /*! @} */ 6095 6096 /*! @name C6 - MCG Control 6 Register */ 6097 /*! @{ */ 6098 6099 #define MCG_C6_CHGPMP_BIAS_MASK (0x1FU) 6100 #define MCG_C6_CHGPMP_BIAS_SHIFT (0U) 6101 /*! CHGPMP_BIAS - Directly controls the PLL Charge Pump Current. Appropiate selection of this value 6102 * is imperative to ensure stable operation of the PLL closed loop system. The default value for 6103 * this field is set to 5'b01000 out of reset which generates a nominal 750nA charge pump current 6104 * (lcp). 6105 */ 6106 #define MCG_C6_CHGPMP_BIAS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CHGPMP_BIAS_SHIFT)) & MCG_C6_CHGPMP_BIAS_MASK) 6107 6108 #define MCG_C6_CME0_MASK (0x20U) 6109 #define MCG_C6_CME0_SHIFT (5U) 6110 /*! CME0 - Clock Monitor Enable 6111 * 0b0..External clock monitor is disabled for OSC. 6112 * 0b1..External clock monitor is enabled for OSC. 6113 */ 6114 #define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK) 6115 6116 #define MCG_C6_PLLS_MASK (0x40U) 6117 #define MCG_C6_PLLS_SHIFT (6U) 6118 /*! PLLS - PLL Select 6119 * 0b0..FLL is selected. 6120 * 0b1..PLL is selected (PLL reference clock must be in the range of 31.25-39.0625 KHz prior to setting the PLLS bit). 6121 */ 6122 #define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK) 6123 6124 #define MCG_C6_LOLIE0_MASK (0x80U) 6125 #define MCG_C6_LOLIE0_SHIFT (7U) 6126 /*! LOLIE0 - Loss of Lock Interrrupt Enable 6127 * 0b0..No interrupt request is generated on loss of lock. 6128 * 0b1..Generate an interrupt request on loss of lock. 6129 */ 6130 #define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK) 6131 /*! @} */ 6132 6133 /*! @name S - MCG Status Register */ 6134 /*! @{ */ 6135 6136 #define MCG_S_IRCST_MASK (0x1U) 6137 #define MCG_S_IRCST_SHIFT (0U) 6138 /*! IRCST - Internal Reference Clock Status 6139 * 0b0..Source of internal reference clock is the slow clock (32 kHz IRC). 6140 * 0b1..Source of internal reference clock is the fast clock (4 MHz IRC). 6141 */ 6142 #define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK) 6143 6144 #define MCG_S_OSCINIT0_MASK (0x2U) 6145 #define MCG_S_OSCINIT0_SHIFT (1U) 6146 /*! OSCINIT0 - OSC Initialization 6147 */ 6148 #define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK) 6149 6150 #define MCG_S_CLKST_MASK (0xCU) 6151 #define MCG_S_CLKST_SHIFT (2U) 6152 /*! CLKST - Clock Mode Status 6153 * 0b00..Encoding 0 - Output of the FLL is selected (reset default). 6154 * 0b01..Encoding 1 - Internal reference clock is selected. 6155 * 0b10..Encoding 2 - External reference clock is selected. 6156 * 0b11..Encoding 3 - Output of the PLL is selected . 6157 */ 6158 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK) 6159 6160 #define MCG_S_IREFST_MASK (0x10U) 6161 #define MCG_S_IREFST_SHIFT (4U) 6162 /*! IREFST - Internal Reference Status 6163 * 0b0..Source of FLL reference clock is the external reference clock. 6164 * 0b1..Source of FLL reference clock is the internal reference clock. 6165 */ 6166 #define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK) 6167 6168 #define MCG_S_PLLST_MASK (0x20U) 6169 #define MCG_S_PLLST_SHIFT (5U) 6170 /*! PLLST - PLL Select Status 6171 * 0b0..Source of PLLS clock is FLL clock. 6172 * 0b1..Source of PLLS clock is PLL output clock. 6173 */ 6174 #define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK) 6175 6176 #define MCG_S_LOCK0_MASK (0x40U) 6177 #define MCG_S_LOCK0_SHIFT (6U) 6178 /*! LOCK0 - Lock Status 6179 * 0b0..PLL is currently unlocked. 6180 * 0b1..PLL is currently locked. 6181 */ 6182 #define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK) 6183 6184 #define MCG_S_LOLS0_MASK (0x80U) 6185 #define MCG_S_LOLS0_SHIFT (7U) 6186 /*! LOLS0 - Loss of Lock Status 6187 * 0b0..PLL has not lost lock since LOLS 0 was last cleared. 6188 * 0b1..PLL has lost lock since LOLS 0 was last cleared. 6189 */ 6190 #define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK) 6191 /*! @} */ 6192 6193 /*! @name SC - MCG Status and Control Register */ 6194 /*! @{ */ 6195 6196 #define MCG_SC_LOCS0_MASK (0x1U) 6197 #define MCG_SC_LOCS0_SHIFT (0U) 6198 /*! LOCS0 - OSC Loss of Clock Status 6199 * 0b0..Loss of OSC has not occurred. 6200 * 0b1..Loss of OSC has occurred. 6201 */ 6202 #define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK) 6203 6204 #define MCG_SC_FCRDIV_MASK (0xEU) 6205 #define MCG_SC_FCRDIV_SHIFT (1U) 6206 /*! FCRDIV - Fast Clock Internal Reference Divider 6207 * 0b000..Divide Factor is 1 6208 * 0b001..Divide Factor is 2. 6209 * 0b010..Divide Factor is 4. 6210 * 0b011..Divide Factor is 8. 6211 * 0b100..Divide Factor is 16 6212 * 0b101..Divide Factor is 32 6213 * 0b110..Divide Factor is 64 6214 * 0b111..Divide Factor is 128. 6215 */ 6216 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK) 6217 6218 #define MCG_SC_FLTPRSRV_MASK (0x10U) 6219 #define MCG_SC_FLTPRSRV_SHIFT (4U) 6220 /*! FLTPRSRV - FLL Filter Preserve Enable 6221 * 0b0..FLL filter and FLL frequency will reset on changes to currect clock mode. 6222 * 0b1..Fll filter and FLL frequency retain their previous values during new clock mode change. 6223 */ 6224 #define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK) 6225 6226 #define MCG_SC_ATMF_MASK (0x20U) 6227 #define MCG_SC_ATMF_SHIFT (5U) 6228 /*! ATMF - Automatic Trim Machine Fail Flag 6229 * 0b0..Automatic Trim Machine completed normally. 6230 * 0b1..Automatic Trim Machine failed. 6231 */ 6232 #define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK) 6233 6234 #define MCG_SC_ATMS_MASK (0x40U) 6235 #define MCG_SC_ATMS_SHIFT (6U) 6236 /*! ATMS - Automatic Trim Machine Select 6237 * 0b0..32 kHz Internal Reference Clock selected. 6238 * 0b1..4 MHz Internal Reference Clock selected. 6239 */ 6240 #define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK) 6241 6242 #define MCG_SC_ATME_MASK (0x80U) 6243 #define MCG_SC_ATME_SHIFT (7U) 6244 /*! ATME - Automatic Trim Machine Enable 6245 * 0b0..Auto Trim Machine disabled. 6246 * 0b1..Auto Trim Machine enabled. 6247 */ 6248 #define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK) 6249 /*! @} */ 6250 6251 /*! @name ATCVH - MCG Auto Trim Compare Value High Register */ 6252 /*! @{ */ 6253 6254 #define MCG_ATCVH_ATCVH_MASK (0xFFU) 6255 #define MCG_ATCVH_ATCVH_SHIFT (0U) 6256 /*! ATCVH - ATM Compare Value High 6257 */ 6258 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK) 6259 /*! @} */ 6260 6261 /*! @name ATCVL - MCG Auto Trim Compare Value Low Register */ 6262 /*! @{ */ 6263 6264 #define MCG_ATCVL_ATCVL_MASK (0xFFU) 6265 #define MCG_ATCVL_ATCVL_SHIFT (0U) 6266 /*! ATCVL - ATM Compare Value Low 6267 */ 6268 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK) 6269 /*! @} */ 6270 6271 /*! @name C7 - MCG Control 7 Register */ 6272 /*! @{ */ 6273 6274 #define MCG_C7_OSCSEL_MASK (0x1U) 6275 #define MCG_C7_OSCSEL_SHIFT (0U) 6276 /*! OSCSEL - MCG OSC Clock Select 6277 * 0b0..Selects Oscillator (OSCCLK). 6278 * 0b1..Selects 32 kHz RTC Oscillator. 6279 */ 6280 #define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK) 6281 6282 #define MCG_C7_PLL32KREFSEL_MASK (0xC0U) 6283 #define MCG_C7_PLL32KREFSEL_SHIFT (6U) 6284 /*! PLL32KREFSEL - MCG PLL 32Khz Reference Clock Select 6285 * 0b00..Selects 32 kHz RTC Oscillator. 6286 * 0b01..Selects 32 kHz IRC. 6287 * 0b10..Selects FLL FRDIV clock. 6288 * 0b11..Reserved. 6289 */ 6290 #define MCG_C7_PLL32KREFSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_PLL32KREFSEL_SHIFT)) & MCG_C7_PLL32KREFSEL_MASK) 6291 /*! @} */ 6292 6293 /*! @name C8 - MCG Control 8 Register */ 6294 /*! @{ */ 6295 6296 #define MCG_C8_LOCS1_MASK (0x1U) 6297 #define MCG_C8_LOCS1_SHIFT (0U) 6298 /*! LOCS1 - RTC Loss of Clock Status 6299 * 0b0..Loss of RTC has not occur. 6300 * 0b1..Loss of RTC has occur 6301 */ 6302 #define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK) 6303 6304 #define MCG_C8_COARSE_LOLIE_MASK (0x10U) 6305 #define MCG_C8_COARSE_LOLIE_SHIFT (4U) 6306 /*! COARSE_LOLIE - Loss of Coarse Lock Interrrupt Enable 6307 * 0b0..No interrupt request is generated on coarse loss of lock. 6308 * 0b1..Generate an interrupt request on coarse loss of lock. 6309 */ 6310 #define MCG_C8_COARSE_LOLIE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_COARSE_LOLIE_SHIFT)) & MCG_C8_COARSE_LOLIE_MASK) 6311 6312 #define MCG_C8_CME1_MASK (0x20U) 6313 #define MCG_C8_CME1_SHIFT (5U) 6314 /*! CME1 - Clock Monitor Enable1 6315 * 0b0..External clock monitor is disabled for RTC clock. 6316 * 0b1..External clock monitor is enabled for RTC clock. 6317 */ 6318 #define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK) 6319 6320 #define MCG_C8_LOLRE_MASK (0x40U) 6321 #define MCG_C8_LOLRE_SHIFT (6U) 6322 /*! LOLRE - PLL Loss of Lock Reset Enable 6323 * 0b0..Interrupt request is generated on a PLL loss of lock indication. The PLL loss of lock interrupt enable 6324 * bit must also be set to generate the interrupt request. 6325 * 0b1..Generate a reset request on a PLL loss of lock indication. 6326 */ 6327 #define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK) 6328 6329 #define MCG_C8_LOCRE1_MASK (0x80U) 6330 #define MCG_C8_LOCRE1_SHIFT (7U) 6331 /*! LOCRE1 - Loss of Clock Reset Enable 6332 * 0b0..Interrupt request is generated on a loss of RTC external reference clock. 6333 * 0b1..Generate a reset request on a loss of RTC external reference clock 6334 */ 6335 #define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK) 6336 /*! @} */ 6337 6338 /*! @name C9 - MCG Control 9 Register */ 6339 /*! @{ */ 6340 6341 #define MCG_C9_COARSE_LOCK_MASK (0x40U) 6342 #define MCG_C9_COARSE_LOCK_SHIFT (6U) 6343 /*! COARSE_LOCK - Coarse Lock Status 6344 * 0b0..PLL is currently unlocked. 6345 * 0b1..PLL is currently locked after first sample. 6346 */ 6347 #define MCG_C9_COARSE_LOCK(x) (((uint8_t)(((uint8_t)(x)) << MCG_C9_COARSE_LOCK_SHIFT)) & MCG_C9_COARSE_LOCK_MASK) 6348 6349 #define MCG_C9_COARSE_LOLS_MASK (0x80U) 6350 #define MCG_C9_COARSE_LOLS_SHIFT (7U) 6351 /*! COARSE_LOLS - Coarse Loss of Lock Status 6352 * 0b0..PLL has not lost lock since COARSE_LOLS was last cleared. 6353 * 0b1..PLL has lost lock since COARSE_LOLS was last cleared. 6354 */ 6355 #define MCG_C9_COARSE_LOLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C9_COARSE_LOLS_SHIFT)) & MCG_C9_COARSE_LOLS_MASK) 6356 /*! @} */ 6357 6358 6359 /*! 6360 * @} 6361 */ /* end of group MCG_Register_Masks */ 6362 6363 6364 /* MCG - Peripheral instance base addresses */ 6365 /** Peripheral MCG base address */ 6366 #define MCG_BASE (0x40064000u) 6367 /** Peripheral MCG base pointer */ 6368 #define MCG ((MCG_Type *)MCG_BASE) 6369 /** Array initializer of MCG peripheral base addresses */ 6370 #define MCG_BASE_ADDRS { MCG_BASE } 6371 /** Array initializer of MCG peripheral base pointers */ 6372 #define MCG_BASE_PTRS { MCG } 6373 /** Interrupt vectors for the MCG peripheral type */ 6374 #define MCG_IRQS { MCG_IRQn } 6375 /* MCG C2[EREFS] backward compatibility */ 6376 #define MCG_C2_EREFS_MASK (MCG_C2_EREFS0_MASK) 6377 #define MCG_C2_EREFS_SHIFT (MCG_C2_EREFS0_SHIFT) 6378 #define MCG_C2_EREFS_WIDTH (MCG_C2_EREFS0_WIDTH) 6379 #define MCG_C2_EREFS(x) (MCG_C2_EREFS0(x)) 6380 6381 /* MCG C2[HGO] backward compatibility */ 6382 #define MCG_C2_HGO_MASK (MCG_C2_HGO0_MASK) 6383 #define MCG_C2_HGO_SHIFT (MCG_C2_HGO0_SHIFT) 6384 #define MCG_C2_HGO_WIDTH (MCG_C2_HGO0_WIDTH) 6385 #define MCG_C2_HGO(x) (MCG_C2_HGO0(x)) 6386 6387 /* MCG C2[RANGE] backward compatibility */ 6388 #define MCG_C2_RANGE_MASK (MCG_C2_RANGE0_MASK) 6389 #define MCG_C2_RANGE_SHIFT (MCG_C2_RANGE0_SHIFT) 6390 #define MCG_C2_RANGE_WIDTH (MCG_C2_RANGE0_WIDTH) 6391 #define MCG_C2_RANGE(x) (MCG_C2_RANGE0(x)) 6392 6393 6394 /*! 6395 * @} 6396 */ /* end of group MCG_Peripheral_Access_Layer */ 6397 6398 6399 /* ---------------------------------------------------------------------------- 6400 -- MCM Peripheral Access Layer 6401 ---------------------------------------------------------------------------- */ 6402 6403 /*! 6404 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer 6405 * @{ 6406 */ 6407 6408 /** MCM - Register Layout Typedef */ 6409 typedef struct { 6410 uint8_t RESERVED_0[8]; 6411 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ 6412 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ 6413 __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */ 6414 uint8_t RESERVED_1[32]; 6415 __IO uint32_t PID; /**< Process ID register, offset: 0x30 */ 6416 uint8_t RESERVED_2[12]; 6417 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */ 6418 uint8_t RESERVED_3[60]; 6419 __IO uint32_t MATCR[1]; /**< Master Attribute Configuration Register, array offset: 0x80, array step: 0x4 */ 6420 } MCM_Type; 6421 6422 /* ---------------------------------------------------------------------------- 6423 -- MCM Register Masks 6424 ---------------------------------------------------------------------------- */ 6425 6426 /*! 6427 * @addtogroup MCM_Register_Masks MCM Register Masks 6428 * @{ 6429 */ 6430 6431 /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */ 6432 /*! @{ */ 6433 6434 #define MCM_PLASC_ASC_MASK (0xFFU) 6435 #define MCM_PLASC_ASC_SHIFT (0U) 6436 /*! ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the 6437 * crossbar switch's slave input port. 6438 * 0b00000000..A bus slave connection to AXBS input port n is absent. 6439 * 0b00000001..A bus slave connection to AXBS input port n is present. 6440 */ 6441 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK) 6442 /*! @} */ 6443 6444 /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */ 6445 /*! @{ */ 6446 6447 #define MCM_PLAMC_AMC_MASK (0xFFU) 6448 #define MCM_PLAMC_AMC_SHIFT (0U) 6449 /*! AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 6450 * 0b00000000..A bus master connection to AXBS input port n is absent 6451 * 0b00000001..A bus master connection to AXBS input port n is present 6452 */ 6453 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK) 6454 /*! @} */ 6455 6456 /*! @name PLACR - Platform Control Register */ 6457 /*! @{ */ 6458 6459 #define MCM_PLACR_ARB_MASK (0x200U) 6460 #define MCM_PLACR_ARB_SHIFT (9U) 6461 /*! ARB - Arbitration select 6462 * 0b0..Fixed-priority arbitration for the crossbar masters 6463 * 0b1..Round-robin arbitration for the crossbar masters 6464 */ 6465 #define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK) 6466 6467 #define MCM_PLACR_CFCC_MASK (0x400U) 6468 #define MCM_PLACR_CFCC_SHIFT (10U) 6469 /*! CFCC - Clear Flash Controller Cache 6470 */ 6471 #define MCM_PLACR_CFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_CFCC_SHIFT)) & MCM_PLACR_CFCC_MASK) 6472 6473 #define MCM_PLACR_DFCDA_MASK (0x800U) 6474 #define MCM_PLACR_DFCDA_SHIFT (11U) 6475 /*! DFCDA - Disable Flash Controller Data Caching 6476 * 0b0..Enable flash controller data caching 6477 * 0b1..Disable flash controller data caching. 6478 */ 6479 #define MCM_PLACR_DFCDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCDA_SHIFT)) & MCM_PLACR_DFCDA_MASK) 6480 6481 #define MCM_PLACR_DFCIC_MASK (0x1000U) 6482 #define MCM_PLACR_DFCIC_SHIFT (12U) 6483 /*! DFCIC - Disable Flash Controller Instruction Caching 6484 * 0b0..Enable flash controller instruction caching. 6485 * 0b1..Disable flash controller instruction caching. 6486 */ 6487 #define MCM_PLACR_DFCIC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCIC_SHIFT)) & MCM_PLACR_DFCIC_MASK) 6488 6489 #define MCM_PLACR_DFCC_MASK (0x2000U) 6490 #define MCM_PLACR_DFCC_SHIFT (13U) 6491 /*! DFCC - Disable Flash Controller Cache 6492 * 0b0..Enable flash controller cache. 6493 * 0b1..Disable flash controller cache. 6494 */ 6495 #define MCM_PLACR_DFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCC_SHIFT)) & MCM_PLACR_DFCC_MASK) 6496 6497 #define MCM_PLACR_EFDS_MASK (0x4000U) 6498 #define MCM_PLACR_EFDS_SHIFT (14U) 6499 /*! EFDS - Enable Flash Data Speculation 6500 * 0b0..Disable flash data speculation. 6501 * 0b1..Enable flash data speculation. 6502 */ 6503 #define MCM_PLACR_EFDS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_EFDS_SHIFT)) & MCM_PLACR_EFDS_MASK) 6504 6505 #define MCM_PLACR_DFCS_MASK (0x8000U) 6506 #define MCM_PLACR_DFCS_SHIFT (15U) 6507 /*! DFCS - Disable Flash Controller Speculation 6508 * 0b0..Enable flash controller speculation. 6509 * 0b1..Disable flash controller speculation. 6510 */ 6511 #define MCM_PLACR_DFCS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCS_SHIFT)) & MCM_PLACR_DFCS_MASK) 6512 6513 #define MCM_PLACR_ESFC_MASK (0x10000U) 6514 #define MCM_PLACR_ESFC_SHIFT (16U) 6515 /*! ESFC - Enable Stalling Flash Controller 6516 * 0b0..Disable stalling flash controller when flash is busy. 6517 * 0b1..Enable stalling flash controller when flash is busy. 6518 */ 6519 #define MCM_PLACR_ESFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ESFC_SHIFT)) & MCM_PLACR_ESFC_MASK) 6520 /*! @} */ 6521 6522 /*! @name PID - Process ID register */ 6523 /*! @{ */ 6524 6525 #define MCM_PID_PID_MASK (0xFFU) 6526 #define MCM_PID_PID_SHIFT (0U) 6527 /*! PID - M0_PID For MPU 6528 * 0b00000000..Reserved for privileged secure tasks 6529 */ 6530 #define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x)) << MCM_PID_PID_SHIFT)) & MCM_PID_PID_MASK) 6531 /*! @} */ 6532 6533 /*! @name CPO - Compute Operation Control Register */ 6534 /*! @{ */ 6535 6536 #define MCM_CPO_CPOREQ_MASK (0x1U) 6537 #define MCM_CPO_CPOREQ_SHIFT (0U) 6538 /*! CPOREQ - Compute Operation Request 6539 * 0b0..Request is cleared. 6540 * 0b1..Request Compute Operation. 6541 */ 6542 #define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK) 6543 6544 #define MCM_CPO_CPOACK_MASK (0x2U) 6545 #define MCM_CPO_CPOACK_SHIFT (1U) 6546 /*! CPOACK - Compute Operation Acknowledge 6547 * 0b0..Compute operation entry has not completed or compute operation exit has completed. 6548 * 0b1..Compute operation entry has completed or compute operation exit has not completed. 6549 */ 6550 #define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK) 6551 6552 #define MCM_CPO_CPOWOI_MASK (0x4U) 6553 #define MCM_CPO_CPOWOI_SHIFT (2U) 6554 /*! CPOWOI - Compute Operation Wake-up on Interrupt 6555 * 0b0..No effect. 6556 * 0b1..When set, the CPOREQ is cleared on any interrupt or exception vector fetch. 6557 */ 6558 #define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK) 6559 /*! @} */ 6560 6561 /*! @name MATCR - Master Attribute Configuration Register */ 6562 /*! @{ */ 6563 6564 #define MCM_MATCR_ATC0_MASK (0x7U) 6565 #define MCM_MATCR_ATC0_SHIFT (0U) 6566 /*! ATC0 - Attribute Configuration Master n 6567 * 0b00x..Master attributes are statically forced to {privileged, secure}. 6568 * 0b010..Master attributes are statically forced to {user, secure}. 6569 * 0b011..Master attributes are statically forced to {user, nonsecure}. 6570 * 0b100..Enable master attribute {privileged or user} and statically force {secure}. 6571 * 0b101..Enable master attribute {privileged or user} and statically force {nonsecure}. 6572 * 0b11x..Enable master attribute {privileged or user, secure or nonsecure} 6573 */ 6574 #define MCM_MATCR_ATC0(x) (((uint32_t)(((uint32_t)(x)) << MCM_MATCR_ATC0_SHIFT)) & MCM_MATCR_ATC0_MASK) 6575 6576 #define MCM_MATCR_RO0_MASK (0x80U) 6577 #define MCM_MATCR_RO0_SHIFT (7U) 6578 /*! RO0 - Read-Only Master n 6579 * 0b0..Writes to the ATCn are allowed. 6580 * 0b1..Writes to the ATCn are ignored. 6581 */ 6582 #define MCM_MATCR_RO0(x) (((uint32_t)(((uint32_t)(x)) << MCM_MATCR_RO0_SHIFT)) & MCM_MATCR_RO0_MASK) 6583 6584 #define MCM_MATCR_ATC2_MASK (0x70000U) 6585 #define MCM_MATCR_ATC2_SHIFT (16U) 6586 /*! ATC2 - Attribute Configuration Master n 6587 * 0b00x..Master attributes are statically forced to {privileged, secure}. 6588 * 0b010..Master attributes are statically forced to {user, secure}. 6589 * 0b011..Master attributes are statically forced to {user, nonsecure}. 6590 * 0b100..Enable master attribute {privileged or user} and statically force {secure}. 6591 * 0b101..Enable master attribute {privileged or user} and statically force {nonsecure}. 6592 * 0b11x..Enable master attribute {privileged or user, secure or nonsecure} 6593 */ 6594 #define MCM_MATCR_ATC2(x) (((uint32_t)(((uint32_t)(x)) << MCM_MATCR_ATC2_SHIFT)) & MCM_MATCR_ATC2_MASK) 6595 6596 #define MCM_MATCR_RO2_MASK (0x800000U) 6597 #define MCM_MATCR_RO2_SHIFT (23U) 6598 /*! RO2 - Read-Only Master n 6599 * 0b0..Writes to the ATCn are allowed. 6600 * 0b1..Writes to the ATCn are ignored. 6601 */ 6602 #define MCM_MATCR_RO2(x) (((uint32_t)(((uint32_t)(x)) << MCM_MATCR_RO2_SHIFT)) & MCM_MATCR_RO2_MASK) 6603 /*! @} */ 6604 6605 /* The count of MCM_MATCR */ 6606 #define MCM_MATCR_COUNT (1U) 6607 6608 6609 /*! 6610 * @} 6611 */ /* end of group MCM_Register_Masks */ 6612 6613 6614 /* MCM - Peripheral instance base addresses */ 6615 /** Peripheral MCM base address */ 6616 #define MCM_BASE (0xF0003000u) 6617 /** Peripheral MCM base pointer */ 6618 #define MCM ((MCM_Type *)MCM_BASE) 6619 /** Array initializer of MCM peripheral base addresses */ 6620 #define MCM_BASE_ADDRS { MCM_BASE } 6621 /** Array initializer of MCM peripheral base pointers */ 6622 #define MCM_BASE_PTRS { MCM } 6623 6624 /*! 6625 * @} 6626 */ /* end of group MCM_Peripheral_Access_Layer */ 6627 6628 6629 /* ---------------------------------------------------------------------------- 6630 -- MTB Peripheral Access Layer 6631 ---------------------------------------------------------------------------- */ 6632 6633 /*! 6634 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer 6635 * @{ 6636 */ 6637 6638 /** MTB - Register Layout Typedef */ 6639 typedef struct { 6640 __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */ 6641 __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */ 6642 __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */ 6643 __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */ 6644 uint8_t RESERVED_0[3824]; 6645 __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */ 6646 uint8_t RESERVED_1[156]; 6647 __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */ 6648 __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */ 6649 uint8_t RESERVED_2[8]; 6650 __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */ 6651 __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */ 6652 __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */ 6653 __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */ 6654 uint8_t RESERVED_3[8]; 6655 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ 6656 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ 6657 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ 6658 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ 6659 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ 6660 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ 6661 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ 6662 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ 6663 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ 6664 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ 6665 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ 6666 } MTB_Type; 6667 6668 /* ---------------------------------------------------------------------------- 6669 -- MTB Register Masks 6670 ---------------------------------------------------------------------------- */ 6671 6672 /*! 6673 * @addtogroup MTB_Register_Masks MTB Register Masks 6674 * @{ 6675 */ 6676 6677 /*! @name POSITION - MTB Position Register */ 6678 /*! @{ */ 6679 6680 #define MTB_POSITION_WRAP_MASK (0x4U) 6681 #define MTB_POSITION_WRAP_SHIFT (2U) 6682 /*! WRAP - WRAP 6683 */ 6684 #define MTB_POSITION_WRAP(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_WRAP_SHIFT)) & MTB_POSITION_WRAP_MASK) 6685 6686 #define MTB_POSITION_POINTER_MASK (0xFFFFFFF8U) 6687 #define MTB_POSITION_POINTER_SHIFT (3U) 6688 /*! POINTER - Trace Packet Address Pointer[28:0] 6689 */ 6690 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_POINTER_SHIFT)) & MTB_POSITION_POINTER_MASK) 6691 /*! @} */ 6692 6693 /*! @name MASTER - MTB Master Register */ 6694 /*! @{ */ 6695 6696 #define MTB_MASTER_MASK_MASK (0x1FU) 6697 #define MTB_MASTER_MASK_SHIFT (0U) 6698 /*! MASK - Mask 6699 */ 6700 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_MASK_SHIFT)) & MTB_MASTER_MASK_MASK) 6701 6702 #define MTB_MASTER_TSTARTEN_MASK (0x20U) 6703 #define MTB_MASTER_TSTARTEN_SHIFT (5U) 6704 /*! TSTARTEN - Trace Start Input Enable 6705 */ 6706 #define MTB_MASTER_TSTARTEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTARTEN_SHIFT)) & MTB_MASTER_TSTARTEN_MASK) 6707 6708 #define MTB_MASTER_TSTOPEN_MASK (0x40U) 6709 #define MTB_MASTER_TSTOPEN_SHIFT (6U) 6710 /*! TSTOPEN - Trace Stop Input Enable 6711 */ 6712 #define MTB_MASTER_TSTOPEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTOPEN_SHIFT)) & MTB_MASTER_TSTOPEN_MASK) 6713 6714 #define MTB_MASTER_SFRWPRIV_MASK (0x80U) 6715 #define MTB_MASTER_SFRWPRIV_SHIFT (7U) 6716 /*! SFRWPRIV - Special Function Register Write Privilege 6717 */ 6718 #define MTB_MASTER_SFRWPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_SFRWPRIV_SHIFT)) & MTB_MASTER_SFRWPRIV_MASK) 6719 6720 #define MTB_MASTER_RAMPRIV_MASK (0x100U) 6721 #define MTB_MASTER_RAMPRIV_SHIFT (8U) 6722 /*! RAMPRIV - RAM Privilege 6723 */ 6724 #define MTB_MASTER_RAMPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_RAMPRIV_SHIFT)) & MTB_MASTER_RAMPRIV_MASK) 6725 6726 #define MTB_MASTER_HALTREQ_MASK (0x200U) 6727 #define MTB_MASTER_HALTREQ_SHIFT (9U) 6728 /*! HALTREQ - Halt Request 6729 */ 6730 #define MTB_MASTER_HALTREQ(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_HALTREQ_SHIFT)) & MTB_MASTER_HALTREQ_MASK) 6731 6732 #define MTB_MASTER_EN_MASK (0x80000000U) 6733 #define MTB_MASTER_EN_SHIFT (31U) 6734 /*! EN - Main Trace Enable 6735 */ 6736 #define MTB_MASTER_EN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_EN_SHIFT)) & MTB_MASTER_EN_MASK) 6737 /*! @} */ 6738 6739 /*! @name FLOW - MTB Flow Register */ 6740 /*! @{ */ 6741 6742 #define MTB_FLOW_AUTOSTOP_MASK (0x1U) 6743 #define MTB_FLOW_AUTOSTOP_SHIFT (0U) 6744 /*! AUTOSTOP - AUTOSTOP 6745 */ 6746 #define MTB_FLOW_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOSTOP_SHIFT)) & MTB_FLOW_AUTOSTOP_MASK) 6747 6748 #define MTB_FLOW_AUTOHALT_MASK (0x2U) 6749 #define MTB_FLOW_AUTOHALT_SHIFT (1U) 6750 /*! AUTOHALT - AUTOHALT 6751 */ 6752 #define MTB_FLOW_AUTOHALT(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOHALT_SHIFT)) & MTB_FLOW_AUTOHALT_MASK) 6753 6754 #define MTB_FLOW_WATERMARK_MASK (0xFFFFFFF8U) 6755 #define MTB_FLOW_WATERMARK_SHIFT (3U) 6756 /*! WATERMARK - WATERMARK[28:0] 6757 */ 6758 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_WATERMARK_SHIFT)) & MTB_FLOW_WATERMARK_MASK) 6759 /*! @} */ 6760 6761 /*! @name BASE - MTB Base Register */ 6762 /*! @{ */ 6763 6764 #define MTB_BASE_BASEADDR_MASK (0xFFFFFFFFU) 6765 #define MTB_BASE_BASEADDR_SHIFT (0U) 6766 /*! BASEADDR - BASEADDR 6767 */ 6768 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x)) << MTB_BASE_BASEADDR_SHIFT)) & MTB_BASE_BASEADDR_MASK) 6769 /*! @} */ 6770 6771 /*! @name MODECTRL - Integration Mode Control Register */ 6772 /*! @{ */ 6773 6774 #define MTB_MODECTRL_MODECTRL_MASK (0xFFFFFFFFU) 6775 #define MTB_MODECTRL_MODECTRL_SHIFT (0U) 6776 /*! MODECTRL - MODECTRL 6777 */ 6778 #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x)) << MTB_MODECTRL_MODECTRL_SHIFT)) & MTB_MODECTRL_MODECTRL_MASK) 6779 /*! @} */ 6780 6781 /*! @name TAGSET - Claim TAG Set Register */ 6782 /*! @{ */ 6783 6784 #define MTB_TAGSET_TAGSET_MASK (0xFFFFFFFFU) 6785 #define MTB_TAGSET_TAGSET_SHIFT (0U) 6786 /*! TAGSET - TAGSET 6787 */ 6788 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGSET_TAGSET_SHIFT)) & MTB_TAGSET_TAGSET_MASK) 6789 /*! @} */ 6790 6791 /*! @name TAGCLEAR - Claim TAG Clear Register */ 6792 /*! @{ */ 6793 6794 #define MTB_TAGCLEAR_TAGCLEAR_MASK (0xFFFFFFFFU) 6795 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT (0U) 6796 /*! TAGCLEAR - TAGCLEAR 6797 */ 6798 #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGCLEAR_TAGCLEAR_SHIFT)) & MTB_TAGCLEAR_TAGCLEAR_MASK) 6799 /*! @} */ 6800 6801 /*! @name LOCKACCESS - Lock Access Register */ 6802 /*! @{ */ 6803 6804 #define MTB_LOCKACCESS_LOCKACCESS_MASK (0xFFFFFFFFU) 6805 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT (0U) 6806 #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKACCESS_LOCKACCESS_SHIFT)) & MTB_LOCKACCESS_LOCKACCESS_MASK) 6807 /*! @} */ 6808 6809 /*! @name LOCKSTAT - Lock Status Register */ 6810 /*! @{ */ 6811 6812 #define MTB_LOCKSTAT_LOCKSTAT_MASK (0xFFFFFFFFU) 6813 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT (0U) 6814 /*! LOCKSTAT - LOCKSTAT 6815 */ 6816 #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKSTAT_LOCKSTAT_SHIFT)) & MTB_LOCKSTAT_LOCKSTAT_MASK) 6817 /*! @} */ 6818 6819 /*! @name AUTHSTAT - Authentication Status Register */ 6820 /*! @{ */ 6821 6822 #define MTB_AUTHSTAT_BIT0_MASK (0x1U) 6823 #define MTB_AUTHSTAT_BIT0_SHIFT (0U) 6824 #define MTB_AUTHSTAT_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT0_SHIFT)) & MTB_AUTHSTAT_BIT0_MASK) 6825 6826 #define MTB_AUTHSTAT_BIT2_MASK (0x4U) 6827 #define MTB_AUTHSTAT_BIT2_SHIFT (2U) 6828 /*! BIT2 - BIT2 6829 */ 6830 #define MTB_AUTHSTAT_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT2_SHIFT)) & MTB_AUTHSTAT_BIT2_MASK) 6831 /*! @} */ 6832 6833 /*! @name DEVICEARCH - Device Architecture Register */ 6834 /*! @{ */ 6835 6836 #define MTB_DEVICEARCH_DEVICEARCH_MASK (0xFFFFFFFFU) 6837 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT (0U) 6838 /*! DEVICEARCH - DEVICEARCH 6839 */ 6840 #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICEARCH_DEVICEARCH_SHIFT)) & MTB_DEVICEARCH_DEVICEARCH_MASK) 6841 /*! @} */ 6842 6843 /*! @name DEVICECFG - Device Configuration Register */ 6844 /*! @{ */ 6845 6846 #define MTB_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU) 6847 #define MTB_DEVICECFG_DEVICECFG_SHIFT (0U) 6848 /*! DEVICECFG - DEVICECFG 6849 */ 6850 #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICECFG_DEVICECFG_SHIFT)) & MTB_DEVICECFG_DEVICECFG_MASK) 6851 /*! @} */ 6852 6853 /*! @name DEVICETYPID - Device Type Identifier Register */ 6854 /*! @{ */ 6855 6856 #define MTB_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU) 6857 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT (0U) 6858 /*! DEVICETYPID - DEVICETYPID 6859 */ 6860 #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICETYPID_DEVICETYPID_SHIFT)) & MTB_DEVICETYPID_DEVICETYPID_MASK) 6861 /*! @} */ 6862 6863 /*! @name PERIPHID4 - Peripheral ID Register */ 6864 /*! @{ */ 6865 6866 #define MTB_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) 6867 #define MTB_PERIPHID4_PERIPHID_SHIFT (0U) 6868 /*! PERIPHID - PERIPHID 6869 */ 6870 #define MTB_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID4_PERIPHID_SHIFT)) & MTB_PERIPHID4_PERIPHID_MASK) 6871 /*! @} */ 6872 6873 /*! @name PERIPHID5 - Peripheral ID Register */ 6874 /*! @{ */ 6875 6876 #define MTB_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) 6877 #define MTB_PERIPHID5_PERIPHID_SHIFT (0U) 6878 /*! PERIPHID - PERIPHID 6879 */ 6880 #define MTB_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID5_PERIPHID_SHIFT)) & MTB_PERIPHID5_PERIPHID_MASK) 6881 /*! @} */ 6882 6883 /*! @name PERIPHID6 - Peripheral ID Register */ 6884 /*! @{ */ 6885 6886 #define MTB_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) 6887 #define MTB_PERIPHID6_PERIPHID_SHIFT (0U) 6888 /*! PERIPHID - PERIPHID 6889 */ 6890 #define MTB_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID6_PERIPHID_SHIFT)) & MTB_PERIPHID6_PERIPHID_MASK) 6891 /*! @} */ 6892 6893 /*! @name PERIPHID7 - Peripheral ID Register */ 6894 /*! @{ */ 6895 6896 #define MTB_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) 6897 #define MTB_PERIPHID7_PERIPHID_SHIFT (0U) 6898 /*! PERIPHID - PERIPHID 6899 */ 6900 #define MTB_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID7_PERIPHID_SHIFT)) & MTB_PERIPHID7_PERIPHID_MASK) 6901 /*! @} */ 6902 6903 /*! @name PERIPHID0 - Peripheral ID Register */ 6904 /*! @{ */ 6905 6906 #define MTB_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) 6907 #define MTB_PERIPHID0_PERIPHID_SHIFT (0U) 6908 /*! PERIPHID - PERIPHID 6909 */ 6910 #define MTB_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID0_PERIPHID_SHIFT)) & MTB_PERIPHID0_PERIPHID_MASK) 6911 /*! @} */ 6912 6913 /*! @name PERIPHID1 - Peripheral ID Register */ 6914 /*! @{ */ 6915 6916 #define MTB_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) 6917 #define MTB_PERIPHID1_PERIPHID_SHIFT (0U) 6918 /*! PERIPHID - PERIPHID 6919 */ 6920 #define MTB_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID1_PERIPHID_SHIFT)) & MTB_PERIPHID1_PERIPHID_MASK) 6921 /*! @} */ 6922 6923 /*! @name PERIPHID2 - Peripheral ID Register */ 6924 /*! @{ */ 6925 6926 #define MTB_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) 6927 #define MTB_PERIPHID2_PERIPHID_SHIFT (0U) 6928 /*! PERIPHID - PERIPHID 6929 */ 6930 #define MTB_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID2_PERIPHID_SHIFT)) & MTB_PERIPHID2_PERIPHID_MASK) 6931 /*! @} */ 6932 6933 /*! @name PERIPHID3 - Peripheral ID Register */ 6934 /*! @{ */ 6935 6936 #define MTB_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) 6937 #define MTB_PERIPHID3_PERIPHID_SHIFT (0U) 6938 /*! PERIPHID - PERIPHID 6939 */ 6940 #define MTB_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID3_PERIPHID_SHIFT)) & MTB_PERIPHID3_PERIPHID_MASK) 6941 /*! @} */ 6942 6943 /*! @name COMPID - Component ID Register */ 6944 /*! @{ */ 6945 6946 #define MTB_COMPID_COMPID_MASK (0xFFFFFFFFU) 6947 #define MTB_COMPID_COMPID_SHIFT (0U) 6948 /*! COMPID - Component ID 6949 */ 6950 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_COMPID_COMPID_SHIFT)) & MTB_COMPID_COMPID_MASK) 6951 /*! @} */ 6952 6953 /* The count of MTB_COMPID */ 6954 #define MTB_COMPID_COUNT (4U) 6955 6956 6957 /*! 6958 * @} 6959 */ /* end of group MTB_Register_Masks */ 6960 6961 6962 /* MTB - Peripheral instance base addresses */ 6963 /** Peripheral MTB base address */ 6964 #define MTB_BASE (0xF0000000u) 6965 /** Peripheral MTB base pointer */ 6966 #define MTB ((MTB_Type *)MTB_BASE) 6967 /** Array initializer of MTB peripheral base addresses */ 6968 #define MTB_BASE_ADDRS { MTB_BASE } 6969 /** Array initializer of MTB peripheral base pointers */ 6970 #define MTB_BASE_PTRS { MTB } 6971 6972 /*! 6973 * @} 6974 */ /* end of group MTB_Peripheral_Access_Layer */ 6975 6976 6977 /* ---------------------------------------------------------------------------- 6978 -- MTBDWT Peripheral Access Layer 6979 ---------------------------------------------------------------------------- */ 6980 6981 /*! 6982 * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer 6983 * @{ 6984 */ 6985 6986 /** MTBDWT - Register Layout Typedef */ 6987 typedef struct { 6988 __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */ 6989 uint8_t RESERVED_0[28]; 6990 struct { /* offset: 0x20, array step: 0x10 */ 6991 __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */ 6992 __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */ 6993 __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */ 6994 uint8_t RESERVED_0[4]; 6995 } COMPARATOR[2]; 6996 uint8_t RESERVED_1[448]; 6997 __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */ 6998 uint8_t RESERVED_2[3524]; 6999 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ 7000 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ 7001 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ 7002 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ 7003 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ 7004 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ 7005 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ 7006 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ 7007 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ 7008 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ 7009 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ 7010 } MTBDWT_Type; 7011 7012 /* ---------------------------------------------------------------------------- 7013 -- MTBDWT Register Masks 7014 ---------------------------------------------------------------------------- */ 7015 7016 /*! 7017 * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks 7018 * @{ 7019 */ 7020 7021 /*! @name CTRL - MTB DWT Control Register */ 7022 /*! @{ */ 7023 7024 #define MTBDWT_CTRL_DWTCFGCTRL_MASK (0xFFFFFFFU) 7025 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT (0U) 7026 /*! DWTCFGCTRL - DWT configuration controls 7027 */ 7028 #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_DWTCFGCTRL_SHIFT)) & MTBDWT_CTRL_DWTCFGCTRL_MASK) 7029 7030 #define MTBDWT_CTRL_NUMCMP_MASK (0xF0000000U) 7031 #define MTBDWT_CTRL_NUMCMP_SHIFT (28U) 7032 /*! NUMCMP - Number of comparators 7033 */ 7034 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_NUMCMP_SHIFT)) & MTBDWT_CTRL_NUMCMP_MASK) 7035 /*! @} */ 7036 7037 /*! @name COMP - MTB_DWT Comparator Register */ 7038 /*! @{ */ 7039 7040 #define MTBDWT_COMP_COMP_MASK (0xFFFFFFFFU) 7041 #define MTBDWT_COMP_COMP_SHIFT (0U) 7042 /*! COMP - Reference value for comparison 7043 */ 7044 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMP_COMP_SHIFT)) & MTBDWT_COMP_COMP_MASK) 7045 /*! @} */ 7046 7047 /* The count of MTBDWT_COMP */ 7048 #define MTBDWT_COMP_COUNT (2U) 7049 7050 /*! @name MASK - MTB_DWT Comparator Mask Register */ 7051 /*! @{ */ 7052 7053 #define MTBDWT_MASK_MASK_MASK (0x1FU) 7054 #define MTBDWT_MASK_MASK_SHIFT (0U) 7055 /*! MASK - MASK 7056 */ 7057 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_MASK_MASK_SHIFT)) & MTBDWT_MASK_MASK_MASK) 7058 /*! @} */ 7059 7060 /* The count of MTBDWT_MASK */ 7061 #define MTBDWT_MASK_COUNT (2U) 7062 7063 /*! @name FCT - MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1 */ 7064 /*! @{ */ 7065 7066 #define MTBDWT_FCT_FUNCTION_MASK (0xFU) 7067 #define MTBDWT_FCT_FUNCTION_SHIFT (0U) 7068 /*! FUNCTION - Function 7069 * 0b0000..Disabled. 7070 * 0b0100..Instruction fetch. 7071 * 0b0101..Data operand read. 7072 * 0b0110..Data operand write. 7073 * 0b0111..Data operand (read + write). 7074 */ 7075 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_FUNCTION_SHIFT)) & MTBDWT_FCT_FUNCTION_MASK) 7076 7077 #define MTBDWT_FCT_DATAVMATCH_MASK (0x100U) 7078 #define MTBDWT_FCT_DATAVMATCH_SHIFT (8U) 7079 /*! DATAVMATCH - Data Value Match 7080 * 0b0..Perform address comparison. 7081 * 0b1..Perform data value comparison. 7082 */ 7083 #define MTBDWT_FCT_DATAVMATCH(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVMATCH_SHIFT)) & MTBDWT_FCT_DATAVMATCH_MASK) 7084 7085 #define MTBDWT_FCT_DATAVSIZE_MASK (0xC00U) 7086 #define MTBDWT_FCT_DATAVSIZE_SHIFT (10U) 7087 /*! DATAVSIZE - Data Value Size 7088 * 0b00..Byte. 7089 * 0b01..Halfword. 7090 * 0b10..Word. 7091 * 0b11..Reserved. Any attempts to use this value results in UNPREDICTABLE behavior. 7092 */ 7093 #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVSIZE_SHIFT)) & MTBDWT_FCT_DATAVSIZE_MASK) 7094 7095 #define MTBDWT_FCT_DATAVADDR0_MASK (0xF000U) 7096 #define MTBDWT_FCT_DATAVADDR0_SHIFT (12U) 7097 /*! DATAVADDR0 - Data Value Address 0 7098 */ 7099 #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVADDR0_SHIFT)) & MTBDWT_FCT_DATAVADDR0_MASK) 7100 7101 #define MTBDWT_FCT_MATCHED_MASK (0x1000000U) 7102 #define MTBDWT_FCT_MATCHED_SHIFT (24U) 7103 /*! MATCHED - Comparator match 7104 * 0b0..No match. 7105 * 0b1..Match occurred. 7106 */ 7107 #define MTBDWT_FCT_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_MATCHED_SHIFT)) & MTBDWT_FCT_MATCHED_MASK) 7108 /*! @} */ 7109 7110 /* The count of MTBDWT_FCT */ 7111 #define MTBDWT_FCT_COUNT (2U) 7112 7113 /*! @name TBCTRL - MTB_DWT Trace Buffer Control Register */ 7114 /*! @{ */ 7115 7116 #define MTBDWT_TBCTRL_ACOMP0_MASK (0x1U) 7117 #define MTBDWT_TBCTRL_ACOMP0_SHIFT (0U) 7118 /*! ACOMP0 - Action based on Comparator 0 match 7119 * 0b0..Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED]. 7120 * 0b1..Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED]. 7121 */ 7122 #define MTBDWT_TBCTRL_ACOMP0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP0_SHIFT)) & MTBDWT_TBCTRL_ACOMP0_MASK) 7123 7124 #define MTBDWT_TBCTRL_ACOMP1_MASK (0x2U) 7125 #define MTBDWT_TBCTRL_ACOMP1_SHIFT (1U) 7126 /*! ACOMP1 - Action based on Comparator 1 match 7127 * 0b0..Trigger TSTOP based on the assertion of MTBDWT_FCT1[MATCHED]. 7128 * 0b1..Trigger TSTART based on the assertion of MTBDWT_FCT1[MATCHED]. 7129 */ 7130 #define MTBDWT_TBCTRL_ACOMP1(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP1_SHIFT)) & MTBDWT_TBCTRL_ACOMP1_MASK) 7131 7132 #define MTBDWT_TBCTRL_NUMCOMP_MASK (0xF0000000U) 7133 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT (28U) 7134 /*! NUMCOMP - Number of Comparators 7135 */ 7136 #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_NUMCOMP_SHIFT)) & MTBDWT_TBCTRL_NUMCOMP_MASK) 7137 /*! @} */ 7138 7139 /*! @name DEVICECFG - Device Configuration Register */ 7140 /*! @{ */ 7141 7142 #define MTBDWT_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU) 7143 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT (0U) 7144 /*! DEVICECFG - DEVICECFG 7145 */ 7146 #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICECFG_DEVICECFG_SHIFT)) & MTBDWT_DEVICECFG_DEVICECFG_MASK) 7147 /*! @} */ 7148 7149 /*! @name DEVICETYPID - Device Type Identifier Register */ 7150 /*! @{ */ 7151 7152 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU) 7153 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT (0U) 7154 /*! DEVICETYPID - DEVICETYPID 7155 */ 7156 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT)) & MTBDWT_DEVICETYPID_DEVICETYPID_MASK) 7157 /*! @} */ 7158 7159 /*! @name PERIPHID4 - Peripheral ID Register */ 7160 /*! @{ */ 7161 7162 #define MTBDWT_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) 7163 #define MTBDWT_PERIPHID4_PERIPHID_SHIFT (0U) 7164 /*! PERIPHID - PERIPHID 7165 */ 7166 #define MTBDWT_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID4_PERIPHID_SHIFT)) & MTBDWT_PERIPHID4_PERIPHID_MASK) 7167 /*! @} */ 7168 7169 /*! @name PERIPHID5 - Peripheral ID Register */ 7170 /*! @{ */ 7171 7172 #define MTBDWT_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) 7173 #define MTBDWT_PERIPHID5_PERIPHID_SHIFT (0U) 7174 /*! PERIPHID - PERIPHID 7175 */ 7176 #define MTBDWT_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID5_PERIPHID_SHIFT)) & MTBDWT_PERIPHID5_PERIPHID_MASK) 7177 /*! @} */ 7178 7179 /*! @name PERIPHID6 - Peripheral ID Register */ 7180 /*! @{ */ 7181 7182 #define MTBDWT_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) 7183 #define MTBDWT_PERIPHID6_PERIPHID_SHIFT (0U) 7184 /*! PERIPHID - PERIPHID 7185 */ 7186 #define MTBDWT_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID6_PERIPHID_SHIFT)) & MTBDWT_PERIPHID6_PERIPHID_MASK) 7187 /*! @} */ 7188 7189 /*! @name PERIPHID7 - Peripheral ID Register */ 7190 /*! @{ */ 7191 7192 #define MTBDWT_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) 7193 #define MTBDWT_PERIPHID7_PERIPHID_SHIFT (0U) 7194 /*! PERIPHID - PERIPHID 7195 */ 7196 #define MTBDWT_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID7_PERIPHID_SHIFT)) & MTBDWT_PERIPHID7_PERIPHID_MASK) 7197 /*! @} */ 7198 7199 /*! @name PERIPHID0 - Peripheral ID Register */ 7200 /*! @{ */ 7201 7202 #define MTBDWT_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) 7203 #define MTBDWT_PERIPHID0_PERIPHID_SHIFT (0U) 7204 /*! PERIPHID - PERIPHID 7205 */ 7206 #define MTBDWT_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID0_PERIPHID_SHIFT)) & MTBDWT_PERIPHID0_PERIPHID_MASK) 7207 /*! @} */ 7208 7209 /*! @name PERIPHID1 - Peripheral ID Register */ 7210 /*! @{ */ 7211 7212 #define MTBDWT_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) 7213 #define MTBDWT_PERIPHID1_PERIPHID_SHIFT (0U) 7214 /*! PERIPHID - PERIPHID 7215 */ 7216 #define MTBDWT_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID1_PERIPHID_SHIFT)) & MTBDWT_PERIPHID1_PERIPHID_MASK) 7217 /*! @} */ 7218 7219 /*! @name PERIPHID2 - Peripheral ID Register */ 7220 /*! @{ */ 7221 7222 #define MTBDWT_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) 7223 #define MTBDWT_PERIPHID2_PERIPHID_SHIFT (0U) 7224 /*! PERIPHID - PERIPHID 7225 */ 7226 #define MTBDWT_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID2_PERIPHID_SHIFT)) & MTBDWT_PERIPHID2_PERIPHID_MASK) 7227 /*! @} */ 7228 7229 /*! @name PERIPHID3 - Peripheral ID Register */ 7230 /*! @{ */ 7231 7232 #define MTBDWT_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) 7233 #define MTBDWT_PERIPHID3_PERIPHID_SHIFT (0U) 7234 /*! PERIPHID - PERIPHID 7235 */ 7236 #define MTBDWT_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID3_PERIPHID_SHIFT)) & MTBDWT_PERIPHID3_PERIPHID_MASK) 7237 /*! @} */ 7238 7239 /*! @name COMPID - Component ID Register */ 7240 /*! @{ */ 7241 7242 #define MTBDWT_COMPID_COMPID_MASK (0xFFFFFFFFU) 7243 #define MTBDWT_COMPID_COMPID_SHIFT (0U) 7244 /*! COMPID - Component ID 7245 */ 7246 #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMPID_COMPID_SHIFT)) & MTBDWT_COMPID_COMPID_MASK) 7247 /*! @} */ 7248 7249 /* The count of MTBDWT_COMPID */ 7250 #define MTBDWT_COMPID_COUNT (4U) 7251 7252 7253 /*! 7254 * @} 7255 */ /* end of group MTBDWT_Register_Masks */ 7256 7257 7258 /* MTBDWT - Peripheral instance base addresses */ 7259 /** Peripheral MTBDWT base address */ 7260 #define MTBDWT_BASE (0xF0001000u) 7261 /** Peripheral MTBDWT base pointer */ 7262 #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE) 7263 /** Array initializer of MTBDWT peripheral base addresses */ 7264 #define MTBDWT_BASE_ADDRS { MTBDWT_BASE } 7265 /** Array initializer of MTBDWT peripheral base pointers */ 7266 #define MTBDWT_BASE_PTRS { MTBDWT } 7267 7268 /*! 7269 * @} 7270 */ /* end of group MTBDWT_Peripheral_Access_Layer */ 7271 7272 7273 /* ---------------------------------------------------------------------------- 7274 -- NV Peripheral Access Layer 7275 ---------------------------------------------------------------------------- */ 7276 7277 /*! 7278 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer 7279 * @{ 7280 */ 7281 7282 /** NV - Register Layout Typedef */ 7283 typedef struct { 7284 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */ 7285 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */ 7286 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */ 7287 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */ 7288 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */ 7289 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */ 7290 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */ 7291 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */ 7292 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */ 7293 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */ 7294 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */ 7295 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */ 7296 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */ 7297 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */ 7298 } NV_Type; 7299 7300 /* ---------------------------------------------------------------------------- 7301 -- NV Register Masks 7302 ---------------------------------------------------------------------------- */ 7303 7304 /*! 7305 * @addtogroup NV_Register_Masks NV Register Masks 7306 * @{ 7307 */ 7308 7309 /*! @name BACKKEY3 - Backdoor Comparison Key 3. */ 7310 /*! @{ */ 7311 7312 #define NV_BACKKEY3_KEY_MASK (0xFFU) 7313 #define NV_BACKKEY3_KEY_SHIFT (0U) 7314 /*! KEY - Backdoor Comparison Key. 7315 */ 7316 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK) 7317 /*! @} */ 7318 7319 /*! @name BACKKEY2 - Backdoor Comparison Key 2. */ 7320 /*! @{ */ 7321 7322 #define NV_BACKKEY2_KEY_MASK (0xFFU) 7323 #define NV_BACKKEY2_KEY_SHIFT (0U) 7324 /*! KEY - Backdoor Comparison Key. 7325 */ 7326 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK) 7327 /*! @} */ 7328 7329 /*! @name BACKKEY1 - Backdoor Comparison Key 1. */ 7330 /*! @{ */ 7331 7332 #define NV_BACKKEY1_KEY_MASK (0xFFU) 7333 #define NV_BACKKEY1_KEY_SHIFT (0U) 7334 /*! KEY - Backdoor Comparison Key. 7335 */ 7336 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK) 7337 /*! @} */ 7338 7339 /*! @name BACKKEY0 - Backdoor Comparison Key 0. */ 7340 /*! @{ */ 7341 7342 #define NV_BACKKEY0_KEY_MASK (0xFFU) 7343 #define NV_BACKKEY0_KEY_SHIFT (0U) 7344 /*! KEY - Backdoor Comparison Key. 7345 */ 7346 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK) 7347 /*! @} */ 7348 7349 /*! @name BACKKEY7 - Backdoor Comparison Key 7. */ 7350 /*! @{ */ 7351 7352 #define NV_BACKKEY7_KEY_MASK (0xFFU) 7353 #define NV_BACKKEY7_KEY_SHIFT (0U) 7354 /*! KEY - Backdoor Comparison Key. 7355 */ 7356 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK) 7357 /*! @} */ 7358 7359 /*! @name BACKKEY6 - Backdoor Comparison Key 6. */ 7360 /*! @{ */ 7361 7362 #define NV_BACKKEY6_KEY_MASK (0xFFU) 7363 #define NV_BACKKEY6_KEY_SHIFT (0U) 7364 /*! KEY - Backdoor Comparison Key. 7365 */ 7366 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK) 7367 /*! @} */ 7368 7369 /*! @name BACKKEY5 - Backdoor Comparison Key 5. */ 7370 /*! @{ */ 7371 7372 #define NV_BACKKEY5_KEY_MASK (0xFFU) 7373 #define NV_BACKKEY5_KEY_SHIFT (0U) 7374 /*! KEY - Backdoor Comparison Key. 7375 */ 7376 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK) 7377 /*! @} */ 7378 7379 /*! @name BACKKEY4 - Backdoor Comparison Key 4. */ 7380 /*! @{ */ 7381 7382 #define NV_BACKKEY4_KEY_MASK (0xFFU) 7383 #define NV_BACKKEY4_KEY_SHIFT (0U) 7384 /*! KEY - Backdoor Comparison Key. 7385 */ 7386 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK) 7387 /*! @} */ 7388 7389 /*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */ 7390 /*! @{ */ 7391 7392 #define NV_FPROT3_PROT_MASK (0xFFU) 7393 #define NV_FPROT3_PROT_SHIFT (0U) 7394 /*! PROT - P-Flash Region Protect 7395 */ 7396 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK) 7397 /*! @} */ 7398 7399 /*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */ 7400 /*! @{ */ 7401 7402 #define NV_FPROT2_PROT_MASK (0xFFU) 7403 #define NV_FPROT2_PROT_SHIFT (0U) 7404 /*! PROT - P-Flash Region Protect 7405 */ 7406 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK) 7407 /*! @} */ 7408 7409 /*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */ 7410 /*! @{ */ 7411 7412 #define NV_FPROT1_PROT_MASK (0xFFU) 7413 #define NV_FPROT1_PROT_SHIFT (0U) 7414 /*! PROT - P-Flash Region Protect 7415 */ 7416 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK) 7417 /*! @} */ 7418 7419 /*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */ 7420 /*! @{ */ 7421 7422 #define NV_FPROT0_PROT_MASK (0xFFU) 7423 #define NV_FPROT0_PROT_SHIFT (0U) 7424 /*! PROT - P-Flash Region Protect 7425 */ 7426 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK) 7427 /*! @} */ 7428 7429 /*! @name FSEC - Non-volatile Flash Security Register */ 7430 /*! @{ */ 7431 7432 #define NV_FSEC_SEC_MASK (0x3U) 7433 #define NV_FSEC_SEC_SHIFT (0U) 7434 /*! SEC - Flash Security 7435 * 0b10..MCU security status is unsecure 7436 * 0b11..MCU security status is secure 7437 */ 7438 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK) 7439 7440 #define NV_FSEC_FSLACC_MASK (0xCU) 7441 #define NV_FSEC_FSLACC_SHIFT (2U) 7442 /*! FSLACC - Freescale Failure Analysis Access Code 7443 * 0b10..Freescale factory access denied 7444 * 0b11..Freescale factory access granted 7445 */ 7446 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK) 7447 7448 #define NV_FSEC_MEEN_MASK (0x30U) 7449 #define NV_FSEC_MEEN_SHIFT (4U) 7450 /*! MEEN 7451 * 0b10..Mass erase is disabled 7452 * 0b11..Mass erase is enabled 7453 */ 7454 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK) 7455 7456 #define NV_FSEC_KEYEN_MASK (0xC0U) 7457 #define NV_FSEC_KEYEN_SHIFT (6U) 7458 /*! KEYEN - Backdoor Key Security Enable 7459 * 0b10..Backdoor key access enabled 7460 * 0b11..Backdoor key access disabled 7461 */ 7462 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK) 7463 /*! @} */ 7464 7465 /*! @name FOPT - Non-volatile Flash Option Register */ 7466 /*! @{ */ 7467 7468 #define NV_FOPT_LPBOOT_MASK (0x1U) 7469 #define NV_FOPT_LPBOOT_SHIFT (0U) 7470 /*! LPBOOT 7471 * 0b0..Low-power boot 7472 * 0b1..Normal boot 7473 */ 7474 #define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK) 7475 7476 #define NV_FOPT_NMI_EN_MASK (0x4U) 7477 #define NV_FOPT_NMI_EN_SHIFT (2U) 7478 /*! NMI_EN 7479 * 0b0..NMI interrupts are always blocked 7480 * 0b1..NMI_b pin/interrupts reset default to enabled 7481 */ 7482 #define NV_FOPT_NMI_EN(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_EN_SHIFT)) & NV_FOPT_NMI_EN_MASK) 7483 7484 #define NV_FOPT_EXE_MODE_MASK (0x8U) 7485 #define NV_FOPT_EXE_MODE_SHIFT (3U) 7486 /*! EXE_MODE 7487 * 0b0..Execution Mode is RUN Mode 7488 * 0b1..Execution Mode is VLPR Mode 7489 */ 7490 #define NV_FOPT_EXE_MODE(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_EXE_MODE_SHIFT)) & NV_FOPT_EXE_MODE_MASK) 7491 7492 #define NV_FOPT_CLK_SRC_MASK (0x20U) 7493 #define NV_FOPT_CLK_SRC_SHIFT (5U) 7494 /*! CLK_SRC 7495 * 0b0..Externally supplied clock used by Flash 7496 * 0b1..Internal clock source used by Flash 7497 */ 7498 #define NV_FOPT_CLK_SRC(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_CLK_SRC_SHIFT)) & NV_FOPT_CLK_SRC_MASK) 7499 /*! @} */ 7500 7501 7502 /*! 7503 * @} 7504 */ /* end of group NV_Register_Masks */ 7505 7506 7507 /* NV - Peripheral instance base addresses */ 7508 /** Peripheral FTFA_FlashConfig base address */ 7509 #define FTFA_FlashConfig_BASE (0x400u) 7510 /** Peripheral FTFA_FlashConfig base pointer */ 7511 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE) 7512 /** Array initializer of NV peripheral base addresses */ 7513 #define NV_BASE_ADDRS { FTFA_FlashConfig_BASE } 7514 /** Array initializer of NV peripheral base pointers */ 7515 #define NV_BASE_PTRS { FTFA_FlashConfig } 7516 7517 /*! 7518 * @} 7519 */ /* end of group NV_Peripheral_Access_Layer */ 7520 7521 7522 /* ---------------------------------------------------------------------------- 7523 -- OSC Peripheral Access Layer 7524 ---------------------------------------------------------------------------- */ 7525 7526 /*! 7527 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer 7528 * @{ 7529 */ 7530 7531 /** OSC - Register Layout Typedef */ 7532 typedef struct { 7533 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */ 7534 } OSC_Type; 7535 7536 /* ---------------------------------------------------------------------------- 7537 -- OSC Register Masks 7538 ---------------------------------------------------------------------------- */ 7539 7540 /*! 7541 * @addtogroup OSC_Register_Masks OSC Register Masks 7542 * @{ 7543 */ 7544 7545 /*! @name CR - OSC Control Register */ 7546 /*! @{ */ 7547 7548 #define OSC_CR_SC16P_MASK (0x1U) 7549 #define OSC_CR_SC16P_SHIFT (0U) 7550 /*! SC16P - Oscillator 16 pF Capacitor Load Configure 7551 * 0b0..Disable the selection. 7552 * 0b1..Add 16 pF capacitor to the oscillator load. 7553 */ 7554 #define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK) 7555 7556 #define OSC_CR_SC8P_MASK (0x2U) 7557 #define OSC_CR_SC8P_SHIFT (1U) 7558 /*! SC8P - Oscillator 8 pF Capacitor Load Configure 7559 * 0b0..Disable the selection. 7560 * 0b1..Add 8 pF capacitor to the oscillator load. 7561 */ 7562 #define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK) 7563 7564 #define OSC_CR_SC4P_MASK (0x4U) 7565 #define OSC_CR_SC4P_SHIFT (2U) 7566 /*! SC4P - Oscillator 4 pF Capacitor Load Configure 7567 * 0b0..Disable the selection. 7568 * 0b1..Add 4 pF capacitor to the oscillator load. 7569 */ 7570 #define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK) 7571 7572 #define OSC_CR_SC2P_MASK (0x8U) 7573 #define OSC_CR_SC2P_SHIFT (3U) 7574 /*! SC2P - Oscillator 2 pF Capacitor Load Configure 7575 * 0b0..Disable the selection. 7576 * 0b1..Add 2 pF capacitor to the oscillator load. 7577 */ 7578 #define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK) 7579 7580 #define OSC_CR_EREFSTEN_MASK (0x20U) 7581 #define OSC_CR_EREFSTEN_SHIFT (5U) 7582 /*! EREFSTEN - External Reference Stop Enable 7583 * 0b0..External reference clock is disabled in Stop mode. 7584 * 0b1..External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode. 7585 */ 7586 #define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK) 7587 7588 #define OSC_CR_ERCLKEN_MASK (0x80U) 7589 #define OSC_CR_ERCLKEN_SHIFT (7U) 7590 /*! ERCLKEN - External Reference Enable 7591 * 0b0..External reference clock is inactive. 7592 * 0b1..External reference clock is enabled. 7593 */ 7594 #define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK) 7595 /*! @} */ 7596 7597 7598 /*! 7599 * @} 7600 */ /* end of group OSC_Register_Masks */ 7601 7602 7603 /* OSC - Peripheral instance base addresses */ 7604 /** Peripheral OSC base address */ 7605 #define OSC_BASE (0x40066000u) 7606 /** Peripheral OSC base pointer */ 7607 #define OSC ((OSC_Type *)OSC_BASE) 7608 /** Array initializer of OSC peripheral base addresses */ 7609 #define OSC_BASE_ADDRS { OSC_BASE } 7610 /** Array initializer of OSC peripheral base pointers */ 7611 #define OSC_BASE_PTRS { OSC } 7612 7613 /*! 7614 * @} 7615 */ /* end of group OSC_Peripheral_Access_Layer */ 7616 7617 7618 /* ---------------------------------------------------------------------------- 7619 -- PIT Peripheral Access Layer 7620 ---------------------------------------------------------------------------- */ 7621 7622 /*! 7623 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer 7624 * @{ 7625 */ 7626 7627 /** PIT - Register Layout Typedef */ 7628 typedef struct { 7629 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ 7630 uint8_t RESERVED_0[252]; 7631 struct { /* offset: 0x100, array step: 0x10 */ 7632 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ 7633 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ 7634 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ 7635 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ 7636 } CHANNEL[2]; 7637 } PIT_Type; 7638 7639 /* ---------------------------------------------------------------------------- 7640 -- PIT Register Masks 7641 ---------------------------------------------------------------------------- */ 7642 7643 /*! 7644 * @addtogroup PIT_Register_Masks PIT Register Masks 7645 * @{ 7646 */ 7647 7648 /*! @name MCR - PIT Module Control Register */ 7649 /*! @{ */ 7650 7651 #define PIT_MCR_FRZ_MASK (0x1U) 7652 #define PIT_MCR_FRZ_SHIFT (0U) 7653 /*! FRZ - Freeze 7654 * 0b0..Timers continue to run in Debug mode. 7655 * 0b1..Timers are stopped in Debug mode. 7656 */ 7657 #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK) 7658 7659 #define PIT_MCR_MDIS_MASK (0x2U) 7660 #define PIT_MCR_MDIS_SHIFT (1U) 7661 /*! MDIS - Module Disable - (PIT section) 7662 * 0b0..Clock for standard PIT timers is enabled. 7663 * 0b1..Clock for standard PIT timers is disabled. 7664 */ 7665 #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK) 7666 /*! @} */ 7667 7668 /*! @name LDVAL - Timer Load Value Register */ 7669 /*! @{ */ 7670 7671 #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU) 7672 #define PIT_LDVAL_TSV_SHIFT (0U) 7673 /*! TSV - Timer Start Value 7674 */ 7675 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK) 7676 /*! @} */ 7677 7678 /* The count of PIT_LDVAL */ 7679 #define PIT_LDVAL_COUNT (2U) 7680 7681 /*! @name CVAL - Current Timer Value Register */ 7682 /*! @{ */ 7683 7684 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) 7685 #define PIT_CVAL_TVL_SHIFT (0U) 7686 /*! TVL - Current Timer Value 7687 */ 7688 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK) 7689 /*! @} */ 7690 7691 /* The count of PIT_CVAL */ 7692 #define PIT_CVAL_COUNT (2U) 7693 7694 /*! @name TCTRL - Timer Control Register */ 7695 /*! @{ */ 7696 7697 #define PIT_TCTRL_TEN_MASK (0x1U) 7698 #define PIT_TCTRL_TEN_SHIFT (0U) 7699 /*! TEN - Timer Enable 7700 * 0b0..Timer n is disabled. 7701 * 0b1..Timer n is enabled. 7702 */ 7703 #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) 7704 7705 #define PIT_TCTRL_TIE_MASK (0x2U) 7706 #define PIT_TCTRL_TIE_SHIFT (1U) 7707 /*! TIE - Timer Interrupt Enable 7708 * 0b0..Interrupt requests from Timer n are disabled. 7709 * 0b1..Interrupt will be requested whenever TIF is set. 7710 */ 7711 #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK) 7712 7713 #define PIT_TCTRL_CHN_MASK (0x4U) 7714 #define PIT_TCTRL_CHN_SHIFT (2U) 7715 /*! CHN - Chain Mode 7716 * 0b0..Timer is not chained. 7717 * 0b1..Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1. 7718 */ 7719 #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK) 7720 /*! @} */ 7721 7722 /* The count of PIT_TCTRL */ 7723 #define PIT_TCTRL_COUNT (2U) 7724 7725 /*! @name TFLG - Timer Flag Register */ 7726 /*! @{ */ 7727 7728 #define PIT_TFLG_TIF_MASK (0x1U) 7729 #define PIT_TFLG_TIF_SHIFT (0U) 7730 /*! TIF - Timer Interrupt Flag 7731 * 0b0..Timeout has not yet occurred. 7732 * 0b1..Timeout has occurred. 7733 */ 7734 #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK) 7735 /*! @} */ 7736 7737 /* The count of PIT_TFLG */ 7738 #define PIT_TFLG_COUNT (2U) 7739 7740 7741 /*! 7742 * @} 7743 */ /* end of group PIT_Register_Masks */ 7744 7745 7746 /* PIT - Peripheral instance base addresses */ 7747 /** Peripheral PIT0 base address */ 7748 #define PIT0_BASE (0x4002D000u) 7749 /** Peripheral PIT0 base pointer */ 7750 #define PIT0 ((PIT_Type *)PIT0_BASE) 7751 /** Peripheral PIT1 base address */ 7752 #define PIT1_BASE (0x4002E000u) 7753 /** Peripheral PIT1 base pointer */ 7754 #define PIT1 ((PIT_Type *)PIT1_BASE) 7755 /** Array initializer of PIT peripheral base addresses */ 7756 #define PIT_BASE_ADDRS { PIT0_BASE, PIT1_BASE } 7757 /** Array initializer of PIT peripheral base pointers */ 7758 #define PIT_BASE_PTRS { PIT0, PIT1 } 7759 /** Interrupt vectors for the PIT peripheral type */ 7760 #define PIT_IRQS { { PIT0_PIT1_IRQn, PIT0_PIT1_IRQn }, { PIT0_PIT1_IRQn, PIT0_PIT1_IRQn } } 7761 7762 /*! 7763 * @} 7764 */ /* end of group PIT_Peripheral_Access_Layer */ 7765 7766 7767 /* ---------------------------------------------------------------------------- 7768 -- PMC Peripheral Access Layer 7769 ---------------------------------------------------------------------------- */ 7770 7771 /*! 7772 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer 7773 * @{ 7774 */ 7775 7776 /** PMC - Register Layout Typedef */ 7777 typedef struct { 7778 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */ 7779 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */ 7780 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */ 7781 } PMC_Type; 7782 7783 /* ---------------------------------------------------------------------------- 7784 -- PMC Register Masks 7785 ---------------------------------------------------------------------------- */ 7786 7787 /*! 7788 * @addtogroup PMC_Register_Masks PMC Register Masks 7789 * @{ 7790 */ 7791 7792 /*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */ 7793 /*! @{ */ 7794 7795 #define PMC_LVDSC1_LVDV_MASK (0x3U) 7796 #define PMC_LVDSC1_LVDV_SHIFT (0U) 7797 /*! LVDV - Low-Voltage Detect Voltage Select 7798 * 0b00..Low trip point selected (V LVD = V LVDL ) 7799 * 0b01..High trip point selected (V LVD = V LVDH ) 7800 * 0b10..Reserved 7801 * 0b11..Reserved 7802 */ 7803 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK) 7804 7805 #define PMC_LVDSC1_LVDRE_MASK (0x10U) 7806 #define PMC_LVDSC1_LVDRE_SHIFT (4U) 7807 /*! LVDRE - Low-Voltage Detect Reset Enable 7808 * 0b0..LVDF does not generate hardware resets 7809 * 0b1..Force an MCU reset when LVDF = 1 7810 */ 7811 #define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK) 7812 7813 #define PMC_LVDSC1_LVDIE_MASK (0x20U) 7814 #define PMC_LVDSC1_LVDIE_SHIFT (5U) 7815 /*! LVDIE - Low-Voltage Detect Interrupt Enable 7816 * 0b0..Hardware interrupt disabled (use polling) 7817 * 0b1..Request a hardware interrupt when LVDF = 1 7818 */ 7819 #define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK) 7820 7821 #define PMC_LVDSC1_LVDACK_MASK (0x40U) 7822 #define PMC_LVDSC1_LVDACK_SHIFT (6U) 7823 /*! LVDACK - Low-Voltage Detect Acknowledge 7824 */ 7825 #define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK) 7826 7827 #define PMC_LVDSC1_LVDF_MASK (0x80U) 7828 #define PMC_LVDSC1_LVDF_SHIFT (7U) 7829 /*! LVDF - Low-Voltage Detect Flag 7830 * 0b0..Low-voltage event not detected 7831 * 0b1..Low-voltage event detected 7832 */ 7833 #define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK) 7834 /*! @} */ 7835 7836 /*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */ 7837 /*! @{ */ 7838 7839 #define PMC_LVDSC2_LVWV_MASK (0x3U) 7840 #define PMC_LVDSC2_LVWV_SHIFT (0U) 7841 /*! LVWV - Low-Voltage Warning Voltage Select 7842 * 0b00..Low trip point selected (VLVW = VLVW1) 7843 * 0b01..Mid 1 trip point selected (VLVW = VLVW2) 7844 * 0b10..Mid 2 trip point selected (VLVW = VLVW3) 7845 * 0b11..High trip point selected (VLVW = VLVW4) 7846 */ 7847 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK) 7848 7849 #define PMC_LVDSC2_LVWIE_MASK (0x20U) 7850 #define PMC_LVDSC2_LVWIE_SHIFT (5U) 7851 /*! LVWIE - Low-Voltage Warning Interrupt Enable 7852 * 0b0..Hardware interrupt disabled (use polling) 7853 * 0b1..Request a hardware interrupt when LVWF = 1 7854 */ 7855 #define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK) 7856 7857 #define PMC_LVDSC2_LVWACK_MASK (0x40U) 7858 #define PMC_LVDSC2_LVWACK_SHIFT (6U) 7859 /*! LVWACK - Low-Voltage Warning Acknowledge 7860 */ 7861 #define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK) 7862 7863 #define PMC_LVDSC2_LVWF_MASK (0x80U) 7864 #define PMC_LVDSC2_LVWF_SHIFT (7U) 7865 /*! LVWF - Low-Voltage Warning Flag 7866 * 0b0..Low-voltage warning event not detected 7867 * 0b1..Low-voltage warning event detected 7868 */ 7869 #define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK) 7870 /*! @} */ 7871 7872 /*! @name REGSC - Regulator Status And Control register */ 7873 /*! @{ */ 7874 7875 #define PMC_REGSC_BGBE_MASK (0x1U) 7876 #define PMC_REGSC_BGBE_SHIFT (0U) 7877 /*! BGBE - Bandgap Buffer Enable 7878 * 0b0..Bandgap buffer not enabled 7879 * 0b1..Bandgap buffer enabled 7880 */ 7881 #define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK) 7882 7883 #define PMC_REGSC_BGBDS_MASK (0x2U) 7884 #define PMC_REGSC_BGBDS_SHIFT (1U) 7885 /*! BGBDS - Bandgap Buffer Drive Select 7886 * 0b0..Low drive 7887 * 0b1..High drive 7888 */ 7889 #define PMC_REGSC_BGBDS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBDS_SHIFT)) & PMC_REGSC_BGBDS_MASK) 7890 7891 #define PMC_REGSC_REGONS_MASK (0x4U) 7892 #define PMC_REGSC_REGONS_SHIFT (2U) 7893 /*! REGONS - Regulator In Run Regulation Status 7894 * 0b0..Regulator is in stop regulation or in transition to/from it 7895 * 0b1..Regulator is in run regulation 7896 */ 7897 #define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK) 7898 7899 #define PMC_REGSC_ACKISO_MASK (0x8U) 7900 #define PMC_REGSC_ACKISO_SHIFT (3U) 7901 /*! ACKISO - Acknowledge Isolation 7902 * 0b0..Peripherals and I/O pads are in normal run state. 7903 * 0b1..Certain peripherals and I/O pads are in an isolated and latched state. 7904 */ 7905 #define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK) 7906 7907 #define PMC_REGSC_BGEN_MASK (0x10U) 7908 #define PMC_REGSC_BGEN_SHIFT (4U) 7909 /*! BGEN - Bandgap Enable In VLPx Operation 7910 * 0b0..Bandgap voltage reference is disabled in VLPx , and VLLSx modes. 7911 * 0b1..Bandgap voltage reference is enabled in VLPx , and VLLSx modes. 7912 */ 7913 #define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK) 7914 /*! @} */ 7915 7916 7917 /*! 7918 * @} 7919 */ /* end of group PMC_Register_Masks */ 7920 7921 7922 /* PMC - Peripheral instance base addresses */ 7923 /** Peripheral PMC base address */ 7924 #define PMC_BASE (0x4007D000u) 7925 /** Peripheral PMC base pointer */ 7926 #define PMC ((PMC_Type *)PMC_BASE) 7927 /** Array initializer of PMC peripheral base addresses */ 7928 #define PMC_BASE_ADDRS { PMC_BASE } 7929 /** Array initializer of PMC peripheral base pointers */ 7930 #define PMC_BASE_PTRS { PMC } 7931 /** Interrupt vectors for the PMC peripheral type */ 7932 #define PMC_IRQS { PMC_IRQn } 7933 7934 /*! 7935 * @} 7936 */ /* end of group PMC_Peripheral_Access_Layer */ 7937 7938 7939 /* ---------------------------------------------------------------------------- 7940 -- PORT Peripheral Access Layer 7941 ---------------------------------------------------------------------------- */ 7942 7943 /*! 7944 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer 7945 * @{ 7946 */ 7947 7948 /** PORT - Register Layout Typedef */ 7949 typedef struct { 7950 __IO uint32_t PCR[8]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */ 7951 uint8_t RESERVED_0[96]; 7952 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */ 7953 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */ 7954 uint8_t RESERVED_1[24]; 7955 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */ 7956 uint8_t RESERVED_2[28]; 7957 __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */ 7958 __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */ 7959 __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */ 7960 } PORT_Type; 7961 7962 /* ---------------------------------------------------------------------------- 7963 -- PORT Register Masks 7964 ---------------------------------------------------------------------------- */ 7965 7966 /*! 7967 * @addtogroup PORT_Register_Masks PORT Register Masks 7968 * @{ 7969 */ 7970 7971 /*! @name PCR - Pin Control Register n */ 7972 /*! @{ */ 7973 7974 #define PORT_PCR_PS_MASK (0x1U) 7975 #define PORT_PCR_PS_SHIFT (0U) 7976 /*! PS - Pull Select 7977 * 0b0..Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set. 7978 * 0b1..Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set. 7979 */ 7980 #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK) 7981 7982 #define PORT_PCR_PE_MASK (0x2U) 7983 #define PORT_PCR_PE_SHIFT (1U) 7984 /*! PE - Pull Enable 7985 * 0b0..Internal pullup or pulldown resistor is not enabled on the corresponding pin. 7986 * 0b1..Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input. 7987 */ 7988 #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK) 7989 7990 #define PORT_PCR_SRE_MASK (0x4U) 7991 #define PORT_PCR_SRE_SHIFT (2U) 7992 /*! SRE - Slew Rate Enable 7993 * 0b0..Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 7994 * 0b1..Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output. 7995 */ 7996 #define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK) 7997 7998 #define PORT_PCR_MUX_MASK (0x700U) 7999 #define PORT_PCR_MUX_SHIFT (8U) 8000 /*! MUX - Pin Mux Control 8001 * 0b000..Pin disabled (analog). 8002 * 0b001..Alternative 1 (GPIO). 8003 * 0b010..Alternative 2 (chip-specific). 8004 * 0b011..Alternative 3 (chip-specific). 8005 * 0b100..Alternative 4 (chip-specific). 8006 * 0b101..Alternative 5 (chip-specific). 8007 * 0b110..Alternative 6 (chip-specific). 8008 * 0b111..Alternative 7 (chip-specific). 8009 */ 8010 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) 8011 8012 #define PORT_PCR_LK_MASK (0x8000U) 8013 #define PORT_PCR_LK_SHIFT (15U) 8014 /*! LK - Lock Register 8015 * 0b0..Pin Control Register fields [15:0] are not locked. 8016 * 0b1..Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset. 8017 */ 8018 #define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK) 8019 8020 #define PORT_PCR_IRQC_MASK (0xF0000U) 8021 #define PORT_PCR_IRQC_SHIFT (16U) 8022 /*! IRQC - Interrupt Configuration 8023 * 0b0000..Interrupt/DMA request disabled. 8024 * 0b0001..DMA request on rising edge. 8025 * 0b0010..DMA request on falling edge. 8026 * 0b0011..DMA request on either edge. 8027 * 0b1000..Interrupt when logic zero. 8028 * 0b1001..Interrupt on rising edge. 8029 * 0b1010..Interrupt on falling edge. 8030 * 0b1011..Interrupt on either edge. 8031 * 0b1100..Interrupt when logic one. 8032 */ 8033 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK) 8034 8035 #define PORT_PCR_ISF_MASK (0x1000000U) 8036 #define PORT_PCR_ISF_SHIFT (24U) 8037 /*! ISF - Interrupt Status Flag 8038 * 0b0..Configured interrupt is not detected. 8039 * 0b1..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the 8040 * corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the 8041 * flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive 8042 * interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared. 8043 */ 8044 #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK) 8045 /*! @} */ 8046 8047 /* The count of PORT_PCR */ 8048 #define PORT_PCR_COUNT (8U) 8049 8050 /*! @name GPCLR - Global Pin Control Low Register */ 8051 /*! @{ */ 8052 8053 #define PORT_GPCLR_GPWD_MASK (0xFFFFU) 8054 #define PORT_GPCLR_GPWD_SHIFT (0U) 8055 /*! GPWD - Global Pin Write Data 8056 */ 8057 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK) 8058 8059 #define PORT_GPCLR_GPWE_MASK (0xFFFF0000U) 8060 #define PORT_GPCLR_GPWE_SHIFT (16U) 8061 /*! GPWE - Global Pin Write Enable 8062 * 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD. 8063 * 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD. 8064 */ 8065 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK) 8066 /*! @} */ 8067 8068 /*! @name GPCHR - Global Pin Control High Register */ 8069 /*! @{ */ 8070 8071 #define PORT_GPCHR_GPWD_MASK (0xFFFFU) 8072 #define PORT_GPCHR_GPWD_SHIFT (0U) 8073 /*! GPWD - Global Pin Write Data 8074 */ 8075 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK) 8076 8077 #define PORT_GPCHR_GPWE_MASK (0xFFFF0000U) 8078 #define PORT_GPCHR_GPWE_SHIFT (16U) 8079 /*! GPWE - Global Pin Write Enable 8080 * 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD. 8081 * 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD. 8082 */ 8083 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK) 8084 /*! @} */ 8085 8086 /*! @name ISFR - Interrupt Status Flag Register */ 8087 /*! @{ */ 8088 8089 #define PORT_ISFR_ISF_MASK (0xFFFFFFFFU) 8090 #define PORT_ISFR_ISF_SHIFT (0U) 8091 /*! ISF - Interrupt Status Flag 8092 * 0b00000000000000000000000000000000..Configured interrupt is not detected. 8093 * 0b00000000000000000000000000000001..Configured interrupt is detected. If the pin is configured to generate a 8094 * DMA request, then the corresponding flag will be cleared automatically at 8095 * the completion of the requested DMA transfer. Otherwise, the flag remains set 8096 * until a logic one is written to the flag. If the pin is configured for a 8097 * level sensitive interrupt and the pin remains asserted, then the flag is set 8098 * again immediately after it is cleared. 8099 */ 8100 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK) 8101 /*! @} */ 8102 8103 /*! @name DFER - Digital Filter Enable Register */ 8104 /*! @{ */ 8105 8106 #define PORT_DFER_DFE_MASK (0xFFFFFFFFU) 8107 #define PORT_DFER_DFE_SHIFT (0U) 8108 /*! DFE - Digital Filter Enable 8109 * 0b00000000000000000000000000000000..Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero. 8110 * 0b00000000000000000000000000000001..Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input. 8111 */ 8112 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK) 8113 /*! @} */ 8114 8115 /*! @name DFCR - Digital Filter Clock Register */ 8116 /*! @{ */ 8117 8118 #define PORT_DFCR_CS_MASK (0x1U) 8119 #define PORT_DFCR_CS_SHIFT (0U) 8120 /*! CS - Clock Source 8121 * 0b0..Digital filters are clocked by the bus clock. 8122 * 0b1..Digital filters are clocked by the 1 kHz LPO clock. 8123 */ 8124 #define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK) 8125 /*! @} */ 8126 8127 /*! @name DFWR - Digital Filter Width Register */ 8128 /*! @{ */ 8129 8130 #define PORT_DFWR_FILT_MASK (0x1FU) 8131 #define PORT_DFWR_FILT_SHIFT (0U) 8132 /*! FILT - Filter Length 8133 */ 8134 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK) 8135 /*! @} */ 8136 8137 8138 /*! 8139 * @} 8140 */ /* end of group PORT_Register_Masks */ 8141 8142 8143 /* PORT - Peripheral instance base addresses */ 8144 /** Peripheral PORTA base address */ 8145 #define PORTA_BASE (0x40046000u) 8146 /** Peripheral PORTA base pointer */ 8147 #define PORTA ((PORT_Type *)PORTA_BASE) 8148 /** Peripheral PORTB base address */ 8149 #define PORTB_BASE (0x40047000u) 8150 /** Peripheral PORTB base pointer */ 8151 #define PORTB ((PORT_Type *)PORTB_BASE) 8152 /** Peripheral PORTC base address */ 8153 #define PORTC_BASE (0x40048000u) 8154 /** Peripheral PORTC base pointer */ 8155 #define PORTC ((PORT_Type *)PORTC_BASE) 8156 /** Peripheral PORTD base address */ 8157 #define PORTD_BASE (0x40049000u) 8158 /** Peripheral PORTD base pointer */ 8159 #define PORTD ((PORT_Type *)PORTD_BASE) 8160 /** Peripheral PORTE base address */ 8161 #define PORTE_BASE (0x4004A000u) 8162 /** Peripheral PORTE base pointer */ 8163 #define PORTE ((PORT_Type *)PORTE_BASE) 8164 /** Peripheral PORTF base address */ 8165 #define PORTF_BASE (0x4004B000u) 8166 /** Peripheral PORTF base pointer */ 8167 #define PORTF ((PORT_Type *)PORTF_BASE) 8168 /** Peripheral PORTG base address */ 8169 #define PORTG_BASE (0x4004C000u) 8170 /** Peripheral PORTG base pointer */ 8171 #define PORTG ((PORT_Type *)PORTG_BASE) 8172 /** Peripheral PORTH base address */ 8173 #define PORTH_BASE (0x4004D000u) 8174 /** Peripheral PORTH base pointer */ 8175 #define PORTH ((PORT_Type *)PORTH_BASE) 8176 /** Peripheral PORTI base address */ 8177 #define PORTI_BASE (0x4004E000u) 8178 /** Peripheral PORTI base pointer */ 8179 #define PORTI ((PORT_Type *)PORTI_BASE) 8180 /** Array initializer of PORT peripheral base addresses */ 8181 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE, PORTF_BASE, PORTG_BASE, PORTH_BASE, PORTI_BASE } 8182 /** Array initializer of PORT peripheral base pointers */ 8183 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE, PORTF, PORTG, PORTH, PORTI } 8184 /** Interrupt vectors for the PORT peripheral type */ 8185 #define PORT_IRQS { PTx_IRQn, PTx_IRQn, PTx_IRQn, PTx_IRQn, PTx_IRQn, PTx_IRQn, PTx_IRQn, PTx_IRQn, PTx_IRQn } 8186 8187 /*! 8188 * @} 8189 */ /* end of group PORT_Peripheral_Access_Layer */ 8190 8191 8192 /* ---------------------------------------------------------------------------- 8193 -- RCM Peripheral Access Layer 8194 ---------------------------------------------------------------------------- */ 8195 8196 /*! 8197 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer 8198 * @{ 8199 */ 8200 8201 /** RCM - Register Layout Typedef */ 8202 typedef struct { 8203 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */ 8204 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */ 8205 uint8_t RESERVED_0[2]; 8206 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */ 8207 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */ 8208 } RCM_Type; 8209 8210 /* ---------------------------------------------------------------------------- 8211 -- RCM Register Masks 8212 ---------------------------------------------------------------------------- */ 8213 8214 /*! 8215 * @addtogroup RCM_Register_Masks RCM Register Masks 8216 * @{ 8217 */ 8218 8219 /*! @name SRS0 - System Reset Status Register 0 */ 8220 /*! @{ */ 8221 8222 #define RCM_SRS0_WAKEUP_MASK (0x1U) 8223 #define RCM_SRS0_WAKEUP_SHIFT (0U) 8224 /*! WAKEUP - Low Leakage Wakeup Reset 8225 * 0b0..Reset not caused by wakeup source 8226 * 0b1..Reset caused by wakeup source 8227 */ 8228 #define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK) 8229 8230 #define RCM_SRS0_LVD_MASK (0x2U) 8231 #define RCM_SRS0_LVD_SHIFT (1U) 8232 /*! LVD - Low-Voltage Detect Reset 8233 * 0b0..Reset not caused by LVD trip or POR 8234 * 0b1..Reset caused by LVD trip or POR 8235 */ 8236 #define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK) 8237 8238 #define RCM_SRS0_LOC_MASK (0x4U) 8239 #define RCM_SRS0_LOC_SHIFT (2U) 8240 /*! LOC - Loss-of-Clock Reset 8241 * 0b0..Reset not caused by a loss of external clock. 8242 * 0b1..Reset caused by a loss of external clock. 8243 */ 8244 #define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK) 8245 8246 #define RCM_SRS0_LOL_MASK (0x8U) 8247 #define RCM_SRS0_LOL_SHIFT (3U) 8248 /*! LOL - Loss-of-Lock Reset 8249 * 0b0..Reset not caused by a loss of lock in the PLL 8250 * 0b1..Reset caused by a loss of lock in the PLL 8251 */ 8252 #define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK) 8253 8254 #define RCM_SRS0_WDOG_MASK (0x20U) 8255 #define RCM_SRS0_WDOG_SHIFT (5U) 8256 /*! WDOG - Watchdog 8257 * 0b0..Reset not caused by watchdog timeout 8258 * 0b1..Reset caused by watchdog timeout 8259 */ 8260 #define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK) 8261 8262 #define RCM_SRS0_PIN_MASK (0x40U) 8263 #define RCM_SRS0_PIN_SHIFT (6U) 8264 /*! PIN - External Reset Pin 8265 * 0b0..Reset not caused by external reset pin 8266 * 0b1..Reset caused by external reset pin 8267 */ 8268 #define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK) 8269 8270 #define RCM_SRS0_POR_MASK (0x80U) 8271 #define RCM_SRS0_POR_SHIFT (7U) 8272 /*! POR - Power-On Reset 8273 * 0b0..Reset not caused by POR 8274 * 0b1..Reset caused by POR 8275 */ 8276 #define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK) 8277 /*! @} */ 8278 8279 /*! @name SRS1 - System Reset Status Register 1 */ 8280 /*! @{ */ 8281 8282 #define RCM_SRS1_LOCKUP_MASK (0x2U) 8283 #define RCM_SRS1_LOCKUP_SHIFT (1U) 8284 /*! LOCKUP - Core Lockup 8285 * 0b0..Reset not caused by core LOCKUP event 8286 * 0b1..Reset caused by core LOCKUP event 8287 */ 8288 #define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK) 8289 8290 #define RCM_SRS1_SW_MASK (0x4U) 8291 #define RCM_SRS1_SW_SHIFT (2U) 8292 /*! SW - Software 8293 * 0b0..Reset not caused by software setting of SYSRESETREQ bit 8294 * 0b1..Reset caused by software setting of SYSRESETREQ bit 8295 */ 8296 #define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK) 8297 8298 #define RCM_SRS1_MDM_AP_MASK (0x8U) 8299 #define RCM_SRS1_MDM_AP_SHIFT (3U) 8300 /*! MDM_AP - MDM-AP System Reset Request 8301 * 0b0..Reset not caused by host debugger system setting of the System Reset Request bit 8302 * 0b1..Reset caused by host debugger system setting of the System Reset Request bit 8303 */ 8304 #define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK) 8305 8306 #define RCM_SRS1_SACKERR_MASK (0x20U) 8307 #define RCM_SRS1_SACKERR_SHIFT (5U) 8308 /*! SACKERR - Stop Mode Acknowledge Error Reset 8309 * 0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode 8310 * 0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode 8311 */ 8312 #define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK) 8313 /*! @} */ 8314 8315 /*! @name RPFC - Reset Pin Filter Control register */ 8316 /*! @{ */ 8317 8318 #define RCM_RPFC_RSTFLTSRW_MASK (0x3U) 8319 #define RCM_RPFC_RSTFLTSRW_SHIFT (0U) 8320 /*! RSTFLTSRW - Reset Pin Filter Select in Run and Wait Modes 8321 * 0b00..All filtering disabled 8322 * 0b01..Bus clock filter enabled for normal operation 8323 * 0b10..LPO clock filter enabled for normal operation 8324 * 0b11..Reserved 8325 */ 8326 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK) 8327 8328 #define RCM_RPFC_RSTFLTSS_MASK (0x4U) 8329 #define RCM_RPFC_RSTFLTSS_SHIFT (2U) 8330 /*! RSTFLTSS - Reset Pin Filter Select in Stop Mode 8331 * 0b0..All filtering disabled 8332 * 0b1..LPO clock filter enabled 8333 */ 8334 #define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK) 8335 /*! @} */ 8336 8337 /*! @name RPFW - Reset Pin Filter Width register */ 8338 /*! @{ */ 8339 8340 #define RCM_RPFW_RSTFLTSEL_MASK (0x1FU) 8341 #define RCM_RPFW_RSTFLTSEL_SHIFT (0U) 8342 /*! RSTFLTSEL - Reset Pin Filter Bus Clock Select 8343 * 0b00000..Bus clock filter count is 1 8344 * 0b00001..Bus clock filter count is 2 8345 * 0b00010..Bus clock filter count is 3 8346 * 0b00011..Bus clock filter count is 4 8347 * 0b00100..Bus clock filter count is 5 8348 * 0b00101..Bus clock filter count is 6 8349 * 0b00110..Bus clock filter count is 7 8350 * 0b00111..Bus clock filter count is 8 8351 * 0b01000..Bus clock filter count is 9 8352 * 0b01001..Bus clock filter count is 10 8353 * 0b01010..Bus clock filter count is 11 8354 * 0b01011..Bus clock filter count is 12 8355 * 0b01100..Bus clock filter count is 13 8356 * 0b01101..Bus clock filter count is 14 8357 * 0b01110..Bus clock filter count is 15 8358 * 0b01111..Bus clock filter count is 16 8359 * 0b10000..Bus clock filter count is 17 8360 * 0b10001..Bus clock filter count is 18 8361 * 0b10010..Bus clock filter count is 19 8362 * 0b10011..Bus clock filter count is 20 8363 * 0b10100..Bus clock filter count is 21 8364 * 0b10101..Bus clock filter count is 22 8365 * 0b10110..Bus clock filter count is 23 8366 * 0b10111..Bus clock filter count is 24 8367 * 0b11000..Bus clock filter count is 25 8368 * 0b11001..Bus clock filter count is 26 8369 * 0b11010..Bus clock filter count is 27 8370 * 0b11011..Bus clock filter count is 28 8371 * 0b11100..Bus clock filter count is 29 8372 * 0b11101..Bus clock filter count is 30 8373 * 0b11110..Bus clock filter count is 31 8374 * 0b11111..Bus clock filter count is 32 8375 */ 8376 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK) 8377 /*! @} */ 8378 8379 8380 /*! 8381 * @} 8382 */ /* end of group RCM_Register_Masks */ 8383 8384 8385 /* RCM - Peripheral instance base addresses */ 8386 /** Peripheral RCM base address */ 8387 #define RCM_BASE (0x4007B000u) 8388 /** Peripheral RCM base pointer */ 8389 #define RCM ((RCM_Type *)RCM_BASE) 8390 /** Array initializer of RCM peripheral base addresses */ 8391 #define RCM_BASE_ADDRS { RCM_BASE } 8392 /** Array initializer of RCM peripheral base pointers */ 8393 #define RCM_BASE_PTRS { RCM } 8394 8395 /*! 8396 * @} 8397 */ /* end of group RCM_Peripheral_Access_Layer */ 8398 8399 8400 /* ---------------------------------------------------------------------------- 8401 -- RNG Peripheral Access Layer 8402 ---------------------------------------------------------------------------- */ 8403 8404 /*! 8405 * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer 8406 * @{ 8407 */ 8408 8409 /** RNG - Register Layout Typedef */ 8410 typedef struct { 8411 __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */ 8412 __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */ 8413 __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */ 8414 __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */ 8415 } RNG_Type; 8416 8417 /* ---------------------------------------------------------------------------- 8418 -- RNG Register Masks 8419 ---------------------------------------------------------------------------- */ 8420 8421 /*! 8422 * @addtogroup RNG_Register_Masks RNG Register Masks 8423 * @{ 8424 */ 8425 8426 /*! @name CR - RNGA Control Register */ 8427 /*! @{ */ 8428 8429 #define RNG_CR_GO_MASK (0x1U) 8430 #define RNG_CR_GO_SHIFT (0U) 8431 /*! GO - Go 8432 * 0b0..Disabled 8433 * 0b1..Enabled 8434 */ 8435 #define RNG_CR_GO(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_GO_SHIFT)) & RNG_CR_GO_MASK) 8436 8437 #define RNG_CR_HA_MASK (0x2U) 8438 #define RNG_CR_HA_SHIFT (1U) 8439 /*! HA - High Assurance 8440 * 0b0..Disabled 8441 * 0b1..Enabled 8442 */ 8443 #define RNG_CR_HA(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_HA_SHIFT)) & RNG_CR_HA_MASK) 8444 8445 #define RNG_CR_INTM_MASK (0x4U) 8446 #define RNG_CR_INTM_SHIFT (2U) 8447 /*! INTM - Interrupt Mask 8448 * 0b0..Not masked 8449 * 0b1..Masked 8450 */ 8451 #define RNG_CR_INTM(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_INTM_SHIFT)) & RNG_CR_INTM_MASK) 8452 8453 #define RNG_CR_CLRI_MASK (0x8U) 8454 #define RNG_CR_CLRI_SHIFT (3U) 8455 /*! CLRI - Clear Interrupt 8456 * 0b0..Do not clear the interrupt. 8457 * 0b1..Clear the interrupt. When you write 1 to this field, RNGA then resets the error-interrupt indicator (SR[ERRI]). This bit always reads as 0. 8458 */ 8459 #define RNG_CR_CLRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_CLRI_SHIFT)) & RNG_CR_CLRI_MASK) 8460 8461 #define RNG_CR_SLP_MASK (0x10U) 8462 #define RNG_CR_SLP_SHIFT (4U) 8463 /*! SLP - Sleep 8464 * 0b0..Normal mode 8465 * 0b1..Sleep (low-power) mode 8466 */ 8467 #define RNG_CR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_SLP_SHIFT)) & RNG_CR_SLP_MASK) 8468 /*! @} */ 8469 8470 /*! @name SR - RNGA Status Register */ 8471 /*! @{ */ 8472 8473 #define RNG_SR_SECV_MASK (0x1U) 8474 #define RNG_SR_SECV_SHIFT (0U) 8475 /*! SECV - Security Violation 8476 * 0b0..No security violation 8477 * 0b1..Security violation 8478 */ 8479 #define RNG_SR_SECV(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SECV_SHIFT)) & RNG_SR_SECV_MASK) 8480 8481 #define RNG_SR_LRS_MASK (0x2U) 8482 #define RNG_SR_LRS_SHIFT (1U) 8483 /*! LRS - Last Read Status 8484 * 0b0..No underflow 8485 * 0b1..Underflow 8486 */ 8487 #define RNG_SR_LRS(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_LRS_SHIFT)) & RNG_SR_LRS_MASK) 8488 8489 #define RNG_SR_ORU_MASK (0x4U) 8490 #define RNG_SR_ORU_SHIFT (2U) 8491 /*! ORU - Output Register Underflow 8492 * 0b0..No underflow 8493 * 0b1..Underflow 8494 */ 8495 #define RNG_SR_ORU(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ORU_SHIFT)) & RNG_SR_ORU_MASK) 8496 8497 #define RNG_SR_ERRI_MASK (0x8U) 8498 #define RNG_SR_ERRI_SHIFT (3U) 8499 /*! ERRI - Error Interrupt 8500 * 0b0..No underflow 8501 * 0b1..Underflow 8502 */ 8503 #define RNG_SR_ERRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ERRI_SHIFT)) & RNG_SR_ERRI_MASK) 8504 8505 #define RNG_SR_SLP_MASK (0x10U) 8506 #define RNG_SR_SLP_SHIFT (4U) 8507 /*! SLP - Sleep 8508 * 0b0..Normal mode 8509 * 0b1..Sleep (low-power) mode 8510 */ 8511 #define RNG_SR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK) 8512 8513 #define RNG_SR_OREG_LVL_MASK (0xFF00U) 8514 #define RNG_SR_OREG_LVL_SHIFT (8U) 8515 /*! OREG_LVL - Output Register Level 8516 * 0b00000000..No words (empty) 8517 * 0b00000001..One word (valid) 8518 */ 8519 #define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK) 8520 8521 #define RNG_SR_OREG_SIZE_MASK (0xFF0000U) 8522 #define RNG_SR_OREG_SIZE_SHIFT (16U) 8523 /*! OREG_SIZE - Output Register Size 8524 * 0b00000001..One word (this value is fixed) 8525 */ 8526 #define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK) 8527 /*! @} */ 8528 8529 /*! @name ER - RNGA Entropy Register */ 8530 /*! @{ */ 8531 8532 #define RNG_ER_EXT_ENT_MASK (0xFFFFFFFFU) 8533 #define RNG_ER_EXT_ENT_SHIFT (0U) 8534 /*! EXT_ENT - External Entropy 8535 */ 8536 #define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x)) << RNG_ER_EXT_ENT_SHIFT)) & RNG_ER_EXT_ENT_MASK) 8537 /*! @} */ 8538 8539 /*! @name OR - RNGA Output Register */ 8540 /*! @{ */ 8541 8542 #define RNG_OR_RANDOUT_MASK (0xFFFFFFFFU) 8543 #define RNG_OR_RANDOUT_SHIFT (0U) 8544 /*! RANDOUT - Random Output 8545 * 0b00000000000000000000000000000000..Invalid data (if you read this field when it is 0 and SR[OREG_LVL] is 0, 8546 * RNGA then writes 1 to SR[ERRI], SR[ORU], and SR[LRS]; when the error 8547 * interrupt is not masked (CR[INTM]=0), RNGA also asserts an error interrupt request 8548 * to the interrupt controller). 8549 */ 8550 #define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x)) << RNG_OR_RANDOUT_SHIFT)) & RNG_OR_RANDOUT_MASK) 8551 /*! @} */ 8552 8553 8554 /*! 8555 * @} 8556 */ /* end of group RNG_Register_Masks */ 8557 8558 8559 /* RNG - Peripheral instance base addresses */ 8560 /** Peripheral RNG base address */ 8561 #define RNG_BASE (0x40029000u) 8562 /** Peripheral RNG base pointer */ 8563 #define RNG ((RNG_Type *)RNG_BASE) 8564 /** Array initializer of RNG peripheral base addresses */ 8565 #define RNG_BASE_ADDRS { RNG_BASE } 8566 /** Array initializer of RNG peripheral base pointers */ 8567 #define RNG_BASE_PTRS { RNG } 8568 /** Interrupt vectors for the RNG peripheral type */ 8569 #define RNG_IRQS { RNGA_IRQn } 8570 8571 /*! 8572 * @} 8573 */ /* end of group RNG_Peripheral_Access_Layer */ 8574 8575 8576 /* ---------------------------------------------------------------------------- 8577 -- ROM Peripheral Access Layer 8578 ---------------------------------------------------------------------------- */ 8579 8580 /*! 8581 * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer 8582 * @{ 8583 */ 8584 8585 /** ROM - Register Layout Typedef */ 8586 typedef struct { 8587 __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */ 8588 __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */ 8589 uint8_t RESERVED_0[4028]; 8590 __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */ 8591 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ 8592 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ 8593 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ 8594 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ 8595 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ 8596 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ 8597 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ 8598 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ 8599 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ 8600 } ROM_Type; 8601 8602 /* ---------------------------------------------------------------------------- 8603 -- ROM Register Masks 8604 ---------------------------------------------------------------------------- */ 8605 8606 /*! 8607 * @addtogroup ROM_Register_Masks ROM Register Masks 8608 * @{ 8609 */ 8610 8611 /*! @name ENTRY - Entry */ 8612 /*! @{ */ 8613 8614 #define ROM_ENTRY_ENTRY_MASK (0xFFFFFFFFU) 8615 #define ROM_ENTRY_ENTRY_SHIFT (0U) 8616 /*! ENTRY - ENTRY 8617 */ 8618 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x)) << ROM_ENTRY_ENTRY_SHIFT)) & ROM_ENTRY_ENTRY_MASK) 8619 /*! @} */ 8620 8621 /* The count of ROM_ENTRY */ 8622 #define ROM_ENTRY_COUNT (3U) 8623 8624 /*! @name TABLEMARK - End of Table Marker Register */ 8625 /*! @{ */ 8626 8627 #define ROM_TABLEMARK_MARK_MASK (0xFFFFFFFFU) 8628 #define ROM_TABLEMARK_MARK_SHIFT (0U) 8629 /*! MARK - MARK 8630 */ 8631 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x)) << ROM_TABLEMARK_MARK_SHIFT)) & ROM_TABLEMARK_MARK_MASK) 8632 /*! @} */ 8633 8634 /*! @name SYSACCESS - System Access Register */ 8635 /*! @{ */ 8636 8637 #define ROM_SYSACCESS_SYSACCESS_MASK (0xFFFFFFFFU) 8638 #define ROM_SYSACCESS_SYSACCESS_SHIFT (0U) 8639 /*! SYSACCESS - SYSACCESS 8640 */ 8641 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x)) << ROM_SYSACCESS_SYSACCESS_SHIFT)) & ROM_SYSACCESS_SYSACCESS_MASK) 8642 /*! @} */ 8643 8644 /*! @name PERIPHID4 - Peripheral ID Register */ 8645 /*! @{ */ 8646 8647 #define ROM_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) 8648 #define ROM_PERIPHID4_PERIPHID_SHIFT (0U) 8649 /*! PERIPHID - PERIPHID 8650 */ 8651 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID4_PERIPHID_SHIFT)) & ROM_PERIPHID4_PERIPHID_MASK) 8652 /*! @} */ 8653 8654 /*! @name PERIPHID5 - Peripheral ID Register */ 8655 /*! @{ */ 8656 8657 #define ROM_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) 8658 #define ROM_PERIPHID5_PERIPHID_SHIFT (0U) 8659 /*! PERIPHID - PERIPHID 8660 */ 8661 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID5_PERIPHID_SHIFT)) & ROM_PERIPHID5_PERIPHID_MASK) 8662 /*! @} */ 8663 8664 /*! @name PERIPHID6 - Peripheral ID Register */ 8665 /*! @{ */ 8666 8667 #define ROM_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) 8668 #define ROM_PERIPHID6_PERIPHID_SHIFT (0U) 8669 /*! PERIPHID - PERIPHID 8670 */ 8671 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID6_PERIPHID_SHIFT)) & ROM_PERIPHID6_PERIPHID_MASK) 8672 /*! @} */ 8673 8674 /*! @name PERIPHID7 - Peripheral ID Register */ 8675 /*! @{ */ 8676 8677 #define ROM_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) 8678 #define ROM_PERIPHID7_PERIPHID_SHIFT (0U) 8679 /*! PERIPHID - PERIPHID 8680 */ 8681 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID7_PERIPHID_SHIFT)) & ROM_PERIPHID7_PERIPHID_MASK) 8682 /*! @} */ 8683 8684 /*! @name PERIPHID0 - Peripheral ID Register */ 8685 /*! @{ */ 8686 8687 #define ROM_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) 8688 #define ROM_PERIPHID0_PERIPHID_SHIFT (0U) 8689 /*! PERIPHID - PERIPHID 8690 */ 8691 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID0_PERIPHID_SHIFT)) & ROM_PERIPHID0_PERIPHID_MASK) 8692 /*! @} */ 8693 8694 /*! @name PERIPHID1 - Peripheral ID Register */ 8695 /*! @{ */ 8696 8697 #define ROM_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) 8698 #define ROM_PERIPHID1_PERIPHID_SHIFT (0U) 8699 /*! PERIPHID - PERIPHID 8700 */ 8701 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID1_PERIPHID_SHIFT)) & ROM_PERIPHID1_PERIPHID_MASK) 8702 /*! @} */ 8703 8704 /*! @name PERIPHID2 - Peripheral ID Register */ 8705 /*! @{ */ 8706 8707 #define ROM_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) 8708 #define ROM_PERIPHID2_PERIPHID_SHIFT (0U) 8709 /*! PERIPHID - PERIPHID 8710 */ 8711 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID2_PERIPHID_SHIFT)) & ROM_PERIPHID2_PERIPHID_MASK) 8712 /*! @} */ 8713 8714 /*! @name PERIPHID3 - Peripheral ID Register */ 8715 /*! @{ */ 8716 8717 #define ROM_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) 8718 #define ROM_PERIPHID3_PERIPHID_SHIFT (0U) 8719 /*! PERIPHID - PERIPHID 8720 */ 8721 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID3_PERIPHID_SHIFT)) & ROM_PERIPHID3_PERIPHID_MASK) 8722 /*! @} */ 8723 8724 /*! @name COMPID - Component ID Register */ 8725 /*! @{ */ 8726 8727 #define ROM_COMPID_COMPID_MASK (0xFFFFFFFFU) 8728 #define ROM_COMPID_COMPID_SHIFT (0U) 8729 /*! COMPID - Component ID 8730 */ 8731 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << ROM_COMPID_COMPID_SHIFT)) & ROM_COMPID_COMPID_MASK) 8732 /*! @} */ 8733 8734 /* The count of ROM_COMPID */ 8735 #define ROM_COMPID_COUNT (4U) 8736 8737 8738 /*! 8739 * @} 8740 */ /* end of group ROM_Register_Masks */ 8741 8742 8743 /* ROM - Peripheral instance base addresses */ 8744 /** Peripheral ROM base address */ 8745 #define ROM_BASE (0xF0002000u) 8746 /** Peripheral ROM base pointer */ 8747 #define ROM ((ROM_Type *)ROM_BASE) 8748 /** Array initializer of ROM peripheral base addresses */ 8749 #define ROM_BASE_ADDRS { ROM_BASE } 8750 /** Array initializer of ROM peripheral base pointers */ 8751 #define ROM_BASE_PTRS { ROM } 8752 8753 /*! 8754 * @} 8755 */ /* end of group ROM_Peripheral_Access_Layer */ 8756 8757 8758 /* ---------------------------------------------------------------------------- 8759 -- RTC Peripheral Access Layer 8760 ---------------------------------------------------------------------------- */ 8761 8762 /*! 8763 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer 8764 * @{ 8765 */ 8766 8767 /** RTC - Register Layout Typedef */ 8768 typedef struct { 8769 __IO uint16_t YEARMON; /**< RTC Year and Month Counters Register, offset: 0x0 */ 8770 __IO uint16_t DAYS; /**< RTC Days and Day-of-Week Counters Register, offset: 0x2 */ 8771 __IO uint16_t HOURMIN; /**< RTC Hours and Minutes Counters Register, offset: 0x4 */ 8772 __IO uint16_t SECONDS; /**< RTC Seconds Counters Register, offset: 0x6 */ 8773 __IO uint16_t ALM_YEARMON; /**< RTC Year and Months Alarm Register, offset: 0x8 */ 8774 __IO uint16_t ALM_DAYS; /**< RTC Days Alarm Register, offset: 0xA */ 8775 __IO uint16_t ALM_HOURMIN; /**< RTC Hours and Minutes Alarm Register, offset: 0xC */ 8776 __IO uint16_t ALM_SECONDS; /**< RTC Seconds Alarm Register, offset: 0xE */ 8777 __IO uint16_t CTRL; /**< RTC Control Register, offset: 0x10 */ 8778 __IO uint16_t STATUS; /**< RTC Status Register, offset: 0x12 */ 8779 __IO uint16_t ISR; /**< RTC Interrupt Status Register, offset: 0x14 */ 8780 __IO uint16_t IER; /**< RTC Interrupt Enable Register, offset: 0x16 */ 8781 uint8_t RESERVED_0[8]; 8782 __IO uint16_t GP_DATA_REG; /**< RTC General Purpose Data Register, offset: 0x20 */ 8783 __IO uint16_t DST_HOUR; /**< RTC Daylight Saving Hour Register, offset: 0x22 */ 8784 __IO uint16_t DST_MONTH; /**< RTC Daylight Saving Month Register, offset: 0x24 */ 8785 __IO uint16_t DST_DAY; /**< RTC Daylight Saving Day Register, offset: 0x26 */ 8786 __IO uint16_t COMPEN; /**< RTC Compensation Register, offset: 0x28 */ 8787 uint8_t RESERVED_1[8]; 8788 __IO uint16_t TAMPER_SCR; /**< RTC Tamper Status and Control Register, offset: 0x32 */ 8789 __IO uint16_t FILTER01_CFG; /**< RTC Tamper 0 1 Filter Configuration Register, offset: 0x34 */ 8790 __IO uint16_t FILTER2_CFG; /**< RTC Tamper 2 Filter Configuration Register, offset: 0x36 */ 8791 uint8_t RESERVED_2[10]; 8792 __IO uint16_t CTRL2; /**< RTC Control 2 Register, offset: 0x42 */ 8793 } RTC_Type; 8794 8795 /* ---------------------------------------------------------------------------- 8796 -- RTC Register Masks 8797 ---------------------------------------------------------------------------- */ 8798 8799 /*! 8800 * @addtogroup RTC_Register_Masks RTC Register Masks 8801 * @{ 8802 */ 8803 8804 /*! @name YEARMON - RTC Year and Month Counters Register */ 8805 /*! @{ */ 8806 8807 #define RTC_YEARMON_MON_CNT_MASK (0xFU) 8808 #define RTC_YEARMON_MON_CNT_SHIFT (0U) 8809 /*! MON_CNT 8810 * 0b0000..Illegal Value 8811 * 0b0001..January 8812 * 0b0010..February 8813 * 0b0011..March 8814 * 0b0100..April 8815 * 0b0101..May 8816 * 0b0110..June 8817 * 0b0111..July 8818 * 0b1000..August 8819 * 0b1001..September 8820 * 0b0010..October 8821 * 0b0011..November 8822 * 0b1100..December 8823 * 0b1101..Illegal Value 8824 * 0b1110..Illegal Value 8825 * 0b1111..Illegal Value 8826 */ 8827 #define RTC_YEARMON_MON_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_YEARMON_MON_CNT_SHIFT)) & RTC_YEARMON_MON_CNT_MASK) 8828 8829 #define RTC_YEARMON_YROFST_MASK (0xFF00U) 8830 #define RTC_YEARMON_YROFST_SHIFT (8U) 8831 /*! YROFST - Year Offset Count Value 8832 */ 8833 #define RTC_YEARMON_YROFST(x) (((uint16_t)(((uint16_t)(x)) << RTC_YEARMON_YROFST_SHIFT)) & RTC_YEARMON_YROFST_MASK) 8834 /*! @} */ 8835 8836 /*! @name DAYS - RTC Days and Day-of-Week Counters Register */ 8837 /*! @{ */ 8838 8839 #define RTC_DAYS_DAY_CNT_MASK (0x1FU) 8840 #define RTC_DAYS_DAY_CNT_SHIFT (0U) 8841 /*! DAY_CNT - Days Counter Value. 8842 */ 8843 #define RTC_DAYS_DAY_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_DAYS_DAY_CNT_SHIFT)) & RTC_DAYS_DAY_CNT_MASK) 8844 8845 #define RTC_DAYS_DOW_MASK (0x700U) 8846 #define RTC_DAYS_DOW_SHIFT (8U) 8847 /*! DOW - Day of Week Counter Value. 8848 * 0b000..Sunday 8849 * 0b001..Monday 8850 * 0b010..Tuesday 8851 * 0b011..Wednesday 8852 * 0b100..Thrusday 8853 * 0b101..Friday 8854 * 0b110..Saturday 8855 * 0b111..Reserved 8856 */ 8857 #define RTC_DAYS_DOW(x) (((uint16_t)(((uint16_t)(x)) << RTC_DAYS_DOW_SHIFT)) & RTC_DAYS_DOW_MASK) 8858 /*! @} */ 8859 8860 /*! @name HOURMIN - RTC Hours and Minutes Counters Register */ 8861 /*! @{ */ 8862 8863 #define RTC_HOURMIN_MIN_CNT_MASK (0x3FU) 8864 #define RTC_HOURMIN_MIN_CNT_SHIFT (0U) 8865 /*! MIN_CNT - Minutes Counter Value. 8866 */ 8867 #define RTC_HOURMIN_MIN_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_HOURMIN_MIN_CNT_SHIFT)) & RTC_HOURMIN_MIN_CNT_MASK) 8868 8869 #define RTC_HOURMIN_HOUR_CNT_MASK (0x1F00U) 8870 #define RTC_HOURMIN_HOUR_CNT_SHIFT (8U) 8871 /*! HOUR_CNT - Hours Counter Value. 8872 */ 8873 #define RTC_HOURMIN_HOUR_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_HOURMIN_HOUR_CNT_SHIFT)) & RTC_HOURMIN_HOUR_CNT_MASK) 8874 /*! @} */ 8875 8876 /*! @name SECONDS - RTC Seconds Counters Register */ 8877 /*! @{ */ 8878 8879 #define RTC_SECONDS_SEC_CNT_MASK (0x3FU) 8880 #define RTC_SECONDS_SEC_CNT_SHIFT (0U) 8881 /*! SEC_CNT - Seconds Counter Value. 8882 */ 8883 #define RTC_SECONDS_SEC_CNT(x) (((uint16_t)(((uint16_t)(x)) << RTC_SECONDS_SEC_CNT_SHIFT)) & RTC_SECONDS_SEC_CNT_MASK) 8884 /*! @} */ 8885 8886 /*! @name ALM_YEARMON - RTC Year and Months Alarm Register */ 8887 /*! @{ */ 8888 8889 #define RTC_ALM_YEARMON_ALM_MON_MASK (0xFU) 8890 #define RTC_ALM_YEARMON_ALM_MON_SHIFT (0U) 8891 /*! ALM_MON - Months Value for Alarm. 8892 */ 8893 #define RTC_ALM_YEARMON_ALM_MON(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_YEARMON_ALM_MON_SHIFT)) & RTC_ALM_YEARMON_ALM_MON_MASK) 8894 8895 #define RTC_ALM_YEARMON_ALM_YEAR_MASK (0xFF00U) 8896 #define RTC_ALM_YEARMON_ALM_YEAR_SHIFT (8U) 8897 /*! ALM_YEAR - Year Value for Alarm. 8898 */ 8899 #define RTC_ALM_YEARMON_ALM_YEAR(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_YEARMON_ALM_YEAR_SHIFT)) & RTC_ALM_YEARMON_ALM_YEAR_MASK) 8900 /*! @} */ 8901 8902 /*! @name ALM_DAYS - RTC Days Alarm Register */ 8903 /*! @{ */ 8904 8905 #define RTC_ALM_DAYS_ALM_DAY_MASK (0x1FU) 8906 #define RTC_ALM_DAYS_ALM_DAY_SHIFT (0U) 8907 /*! ALM_DAY - Days Value for Alarm. 8908 */ 8909 #define RTC_ALM_DAYS_ALM_DAY(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_DAYS_ALM_DAY_SHIFT)) & RTC_ALM_DAYS_ALM_DAY_MASK) 8910 /*! @} */ 8911 8912 /*! @name ALM_HOURMIN - RTC Hours and Minutes Alarm Register */ 8913 /*! @{ */ 8914 8915 #define RTC_ALM_HOURMIN_ALM_MIN_MASK (0x3FU) 8916 #define RTC_ALM_HOURMIN_ALM_MIN_SHIFT (0U) 8917 /*! ALM_MIN - Minutes Value for Alarm. 8918 */ 8919 #define RTC_ALM_HOURMIN_ALM_MIN(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_HOURMIN_ALM_MIN_SHIFT)) & RTC_ALM_HOURMIN_ALM_MIN_MASK) 8920 8921 #define RTC_ALM_HOURMIN_ALM_HOUR_MASK (0x1F00U) 8922 #define RTC_ALM_HOURMIN_ALM_HOUR_SHIFT (8U) 8923 /*! ALM_HOUR - Hours Value for Alarm. 8924 */ 8925 #define RTC_ALM_HOURMIN_ALM_HOUR(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_HOURMIN_ALM_HOUR_SHIFT)) & RTC_ALM_HOURMIN_ALM_HOUR_MASK) 8926 /*! @} */ 8927 8928 /*! @name ALM_SECONDS - RTC Seconds Alarm Register */ 8929 /*! @{ */ 8930 8931 #define RTC_ALM_SECONDS_ALM_SEC_MASK (0x3FU) 8932 #define RTC_ALM_SECONDS_ALM_SEC_SHIFT (0U) 8933 #define RTC_ALM_SECONDS_ALM_SEC(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_SECONDS_ALM_SEC_SHIFT)) & RTC_ALM_SECONDS_ALM_SEC_MASK) 8934 8935 #define RTC_ALM_SECONDS_DEC_SEC_MASK (0x100U) 8936 #define RTC_ALM_SECONDS_DEC_SEC_SHIFT (8U) 8937 /*! DEC_SEC - Decrement Seconds Counter by 1. 8938 */ 8939 #define RTC_ALM_SECONDS_DEC_SEC(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_SECONDS_DEC_SEC_SHIFT)) & RTC_ALM_SECONDS_DEC_SEC_MASK) 8940 8941 #define RTC_ALM_SECONDS_INC_SEC_MASK (0x200U) 8942 #define RTC_ALM_SECONDS_INC_SEC_SHIFT (9U) 8943 /*! INC_SEC - Increment Seconds Counter by 1. 8944 */ 8945 #define RTC_ALM_SECONDS_INC_SEC(x) (((uint16_t)(((uint16_t)(x)) << RTC_ALM_SECONDS_INC_SEC_SHIFT)) & RTC_ALM_SECONDS_INC_SEC_MASK) 8946 /*! @} */ 8947 8948 /*! @name CTRL - RTC Control Register */ 8949 /*! @{ */ 8950 8951 #define RTC_CTRL_FINEEN_MASK (0x1U) 8952 #define RTC_CTRL_FINEEN_SHIFT (0U) 8953 /*! FINEEN - Fine compensation enable bit 8954 * 0b1..Fine compensation is enabled. 8955 * 0b0..Fine compensation is disabled 8956 */ 8957 #define RTC_CTRL_FINEEN(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_FINEEN_SHIFT)) & RTC_CTRL_FINEEN_MASK) 8958 8959 #define RTC_CTRL_COMP_EN_MASK (0x2U) 8960 #define RTC_CTRL_COMP_EN_SHIFT (1U) 8961 #define RTC_CTRL_COMP_EN(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_COMP_EN_SHIFT)) & RTC_CTRL_COMP_EN_MASK) 8962 8963 #define RTC_CTRL_ALM_MATCH_MASK (0xCU) 8964 #define RTC_CTRL_ALM_MATCH_SHIFT (2U) 8965 /*! ALM_MATCH - Alarm Match bits. 8966 * 0b00..Only Seconds, Minutes, and Hours matched. 8967 * 0b01..Only Seconds, Minutes, Hours, and Days matched. 8968 * 0b10..Only Seconds, Minutes, Hours, Days, and Months matched. 8969 * 0b11..Only Seconds, Minutes, Hours, Days, Months, and Year (offset) matched. 8970 */ 8971 #define RTC_CTRL_ALM_MATCH(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_ALM_MATCH_SHIFT)) & RTC_CTRL_ALM_MATCH_MASK) 8972 8973 #define RTC_CTRL_TIMER_STB_MASK_MASK (0x10U) 8974 #define RTC_CTRL_TIMER_STB_MASK_SHIFT (4U) 8975 /*! TIMER_STB_MASK - Sampling timer clocks mask 8976 * 0b1..Sampling clocks are gated in standby mode 8977 * 0b0..Sampling clocks are not gated when in standby mode 8978 */ 8979 #define RTC_CTRL_TIMER_STB_MASK(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_TIMER_STB_MASK_SHIFT)) & RTC_CTRL_TIMER_STB_MASK_MASK) 8980 8981 #define RTC_CTRL_DST_EN_MASK (0x40U) 8982 #define RTC_CTRL_DST_EN_SHIFT (6U) 8983 /*! DST_EN - Daylight Saving Enable. 8984 * 0b0..Disabled. Daylight saving changes are not applied. Daylight saving registers can be modified. 8985 * 0b1..Enabled. Daylight saving changes are applied. 8986 */ 8987 #define RTC_CTRL_DST_EN(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_DST_EN_SHIFT)) & RTC_CTRL_DST_EN_MASK) 8988 8989 #define RTC_CTRL_SWR_MASK (0x100U) 8990 #define RTC_CTRL_SWR_SHIFT (8U) 8991 /*! SWR - Software Reset bit. 8992 * 0b0..Software Reset cleared. 8993 * 0b1..Software Reset asserted. 8994 */ 8995 #define RTC_CTRL_SWR(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_SWR_SHIFT)) & RTC_CTRL_SWR_MASK) 8996 8997 #define RTC_CTRL_CLKOUT_MASK (0x6000U) 8998 #define RTC_CTRL_CLKOUT_SHIFT (13U) 8999 /*! CLKOUT - RTC Clock Output Selection. 9000 * 0b00..No Output Clock 9001 * 0b01..Fine 1 Hz Clock 9002 * 0b10..32.768 kHz Clock 9003 * 0b11..Coarse 1 Hz Clock 9004 */ 9005 #define RTC_CTRL_CLKOUT(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL_CLKOUT_SHIFT)) & RTC_CTRL_CLKOUT_MASK) 9006 /*! @} */ 9007 9008 /*! @name STATUS - RTC Status Register */ 9009 /*! @{ */ 9010 9011 #define RTC_STATUS_INVAL_BIT_MASK (0x1U) 9012 #define RTC_STATUS_INVAL_BIT_SHIFT (0U) 9013 /*! INVAL_BIT - Invalidate CPU read/write access bit. 9014 * 0b0..Time /Date Counters can be read/written. Time /Date is valid. 9015 * 0b1..Time /Date Counter values are changing or Time /Date is invalid and cannot be read or written. 9016 */ 9017 #define RTC_STATUS_INVAL_BIT(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_INVAL_BIT_SHIFT)) & RTC_STATUS_INVAL_BIT_MASK) 9018 9019 #define RTC_STATUS_WRITE_PROT_EN_MASK (0x2U) 9020 #define RTC_STATUS_WRITE_PROT_EN_SHIFT (1U) 9021 /*! WRITE_PROT_EN - Write Protect Enable status bit. 9022 * 0b0..Registers are unlocked and can be accessed. 9023 * 0b1..Registers are locked and in read-only mode. 9024 */ 9025 #define RTC_STATUS_WRITE_PROT_EN(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_WRITE_PROT_EN_SHIFT)) & RTC_STATUS_WRITE_PROT_EN_MASK) 9026 9027 #define RTC_STATUS_CPU_LOW_VOLT_MASK (0x4U) 9028 #define RTC_STATUS_CPU_LOW_VOLT_SHIFT (2U) 9029 /*! CPU_LOW_VOLT - CPU Low Voltage Warning status bit. 9030 * 0b0..CPU in Normal Operating Voltage. 9031 * 0b1..CPU Voltage is below Normal Operating Voltage. RTC Registers in read-only mode. 9032 */ 9033 #define RTC_STATUS_CPU_LOW_VOLT(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_CPU_LOW_VOLT_SHIFT)) & RTC_STATUS_CPU_LOW_VOLT_MASK) 9034 9035 #define RTC_STATUS_RST_SRC_MASK (0x8U) 9036 #define RTC_STATUS_RST_SRC_SHIFT (3U) 9037 /*! RST_SRC - Reset Source bit. 9038 * 0b0..Part was reset due to Standby Mode Exit (that is when VDD is powered up and VBAT was not powered down at all). 9039 * 0b1..Part was reset due to Power-On Reset (that is Power On Reset when both VBAT and VDD are powered up). 9040 */ 9041 #define RTC_STATUS_RST_SRC(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_RST_SRC_SHIFT)) & RTC_STATUS_RST_SRC_MASK) 9042 9043 #define RTC_STATUS_CMP_INT_MASK (0x20U) 9044 #define RTC_STATUS_CMP_INT_SHIFT (5U) 9045 /*! CMP_INT - Compensation Interval bit. 9046 */ 9047 #define RTC_STATUS_CMP_INT(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_CMP_INT_SHIFT)) & RTC_STATUS_CMP_INT_MASK) 9048 9049 #define RTC_STATUS_WE_MASK (0xC0U) 9050 #define RTC_STATUS_WE_SHIFT (6U) 9051 /*! WE - Write Enable bits. 9052 * 0b10..Enable Write Protection - Registers are locked. 9053 */ 9054 #define RTC_STATUS_WE(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_WE_SHIFT)) & RTC_STATUS_WE_MASK) 9055 9056 #define RTC_STATUS_BUS_ERR_MASK (0x100U) 9057 #define RTC_STATUS_BUS_ERR_SHIFT (8U) 9058 /*! BUS_ERR - Bus Error bit. 9059 * 0b0..Read and Write accesses are normal. 9060 * 0b1..Read or Write accesses occurred when INVAL_BIT was asserted. 9061 */ 9062 #define RTC_STATUS_BUS_ERR(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_BUS_ERR_SHIFT)) & RTC_STATUS_BUS_ERR_MASK) 9063 9064 #define RTC_STATUS_CMP_DONE_MASK (0x800U) 9065 #define RTC_STATUS_CMP_DONE_SHIFT (11U) 9066 /*! CMP_DONE - Compensation Done bit. 9067 * 0b0..Compensation busy or not enabled. 9068 * 0b1..Compensation completed. 9069 */ 9070 #define RTC_STATUS_CMP_DONE(x) (((uint16_t)(((uint16_t)(x)) << RTC_STATUS_CMP_DONE_SHIFT)) & RTC_STATUS_CMP_DONE_MASK) 9071 /*! @} */ 9072 9073 /*! @name ISR - RTC Interrupt Status Register */ 9074 /*! @{ */ 9075 9076 #define RTC_ISR_TAMPER_IS_MASK (0x1U) 9077 #define RTC_ISR_TAMPER_IS_SHIFT (0U) 9078 /*! TAMPER_IS - Tamper Interrupt Status bit. 9079 * 0b0..Interrupt is de-asserted. 9080 * 0b1..Interrupt is asserted (Default on reset) . 9081 */ 9082 #define RTC_ISR_TAMPER_IS(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_TAMPER_IS_SHIFT)) & RTC_ISR_TAMPER_IS_MASK) 9083 9084 #define RTC_ISR_ALM_IS_MASK (0x4U) 9085 #define RTC_ISR_ALM_IS_SHIFT (2U) 9086 /*! ALM_IS - Alarm Interrupt Status bit. 9087 * 0b0..Interrupt is de-asserted. 9088 * 0b1..Interrupt is asserted. 9089 */ 9090 #define RTC_ISR_ALM_IS(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_ALM_IS_SHIFT)) & RTC_ISR_ALM_IS_MASK) 9091 9092 #define RTC_ISR_DAY_IS_MASK (0x8U) 9093 #define RTC_ISR_DAY_IS_SHIFT (3U) 9094 /*! DAY_IS - Days Interrupt Status bit. 9095 * 0b0..Interrupt is de-asserted. 9096 * 0b1..Interrupt is asserted. 9097 */ 9098 #define RTC_ISR_DAY_IS(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_DAY_IS_SHIFT)) & RTC_ISR_DAY_IS_MASK) 9099 9100 #define RTC_ISR_HOUR_IS_MASK (0x10U) 9101 #define RTC_ISR_HOUR_IS_SHIFT (4U) 9102 /*! HOUR_IS - Hours Interrupt Status bit. 9103 * 0b0..Interrupt is de-asserted. 9104 * 0b1..Interrupt is asserted. 9105 */ 9106 #define RTC_ISR_HOUR_IS(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_HOUR_IS_SHIFT)) & RTC_ISR_HOUR_IS_MASK) 9107 9108 #define RTC_ISR_MIN_IS_MASK (0x20U) 9109 #define RTC_ISR_MIN_IS_SHIFT (5U) 9110 /*! MIN_IS - Minutes Interrupt Status bit. 9111 * 0b0..Interrupt is de-asserted. 9112 * 0b1..Interrupt is asserted. 9113 */ 9114 #define RTC_ISR_MIN_IS(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_MIN_IS_SHIFT)) & RTC_ISR_MIN_IS_MASK) 9115 9116 #define RTC_ISR_IS_1HZ_MASK (0x40U) 9117 #define RTC_ISR_IS_1HZ_SHIFT (6U) 9118 /*! IS_1HZ - 1 Hz Interval Interrupt Status bit. 9119 * 0b0..Interrupt is de-asserted. 9120 * 0b1..Interrupt is asserted. 9121 */ 9122 #define RTC_ISR_IS_1HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_1HZ_SHIFT)) & RTC_ISR_IS_1HZ_MASK) 9123 9124 #define RTC_ISR_IS_2HZ_MASK (0x80U) 9125 #define RTC_ISR_IS_2HZ_SHIFT (7U) 9126 /*! IS_2HZ - 2 Hz Interval Interrupt Status bit. 9127 * 0b0..Interrupt is de-asserted. 9128 * 0b1..Interrupt is asserted. 9129 */ 9130 #define RTC_ISR_IS_2HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_2HZ_SHIFT)) & RTC_ISR_IS_2HZ_MASK) 9131 9132 #define RTC_ISR_IS_4HZ_MASK (0x100U) 9133 #define RTC_ISR_IS_4HZ_SHIFT (8U) 9134 /*! IS_4HZ - 4 Hz Interval Interrupt Status bit. 9135 * 0b0..Interrupt is de-asserted. 9136 * 0b1..Interrupt is asserted. 9137 */ 9138 #define RTC_ISR_IS_4HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_4HZ_SHIFT)) & RTC_ISR_IS_4HZ_MASK) 9139 9140 #define RTC_ISR_IS_8HZ_MASK (0x200U) 9141 #define RTC_ISR_IS_8HZ_SHIFT (9U) 9142 /*! IS_8HZ - 8 Hz Interval Interrupt Status bit. 9143 * 0b0..Interrupt is de-asserted. 9144 * 0b1..Interrupt is asserted. 9145 */ 9146 #define RTC_ISR_IS_8HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_8HZ_SHIFT)) & RTC_ISR_IS_8HZ_MASK) 9147 9148 #define RTC_ISR_IS_16HZ_MASK (0x400U) 9149 #define RTC_ISR_IS_16HZ_SHIFT (10U) 9150 /*! IS_16HZ - 16 Hz Interval Interrupt Status bit. 9151 * 0b0..Interrupt is de-asserted. 9152 * 0b1..Interrupt is asserted. 9153 */ 9154 #define RTC_ISR_IS_16HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_16HZ_SHIFT)) & RTC_ISR_IS_16HZ_MASK) 9155 9156 #define RTC_ISR_IS_32HZ_MASK (0x800U) 9157 #define RTC_ISR_IS_32HZ_SHIFT (11U) 9158 /*! IS_32HZ - 32 Hz Interval Interrupt Status bit. 9159 * 0b0..Interrupt is de-asserted. 9160 * 0b1..Interrupt is asserted. 9161 */ 9162 #define RTC_ISR_IS_32HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_32HZ_SHIFT)) & RTC_ISR_IS_32HZ_MASK) 9163 9164 #define RTC_ISR_IS_64HZ_MASK (0x1000U) 9165 #define RTC_ISR_IS_64HZ_SHIFT (12U) 9166 /*! IS_64HZ - 64 Hz Interval Interrupt Status bit. 9167 * 0b0..Interrupt is de-asserted. 9168 * 0b1..Interrupt is asserted. 9169 */ 9170 #define RTC_ISR_IS_64HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_64HZ_SHIFT)) & RTC_ISR_IS_64HZ_MASK) 9171 9172 #define RTC_ISR_IS_128HZ_MASK (0x2000U) 9173 #define RTC_ISR_IS_128HZ_SHIFT (13U) 9174 /*! IS_128HZ - 128 Hz Interval Interrupt Status bit. 9175 * 0b0..Interrupt is de-asserted. 9176 * 0b1..Interrupt is asserted. 9177 */ 9178 #define RTC_ISR_IS_128HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_128HZ_SHIFT)) & RTC_ISR_IS_128HZ_MASK) 9179 9180 #define RTC_ISR_IS_256HZ_MASK (0x4000U) 9181 #define RTC_ISR_IS_256HZ_SHIFT (14U) 9182 /*! IS_256HZ - 256 Hz Interval Interrupt Status bit. 9183 * 0b0..Interrupt is de-asserted. 9184 * 0b1..Interrupt is asserted. 9185 */ 9186 #define RTC_ISR_IS_256HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_256HZ_SHIFT)) & RTC_ISR_IS_256HZ_MASK) 9187 9188 #define RTC_ISR_IS_512HZ_MASK (0x8000U) 9189 #define RTC_ISR_IS_512HZ_SHIFT (15U) 9190 /*! IS_512HZ - 512 Hz Interval Interrupt Status bit. 9191 * 0b0..Interrupt is de-asserted. 9192 * 0b1..Interrupt is asserted. 9193 */ 9194 #define RTC_ISR_IS_512HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_ISR_IS_512HZ_SHIFT)) & RTC_ISR_IS_512HZ_MASK) 9195 /*! @} */ 9196 9197 /*! @name IER - RTC Interrupt Enable Register */ 9198 /*! @{ */ 9199 9200 #define RTC_IER_TAMPER_IE_MASK (0x1U) 9201 #define RTC_IER_TAMPER_IE_SHIFT (0U) 9202 /*! TAMPER_IE - Tamper Interrupt Enable bit. 9203 * 0b0..Interrupt is disabled. 9204 * 0b1..Interrupt is enabled (Default on reset). 9205 */ 9206 #define RTC_IER_TAMPER_IE(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_TAMPER_IE_SHIFT)) & RTC_IER_TAMPER_IE_MASK) 9207 9208 #define RTC_IER_ALM_IE_MASK (0x4U) 9209 #define RTC_IER_ALM_IE_SHIFT (2U) 9210 /*! ALM_IE - Alarm Interrupt Enable bit. 9211 * 0b0..Interrupt is disabled. 9212 * 0b1..Interrupt is enabled. 9213 */ 9214 #define RTC_IER_ALM_IE(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_ALM_IE_SHIFT)) & RTC_IER_ALM_IE_MASK) 9215 9216 #define RTC_IER_DAY_IE_MASK (0x8U) 9217 #define RTC_IER_DAY_IE_SHIFT (3U) 9218 /*! DAY_IE - Days Interrupt Enable bit. 9219 * 0b0..Interrupt is disabled. 9220 * 0b1..Interrupt is enabled. 9221 */ 9222 #define RTC_IER_DAY_IE(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_DAY_IE_SHIFT)) & RTC_IER_DAY_IE_MASK) 9223 9224 #define RTC_IER_HOUR_IE_MASK (0x10U) 9225 #define RTC_IER_HOUR_IE_SHIFT (4U) 9226 /*! HOUR_IE - Hours Interrupt Enable bit. 9227 * 0b0..Interrupt is disabled. 9228 * 0b1..Interrupt is enabled. 9229 */ 9230 #define RTC_IER_HOUR_IE(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_HOUR_IE_SHIFT)) & RTC_IER_HOUR_IE_MASK) 9231 9232 #define RTC_IER_MIN_IE_MASK (0x20U) 9233 #define RTC_IER_MIN_IE_SHIFT (5U) 9234 /*! MIN_IE - Minutes Interrupt Enable bit. 9235 * 0b0..Interrupt is disabled. 9236 * 0b1..Interrupt is enabled. 9237 */ 9238 #define RTC_IER_MIN_IE(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_MIN_IE_SHIFT)) & RTC_IER_MIN_IE_MASK) 9239 9240 #define RTC_IER_IE_1HZ_MASK (0x40U) 9241 #define RTC_IER_IE_1HZ_SHIFT (6U) 9242 /*! IE_1HZ - 1 Hz Interval Interrupt Enable bit. 9243 * 0b0..Interrupt is disabled. 9244 * 0b1..Interrupt is enabled. 9245 */ 9246 #define RTC_IER_IE_1HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_1HZ_SHIFT)) & RTC_IER_IE_1HZ_MASK) 9247 9248 #define RTC_IER_IE_2HZ_MASK (0x80U) 9249 #define RTC_IER_IE_2HZ_SHIFT (7U) 9250 /*! IE_2HZ - 2 Hz Interval Interrupt Enable bit. 9251 * 0b0..Interrupt is disabled. 9252 * 0b1..Interrupt is enabled. 9253 */ 9254 #define RTC_IER_IE_2HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_2HZ_SHIFT)) & RTC_IER_IE_2HZ_MASK) 9255 9256 #define RTC_IER_IE_4HZ_MASK (0x100U) 9257 #define RTC_IER_IE_4HZ_SHIFT (8U) 9258 /*! IE_4HZ - 4 Hz Interval Interrupt Enable bit. 9259 * 0b0..Interrupt is disabled. 9260 * 0b1..Interrupt is enabled. 9261 */ 9262 #define RTC_IER_IE_4HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_4HZ_SHIFT)) & RTC_IER_IE_4HZ_MASK) 9263 9264 #define RTC_IER_IE_8HZ_MASK (0x200U) 9265 #define RTC_IER_IE_8HZ_SHIFT (9U) 9266 /*! IE_8HZ - 8 Hz Interval Interrupt Enable bit. 9267 * 0b0..Interrupt is disabled. 9268 * 0b1..Interrupt is enabled. 9269 */ 9270 #define RTC_IER_IE_8HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_8HZ_SHIFT)) & RTC_IER_IE_8HZ_MASK) 9271 9272 #define RTC_IER_IE_16HZ_MASK (0x400U) 9273 #define RTC_IER_IE_16HZ_SHIFT (10U) 9274 /*! IE_16HZ - 16 Hz Interval Interrupt Enable bit. 9275 * 0b0..Interrupt is disabled. 9276 * 0b1..Interrupt is enabled. 9277 */ 9278 #define RTC_IER_IE_16HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_16HZ_SHIFT)) & RTC_IER_IE_16HZ_MASK) 9279 9280 #define RTC_IER_IE_32HZ_MASK (0x800U) 9281 #define RTC_IER_IE_32HZ_SHIFT (11U) 9282 /*! IE_32HZ - 32 Hz Interval Interrupt Enable bit. 9283 * 0b0..Interrupt is disabled. 9284 * 0b1..Interrupt is enabled. 9285 */ 9286 #define RTC_IER_IE_32HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_32HZ_SHIFT)) & RTC_IER_IE_32HZ_MASK) 9287 9288 #define RTC_IER_IE_64HZ_MASK (0x1000U) 9289 #define RTC_IER_IE_64HZ_SHIFT (12U) 9290 /*! IE_64HZ - 64 Hz Interval Interrupt Enable bit. 9291 * 0b0..Interrupt is disabled. 9292 * 0b1..Interrupt is enabled. 9293 */ 9294 #define RTC_IER_IE_64HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_64HZ_SHIFT)) & RTC_IER_IE_64HZ_MASK) 9295 9296 #define RTC_IER_IE_128HZ_MASK (0x2000U) 9297 #define RTC_IER_IE_128HZ_SHIFT (13U) 9298 /*! IE_128HZ - 128 Hz Interval Interrupt Enable bit. 9299 * 0b0..Interrupt is disabled. 9300 * 0b1..Interrupt is enabled. 9301 */ 9302 #define RTC_IER_IE_128HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_128HZ_SHIFT)) & RTC_IER_IE_128HZ_MASK) 9303 9304 #define RTC_IER_IE_256HZ_MASK (0x4000U) 9305 #define RTC_IER_IE_256HZ_SHIFT (14U) 9306 /*! IE_256HZ - 256 Hz Interval Interrupt Enable bit. 9307 * 0b0..Interrupt is disabled. 9308 * 0b1..Interrupt is enabled. 9309 */ 9310 #define RTC_IER_IE_256HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_256HZ_SHIFT)) & RTC_IER_IE_256HZ_MASK) 9311 9312 #define RTC_IER_IE_512HZ_MASK (0x8000U) 9313 #define RTC_IER_IE_512HZ_SHIFT (15U) 9314 /*! IE_512HZ - 512 Hz Interval Interrupt Enable bit. 9315 * 0b0..Interrupt is disabled. 9316 * 0b1..Interrupt is enabled. 9317 */ 9318 #define RTC_IER_IE_512HZ(x) (((uint16_t)(((uint16_t)(x)) << RTC_IER_IE_512HZ_SHIFT)) & RTC_IER_IE_512HZ_MASK) 9319 /*! @} */ 9320 9321 /*! @name GP_DATA_REG - RTC General Purpose Data Register */ 9322 /*! @{ */ 9323 9324 #define RTC_GP_DATA_REG_CFG0_MASK (0x1U) 9325 #define RTC_GP_DATA_REG_CFG0_SHIFT (0U) 9326 /*! CFG0 - 32 kHz RTC OSC Control 9327 * 0b0..Enables the oscillator 9328 * 0b1..Disables the oscillator 9329 */ 9330 #define RTC_GP_DATA_REG_CFG0(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG0_SHIFT)) & RTC_GP_DATA_REG_CFG0_MASK) 9331 9332 #define RTC_GP_DATA_REG_CFG1_MASK (0x2U) 9333 #define RTC_GP_DATA_REG_CFG1_SHIFT (1U) 9334 /*! CFG1 - Switched capacitor 2 pF enable 9335 * 0b0..Disables capacitor 9336 * 0b1..Enables capacitor 9337 */ 9338 #define RTC_GP_DATA_REG_CFG1(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG1_SHIFT)) & RTC_GP_DATA_REG_CFG1_MASK) 9339 9340 #define RTC_GP_DATA_REG_CFG2_MASK (0x4U) 9341 #define RTC_GP_DATA_REG_CFG2_SHIFT (2U) 9342 /*! CFG2 - Switched capacitor 4 pF enable 9343 * 0b0..Disables capacitor 9344 * 0b1..Enables capacitor 9345 */ 9346 #define RTC_GP_DATA_REG_CFG2(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG2_SHIFT)) & RTC_GP_DATA_REG_CFG2_MASK) 9347 9348 #define RTC_GP_DATA_REG_CFG3_MASK (0x8U) 9349 #define RTC_GP_DATA_REG_CFG3_SHIFT (3U) 9350 /*! CFG3 - Switched capacitor 8 pF enable 9351 * 0b0..Disables capacitor 9352 * 0b1..Enables capacitor 9353 */ 9354 #define RTC_GP_DATA_REG_CFG3(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG3_SHIFT)) & RTC_GP_DATA_REG_CFG3_MASK) 9355 9356 #define RTC_GP_DATA_REG_CFG4_MASK (0x10U) 9357 #define RTC_GP_DATA_REG_CFG4_SHIFT (4U) 9358 /*! CFG4 - Switched capacitor 16 pF enable 9359 * 0b0..Disables capacitor 9360 * 0b1..Enables capacitor 9361 */ 9362 #define RTC_GP_DATA_REG_CFG4(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG4_SHIFT)) & RTC_GP_DATA_REG_CFG4_MASK) 9363 9364 #define RTC_GP_DATA_REG_CFG7_MASK (0x80U) 9365 #define RTC_GP_DATA_REG_CFG7_SHIFT (7U) 9366 /*! CFG7 - Boot mode override bit 9367 * 0b0..Boot in RUN 9368 * 0b1..Boot in VLPR 9369 */ 9370 #define RTC_GP_DATA_REG_CFG7(x) (((uint16_t)(((uint16_t)(x)) << RTC_GP_DATA_REG_CFG7_SHIFT)) & RTC_GP_DATA_REG_CFG7_MASK) 9371 /*! @} */ 9372 9373 /*! @name DST_HOUR - RTC Daylight Saving Hour Register */ 9374 /*! @{ */ 9375 9376 #define RTC_DST_HOUR_DST_END_HOUR_MASK (0x1FU) 9377 #define RTC_DST_HOUR_DST_END_HOUR_SHIFT (0U) 9378 /*! DST_END_HOUR - Daylight Saving Time (DST) Hours End Value. 9379 */ 9380 #define RTC_DST_HOUR_DST_END_HOUR(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_HOUR_DST_END_HOUR_SHIFT)) & RTC_DST_HOUR_DST_END_HOUR_MASK) 9381 9382 #define RTC_DST_HOUR_DST_START_HOUR_MASK (0x1F00U) 9383 #define RTC_DST_HOUR_DST_START_HOUR_SHIFT (8U) 9384 /*! DST_START_HOUR - Daylight Saving Time (DST) Hours Start Value. 9385 */ 9386 #define RTC_DST_HOUR_DST_START_HOUR(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_HOUR_DST_START_HOUR_SHIFT)) & RTC_DST_HOUR_DST_START_HOUR_MASK) 9387 /*! @} */ 9388 9389 /*! @name DST_MONTH - RTC Daylight Saving Month Register */ 9390 /*! @{ */ 9391 9392 #define RTC_DST_MONTH_DST_END_MONTH_MASK (0xFU) 9393 #define RTC_DST_MONTH_DST_END_MONTH_SHIFT (0U) 9394 /*! DST_END_MONTH - Daylight Saving Time (DST) Month End Value. 9395 */ 9396 #define RTC_DST_MONTH_DST_END_MONTH(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_MONTH_DST_END_MONTH_SHIFT)) & RTC_DST_MONTH_DST_END_MONTH_MASK) 9397 9398 #define RTC_DST_MONTH_DST_START_MONTH_MASK (0xF00U) 9399 #define RTC_DST_MONTH_DST_START_MONTH_SHIFT (8U) 9400 /*! DST_START_MONTH - Daylight Saving Time (DST) Month Start Value. 9401 */ 9402 #define RTC_DST_MONTH_DST_START_MONTH(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_MONTH_DST_START_MONTH_SHIFT)) & RTC_DST_MONTH_DST_START_MONTH_MASK) 9403 /*! @} */ 9404 9405 /*! @name DST_DAY - RTC Daylight Saving Day Register */ 9406 /*! @{ */ 9407 9408 #define RTC_DST_DAY_DST_END_DAY_MASK (0x1FU) 9409 #define RTC_DST_DAY_DST_END_DAY_SHIFT (0U) 9410 /*! DST_END_DAY - Daylight Saving Time (DST) Day End Value. 9411 */ 9412 #define RTC_DST_DAY_DST_END_DAY(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_DAY_DST_END_DAY_SHIFT)) & RTC_DST_DAY_DST_END_DAY_MASK) 9413 9414 #define RTC_DST_DAY_DST_START_DAY_MASK (0x1F00U) 9415 #define RTC_DST_DAY_DST_START_DAY_SHIFT (8U) 9416 /*! DST_START_DAY - Daylight Saving Time (DST) Day Start Value. 9417 */ 9418 #define RTC_DST_DAY_DST_START_DAY(x) (((uint16_t)(((uint16_t)(x)) << RTC_DST_DAY_DST_START_DAY_SHIFT)) & RTC_DST_DAY_DST_START_DAY_MASK) 9419 /*! @} */ 9420 9421 /*! @name COMPEN - RTC Compensation Register */ 9422 /*! @{ */ 9423 9424 #define RTC_COMPEN_COMPEN_VAL_MASK (0xFFFFU) 9425 #define RTC_COMPEN_COMPEN_VAL_SHIFT (0U) 9426 /*! COMPEN_VAL - Compensation Value 9427 */ 9428 #define RTC_COMPEN_COMPEN_VAL(x) (((uint16_t)(((uint16_t)(x)) << RTC_COMPEN_COMPEN_VAL_SHIFT)) & RTC_COMPEN_COMPEN_VAL_MASK) 9429 /*! @} */ 9430 9431 /*! @name TAMPER_SCR - RTC Tamper Status and Control Register */ 9432 /*! @{ */ 9433 9434 #define RTC_TAMPER_SCR_TMPR_EN_MASK (0xFU) 9435 #define RTC_TAMPER_SCR_TMPR_EN_SHIFT (0U) 9436 /*! TMPR_EN - Tamper Control 9437 */ 9438 #define RTC_TAMPER_SCR_TMPR_EN(x) (((uint16_t)(((uint16_t)(x)) << RTC_TAMPER_SCR_TMPR_EN_SHIFT)) & RTC_TAMPER_SCR_TMPR_EN_MASK) 9439 9440 #define RTC_TAMPER_SCR_TMPR_STS_MASK (0xF00U) 9441 #define RTC_TAMPER_SCR_TMPR_STS_SHIFT (8U) 9442 /*! TMPR_STS - Tamper Status Bit 9443 */ 9444 #define RTC_TAMPER_SCR_TMPR_STS(x) (((uint16_t)(((uint16_t)(x)) << RTC_TAMPER_SCR_TMPR_STS_SHIFT)) & RTC_TAMPER_SCR_TMPR_STS_MASK) 9445 /*! @} */ 9446 9447 /*! @name FILTER01_CFG - RTC Tamper 0 1 Filter Configuration Register */ 9448 /*! @{ */ 9449 9450 #define RTC_FILTER01_CFG_FIL_DUR1_MASK (0xFU) 9451 #define RTC_FILTER01_CFG_FIL_DUR1_SHIFT (0U) 9452 /*! FIL_DUR1 - Tamper Detect Bit 1 Filter Duration 9453 * 0b0000..Filtering operation disabled. 9454 */ 9455 #define RTC_FILTER01_CFG_FIL_DUR1(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER01_CFG_FIL_DUR1_SHIFT)) & RTC_FILTER01_CFG_FIL_DUR1_MASK) 9456 9457 #define RTC_FILTER01_CFG_CLK_SEL1_MASK (0x70U) 9458 #define RTC_FILTER01_CFG_CLK_SEL1_SHIFT (4U) 9459 /*! CLK_SEL1 - Tamper Filter 1 Clock Select 9460 * 0b000..32 kHz clock 9461 * 0b001..512 Hz clock 9462 * 0b010..128 Hz clock 9463 * 0b011..64 Hz clock 9464 * 0b100..16 Hz clock 9465 * 0b101..8 Hz clock 9466 * 0b110..4 Hz clock 9467 * 0b111..2 Hz clock 9468 */ 9469 #define RTC_FILTER01_CFG_CLK_SEL1(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER01_CFG_CLK_SEL1_SHIFT)) & RTC_FILTER01_CFG_CLK_SEL1_MASK) 9470 9471 #define RTC_FILTER01_CFG_POL1_MASK (0x80U) 9472 #define RTC_FILTER01_CFG_POL1_SHIFT (7U) 9473 /*! POL1 - Tamper Detect Input Bit 1 Polarity Control 9474 * 0b0..Tamper detect input bit 1 is active high. 9475 * 0b1..Tamper detect input bit 1 is active low. 9476 */ 9477 #define RTC_FILTER01_CFG_POL1(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER01_CFG_POL1_SHIFT)) & RTC_FILTER01_CFG_POL1_MASK) 9478 9479 #define RTC_FILTER01_CFG_FIL_DUR0_MASK (0xF00U) 9480 #define RTC_FILTER01_CFG_FIL_DUR0_SHIFT (8U) 9481 /*! FIL_DUR0 - Tamper Detect Bit 0 Filter Duration 9482 * 0b0000..Filtering operation disabled. 9483 */ 9484 #define RTC_FILTER01_CFG_FIL_DUR0(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER01_CFG_FIL_DUR0_SHIFT)) & RTC_FILTER01_CFG_FIL_DUR0_MASK) 9485 9486 #define RTC_FILTER01_CFG_CLK_SEL0_MASK (0x7000U) 9487 #define RTC_FILTER01_CFG_CLK_SEL0_SHIFT (12U) 9488 /*! CLK_SEL0 - Tamper Filter 0 Clock Select 9489 * 0b000..32 kHz clock 9490 * 0b001..512 Hz clock 9491 * 0b010..128 Hz clock 9492 * 0b011..64 Hz clock 9493 * 0b100..16 Hz clock 9494 * 0b101..8 Hz clock 9495 * 0b110..4 Hz clock 9496 * 0b111..2 Hz clock 9497 */ 9498 #define RTC_FILTER01_CFG_CLK_SEL0(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER01_CFG_CLK_SEL0_SHIFT)) & RTC_FILTER01_CFG_CLK_SEL0_MASK) 9499 9500 #define RTC_FILTER01_CFG_POL0_MASK (0x8000U) 9501 #define RTC_FILTER01_CFG_POL0_SHIFT (15U) 9502 /*! POL0 - Tamper Detect Input Bit 0 Polarity Control 9503 * 0b0..Tamper detect input bit 0 is active high. 9504 * 0b1..Tamper detect input bit 0 is active low. 9505 */ 9506 #define RTC_FILTER01_CFG_POL0(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER01_CFG_POL0_SHIFT)) & RTC_FILTER01_CFG_POL0_MASK) 9507 /*! @} */ 9508 9509 /*! @name FILTER2_CFG - RTC Tamper 2 Filter Configuration Register */ 9510 /*! @{ */ 9511 9512 #define RTC_FILTER2_CFG_FIL_DUR2_MASK (0xF00U) 9513 #define RTC_FILTER2_CFG_FIL_DUR2_SHIFT (8U) 9514 /*! FIL_DUR2 - Tamper Detect Bit 2 Filter Duration 9515 * 0b0000..Filtering operation disabled. 9516 */ 9517 #define RTC_FILTER2_CFG_FIL_DUR2(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER2_CFG_FIL_DUR2_SHIFT)) & RTC_FILTER2_CFG_FIL_DUR2_MASK) 9518 9519 #define RTC_FILTER2_CFG_CLK_SEL2_MASK (0x7000U) 9520 #define RTC_FILTER2_CFG_CLK_SEL2_SHIFT (12U) 9521 /*! CLK_SEL2 - Tamper Filter 2 Clock Select 9522 * 0b000..32 kHz clock 9523 * 0b001..512 Hz clock 9524 * 0b010..128 Hz clock 9525 * 0b011..64 Hz clock 9526 * 0b100..16 Hz clock 9527 * 0b101..8 Hz clock 9528 * 0b110..4 Hz clock 9529 * 0b111..2 Hz clock 9530 */ 9531 #define RTC_FILTER2_CFG_CLK_SEL2(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER2_CFG_CLK_SEL2_SHIFT)) & RTC_FILTER2_CFG_CLK_SEL2_MASK) 9532 9533 #define RTC_FILTER2_CFG_POL2_MASK (0x8000U) 9534 #define RTC_FILTER2_CFG_POL2_SHIFT (15U) 9535 /*! POL2 - Tamper Detect Input Bit 2 Polarity Control 9536 * 0b0..Tamper detect input bit 2 is active high. 9537 * 0b1..Tamper detect input bit 2 is active low. 9538 */ 9539 #define RTC_FILTER2_CFG_POL2(x) (((uint16_t)(((uint16_t)(x)) << RTC_FILTER2_CFG_POL2_SHIFT)) & RTC_FILTER2_CFG_POL2_MASK) 9540 /*! @} */ 9541 9542 /*! @name CTRL2 - RTC Control 2 Register */ 9543 /*! @{ */ 9544 9545 #define RTC_CTRL2_TAMP_CFG_OVER_MASK (0x1U) 9546 #define RTC_CTRL2_TAMP_CFG_OVER_SHIFT (0U) 9547 /*! TAMP_CFG_OVER - Tamper Configuration Over 9548 * 0b0..Tamper filter processing disabled. 9549 * 0b1..Tamper filter processing enabled. To enable the tamper feature, this bitfield should be set. 9550 */ 9551 #define RTC_CTRL2_TAMP_CFG_OVER(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL2_TAMP_CFG_OVER_SHIFT)) & RTC_CTRL2_TAMP_CFG_OVER_MASK) 9552 9553 #define RTC_CTRL2_WAKEUP_STATUS_MASK (0x60U) 9554 #define RTC_CTRL2_WAKEUP_STATUS_SHIFT (5U) 9555 /*! WAKEUP_STATUS - Wakeup Status 9556 * 0b00..The wakeup/hibernation pin is in HiZ mode. 9557 * 0b01..The wakeup/hibernation pin is at logic 0. MCU is in sleep mode. 9558 * 0b10..The wakeup/ hibernation pin is at logic 1. MCU is in sleep mode. 9559 * 0b11..Reserved 9560 */ 9561 #define RTC_CTRL2_WAKEUP_STATUS(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL2_WAKEUP_STATUS_SHIFT)) & RTC_CTRL2_WAKEUP_STATUS_MASK) 9562 9563 #define RTC_CTRL2_WAKEUP_MODE_MASK (0x80U) 9564 #define RTC_CTRL2_WAKEUP_MODE_SHIFT (7U) 9565 /*! WAKEUP_MODE - Wakeup Mode 9566 * 0b0..Tamper pin 0 is used as the tamper pin. 9567 * 0b1..Tamper pin 0 is used as a wakeup/hibernation pin. 9568 */ 9569 #define RTC_CTRL2_WAKEUP_MODE(x) (((uint16_t)(((uint16_t)(x)) << RTC_CTRL2_WAKEUP_MODE_SHIFT)) & RTC_CTRL2_WAKEUP_MODE_MASK) 9570 /*! @} */ 9571 9572 9573 /*! 9574 * @} 9575 */ /* end of group RTC_Register_Masks */ 9576 9577 9578 /* RTC - Peripheral instance base addresses */ 9579 /** Peripheral RTC base address */ 9580 #define RTC_BASE (0x40050000u) 9581 /** Peripheral RTC base pointer */ 9582 #define RTC ((RTC_Type *)RTC_BASE) 9583 /** Array initializer of RTC peripheral base addresses */ 9584 #define RTC_BASE_ADDRS { RTC_BASE } 9585 /** Array initializer of RTC peripheral base pointers */ 9586 #define RTC_BASE_PTRS { RTC } 9587 /** Interrupt vectors for the RTC peripheral type */ 9588 #define RTC_IRQS { RTC_IRQn } 9589 9590 /*! 9591 * @} 9592 */ /* end of group RTC_Peripheral_Access_Layer */ 9593 9594 9595 /* ---------------------------------------------------------------------------- 9596 -- SIM Peripheral Access Layer 9597 ---------------------------------------------------------------------------- */ 9598 9599 /*! 9600 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer 9601 * @{ 9602 */ 9603 9604 /** SIM - Register Layout Typedef */ 9605 typedef struct { 9606 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */ 9607 __IO uint32_t SOPT1_CFG; /**< SOPT1 Configuration Register, offset: 0x4 */ 9608 uint8_t RESERVED_0[4092]; 9609 __IO uint32_t CTRL_REG; /**< System Control Register, offset: 0x1004 */ 9610 uint8_t RESERVED_1[28]; 9611 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */ 9612 uint8_t RESERVED_2[12]; 9613 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */ 9614 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */ 9615 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */ 9616 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */ 9617 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */ 9618 uint8_t RESERVED_3[4]; 9619 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */ 9620 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */ 9621 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */ 9622 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */ 9623 __I uint32_t UIDML; /**< Unique Identification Register Mid-Low, offset: 0x105C */ 9624 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */ 9625 uint8_t RESERVED_4[8]; 9626 __IO uint32_t MISC_CTL; /**< Miscellaneous Control Register, offset: 0x106C */ 9627 } SIM_Type; 9628 9629 /* ---------------------------------------------------------------------------- 9630 -- SIM Register Masks 9631 ---------------------------------------------------------------------------- */ 9632 9633 /*! 9634 * @addtogroup SIM_Register_Masks SIM Register Masks 9635 * @{ 9636 */ 9637 9638 /*! @name SOPT1 - System Options Register 1 */ 9639 /*! @{ */ 9640 9641 #define SIM_SOPT1_SRAMSIZE_MASK (0xF000U) 9642 #define SIM_SOPT1_SRAMSIZE_SHIFT (12U) 9643 /*! SRAMSIZE - Returns the size of the system RAM 9644 * 0b0101..16kB System RAM 9645 */ 9646 #define SIM_SOPT1_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_SRAMSIZE_SHIFT)) & SIM_SOPT1_SRAMSIZE_MASK) 9647 9648 #define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U) 9649 #define SIM_SOPT1_OSC32KSEL_SHIFT (18U) 9650 /*! OSC32KSEL - 32K oscillator clock select 9651 * 0b00..OSC32KCLK 9652 * 0b01..ERCLK32K 9653 * 0b10..MCGIRCLK 9654 * 0b11..LPO 9655 */ 9656 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK) 9657 /*! @} */ 9658 9659 /*! @name SOPT1_CFG - SOPT1 Configuration Register */ 9660 /*! @{ */ 9661 9662 #define SIM_SOPT1_CFG_LPTMR1SEL_MASK (0x3U) 9663 #define SIM_SOPT1_CFG_LPTMR1SEL_SHIFT (0U) 9664 /*! LPTMR1SEL - LP timer Channel1 Select 9665 * 0b00..Pad PTE4 9666 * 0b01..Pad PTF4 9667 * 0b10..Pad PTG1 9668 * 0b11..Reserved 9669 */ 9670 #define SIM_SOPT1_CFG_LPTMR1SEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_CFG_LPTMR1SEL_SHIFT)) & SIM_SOPT1_CFG_LPTMR1SEL_MASK) 9671 9672 #define SIM_SOPT1_CFG_LPTMR2SEL_MASK (0xCU) 9673 #define SIM_SOPT1_CFG_LPTMR2SEL_SHIFT (2U) 9674 /*! LPTMR2SEL - LP timer Channel2 Select 9675 * 0b00..Pad PTD6 9676 * 0b01..Pad PTF3 9677 * 0b10..Pad PTG5 9678 * 0b11..Reserved 9679 */ 9680 #define SIM_SOPT1_CFG_LPTMR2SEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_CFG_LPTMR2SEL_SHIFT)) & SIM_SOPT1_CFG_LPTMR2SEL_MASK) 9681 9682 #define SIM_SOPT1_CFG_LPTMR3SEL_MASK (0x30U) 9683 #define SIM_SOPT1_CFG_LPTMR3SEL_SHIFT (4U) 9684 /*! LPTMR3SEL - LP timer Channel3 Select 9685 * 0b00..Pad PTD5 9686 * 0b01..Pad PTG0 9687 * 0b10..Pad PTG6 9688 * 0b11..Reserved 9689 */ 9690 #define SIM_SOPT1_CFG_LPTMR3SEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_CFG_LPTMR3SEL_SHIFT)) & SIM_SOPT1_CFG_LPTMR3SEL_MASK) 9691 9692 #define SIM_SOPT1_CFG_CMPOLPTMR0SEL_MASK (0x40U) 9693 #define SIM_SOPT1_CFG_CMPOLPTMR0SEL_SHIFT (6U) 9694 /*! CMPOLPTMR0SEL - Comparator output selection for LPTMR channel0 9695 * 0b0..CMP[1] output selected as LPTMR input[0] 9696 * 0b1..CMP[0] output selected as LPTMR input[0] 9697 */ 9698 #define SIM_SOPT1_CFG_CMPOLPTMR0SEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_CFG_CMPOLPTMR0SEL_SHIFT)) & SIM_SOPT1_CFG_CMPOLPTMR0SEL_MASK) 9699 9700 #define SIM_SOPT1_CFG_RAMSBDIS_MASK (0x100U) 9701 #define SIM_SOPT1_CFG_RAMSBDIS_SHIFT (8U) 9702 /*! RAMSBDIS 9703 * 0b0..Source bias of System SRAM enabled during VLPR and VLPW modes. 9704 * 0b1..Source bias of System SRAM disabled during VLPR and VLPW modes. 9705 */ 9706 #define SIM_SOPT1_CFG_RAMSBDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_CFG_RAMSBDIS_SHIFT)) & SIM_SOPT1_CFG_RAMSBDIS_MASK) 9707 9708 #define SIM_SOPT1_CFG_RAMBPEN_MASK (0x200U) 9709 #define SIM_SOPT1_CFG_RAMBPEN_SHIFT (9U) 9710 /*! RAMBPEN - RAM Bitline Precharge Enable 9711 * 0b0..Bitline precharge of system SRAM disabled during VLPR and VLPW modes. 9712 * 0b1..Bitline precharge of system SRAM enabled during VLPR and VLPW modes. 9713 */ 9714 #define SIM_SOPT1_CFG_RAMBPEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_CFG_RAMBPEN_SHIFT)) & SIM_SOPT1_CFG_RAMBPEN_MASK) 9715 /*! @} */ 9716 9717 /*! @name CTRL_REG - System Control Register */ 9718 /*! @{ */ 9719 9720 #define SIM_CTRL_REG_NMIDIS_MASK (0x1U) 9721 #define SIM_CTRL_REG_NMIDIS_SHIFT (0U) 9722 /*! NMIDIS - NMI Disable 9723 * 0b0..NMI enabled 9724 * 0b1..NMI disabled 9725 */ 9726 #define SIM_CTRL_REG_NMIDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_CTRL_REG_NMIDIS_SHIFT)) & SIM_CTRL_REG_NMIDIS_MASK) 9727 9728 #define SIM_CTRL_REG_PLL_VLP_EN_MASK (0x2U) 9729 #define SIM_CTRL_REG_PLL_VLP_EN_SHIFT (1U) 9730 /*! PLL_VLP_EN - PLL VLP Enable 9731 */ 9732 #define SIM_CTRL_REG_PLL_VLP_EN(x) (((uint32_t)(((uint32_t)(x)) << SIM_CTRL_REG_PLL_VLP_EN_SHIFT)) & SIM_CTRL_REG_PLL_VLP_EN_MASK) 9733 9734 #define SIM_CTRL_REG_PTC2_HD_EN_MASK (0x4U) 9735 #define SIM_CTRL_REG_PTC2_HD_EN_SHIFT (2U) 9736 /*! PTC2_HD_EN - PTC2 HighDrive Enable 9737 */ 9738 #define SIM_CTRL_REG_PTC2_HD_EN(x) (((uint32_t)(((uint32_t)(x)) << SIM_CTRL_REG_PTC2_HD_EN_SHIFT)) & SIM_CTRL_REG_PTC2_HD_EN_MASK) 9739 9740 #define SIM_CTRL_REG_SAR_TRG_CLK_SEL_MASK (0x18U) 9741 #define SIM_CTRL_REG_SAR_TRG_CLK_SEL_SHIFT (3U) 9742 /*! SAR_TRG_CLK_SEL - SAR ADC Trigger Clk Select 9743 * 0b00..Bus Clock (During Low Power Modes such as stop, the Bus clock is not available for conversion and should 9744 * not be selected in case a conversion needs to be performed while in stop) 9745 * 0b01..ADC asynchronous Clock 9746 * 0b10..ERCLK32K 9747 * 0b11..OSCCLK 9748 */ 9749 #define SIM_CTRL_REG_SAR_TRG_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_CTRL_REG_SAR_TRG_CLK_SEL_SHIFT)) & SIM_CTRL_REG_SAR_TRG_CLK_SEL_MASK) 9750 9751 #define SIM_CTRL_REG_CLKOUTSEL_MASK (0xE0U) 9752 #define SIM_CTRL_REG_CLKOUTSEL_SHIFT (5U) 9753 /*! CLKOUTSEL - Clock out Select 9754 * 0b000..Disabled 9755 * 0b001..Gated Core Clk 9756 * 0b010..Bus/Flash Clk 9757 * 0b011..LPO clock from PMC 9758 * 0b100..IRC clock from MCG 9759 * 0b101..Muxed 32Khz source (please refer SOPT1[19:18] for possible options) 9760 * 0b110..MHz Oscillator external reference clock 9761 * 0b111..PLL clock output from MCG 9762 */ 9763 #define SIM_CTRL_REG_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_CTRL_REG_CLKOUTSEL_SHIFT)) & SIM_CTRL_REG_CLKOUTSEL_MASK) 9764 /*! @} */ 9765 9766 /*! @name SDID - System Device Identification Register */ 9767 /*! @{ */ 9768 9769 #define SIM_SDID_PINID_MASK (0xFU) 9770 #define SIM_SDID_PINID_SHIFT (0U) 9771 /*! PINID - Pincount identification 9772 * 0b0011..44-pin 9773 * 0b0100..Reserved 9774 * 0b0101..64-pin 9775 * 0b0110..Reserved 9776 * 0b0111..Reserved 9777 * 0b1000..100-pin 9778 * 0b1001..Reserved 9779 * 0b1010..Reserved 9780 * 0b1011..Reserved 9781 * 0b1100..Reserved 9782 * 0b1101..Reserved 9783 * 0b1110..Reserved 9784 * 0b1111..Reserved 9785 */ 9786 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK) 9787 9788 #define SIM_SDID_DIEID_MASK (0xF0U) 9789 #define SIM_SDID_DIEID_SHIFT (4U) 9790 /*! DIEID - Die ID 9791 * 0b0000..First cut 9792 */ 9793 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK) 9794 9795 #define SIM_SDID_REVID_MASK (0xF00U) 9796 #define SIM_SDID_REVID_SHIFT (8U) 9797 /*! REVID - Revision ID 9798 * 0b0010..Third Cut 9799 */ 9800 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK) 9801 9802 #define SIM_SDID_SRAMSIZE_MASK (0xF000U) 9803 #define SIM_SDID_SRAMSIZE_SHIFT (12U) 9804 /*! SRAMSIZE - SRAM Size 9805 * 0b0101..16kB SRAM 9806 */ 9807 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SRAMSIZE_SHIFT)) & SIM_SDID_SRAMSIZE_MASK) 9808 9809 #define SIM_SDID_ATTR_MASK (0xF0000U) 9810 #define SIM_SDID_ATTR_SHIFT (16U) 9811 /*! ATTR - Attribute ID 9812 * 0b0000..M0+ core 9813 */ 9814 #define SIM_SDID_ATTR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_ATTR_SHIFT)) & SIM_SDID_ATTR_MASK) 9815 9816 #define SIM_SDID_SERIESID_MASK (0xF00000U) 9817 #define SIM_SDID_SERIESID_SHIFT (20U) 9818 /*! SERIESID - Series ID 9819 * 0b0011..Metering Series 9820 */ 9821 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK) 9822 9823 #define SIM_SDID_SUBFAMID_MASK (0xF000000U) 9824 #define SIM_SDID_SUBFAMID_SHIFT (24U) 9825 /*! SUBFAMID - Sub-Family ID 9826 * 0b0010..Device derivatives with 2 AFE enabled (AFE Channels 0 and 2 are enabled) 9827 * 0b0011..Device derivatives with 3 AFE enabled (AFE Channels 0, 1, and 2 are enabled) 9828 * 0b0100..Device derivatives with 4 AFE enabled 9829 */ 9830 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK) 9831 9832 #define SIM_SDID_FAMID_MASK (0xF0000000U) 9833 #define SIM_SDID_FAMID_SHIFT (28U) 9834 /*! FAMID - Metering family ID 9835 * 0b0001..Device derivatives without LCD 9836 * 0b0011..Device derivatives with LCD 9837 */ 9838 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK) 9839 /*! @} */ 9840 9841 /*! @name SCGC4 - System Clock Gating Control Register 4 */ 9842 /*! @{ */ 9843 9844 #define SIM_SCGC4_EWM_MASK (0x2U) 9845 #define SIM_SCGC4_EWM_SHIFT (1U) 9846 /*! EWM - External Watchdog Monitor Clock gate control 9847 * 0b0..Clock disabled 9848 * 0b1..Clock enabled 9849 */ 9850 #define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK) 9851 9852 #define SIM_SCGC4_MCG_MASK (0x10U) 9853 #define SIM_SCGC4_MCG_SHIFT (4U) 9854 /*! MCG - MCG clock gate control. 9855 * 0b0..Clock disabled 9856 * 0b1..Clock enabled 9857 */ 9858 #define SIM_SCGC4_MCG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_MCG_SHIFT)) & SIM_SCGC4_MCG_MASK) 9859 9860 #define SIM_SCGC4_OSC_MASK (0x40U) 9861 #define SIM_SCGC4_OSC_SHIFT (6U) 9862 /*! OSC - Oscillator (Mhz) Clock Gate Control 9863 * 0b0..Clock disabled 9864 * 0b1..Clock enabled 9865 */ 9866 #define SIM_SCGC4_OSC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_OSC_SHIFT)) & SIM_SCGC4_OSC_MASK) 9867 9868 #define SIM_SCGC4_I2C0_MASK (0x80U) 9869 #define SIM_SCGC4_I2C0_SHIFT (7U) 9870 /*! I2C0 - I2C0 Clock Gate Control 9871 * 0b0..Clock disabled 9872 * 0b1..Clock enabled 9873 */ 9874 #define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK) 9875 9876 #define SIM_SCGC4_I2C1_MASK (0x100U) 9877 #define SIM_SCGC4_I2C1_SHIFT (8U) 9878 /*! I2C1 - I2C1 Clock Gate Control 9879 * 0b0..Clock disabled 9880 * 0b1..Clock enabled 9881 */ 9882 #define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK) 9883 9884 #define SIM_SCGC4_UART0_MASK (0x400U) 9885 #define SIM_SCGC4_UART0_SHIFT (10U) 9886 /*! UART0 - UART0 Clock Gate Control 9887 * 0b0..Clock disabled 9888 * 0b1..Clock enabled 9889 */ 9890 #define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK) 9891 9892 #define SIM_SCGC4_UART1_MASK (0x800U) 9893 #define SIM_SCGC4_UART1_SHIFT (11U) 9894 /*! UART1 - UART1 Clock Gate Control 9895 * 0b0..Clock disabled 9896 * 0b1..Clock enabled 9897 */ 9898 #define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK) 9899 9900 #define SIM_SCGC4_UART2_MASK (0x1000U) 9901 #define SIM_SCGC4_UART2_SHIFT (12U) 9902 /*! UART2 - UART2 Clock Gate Control 9903 * 0b0..Clock disabled 9904 * 0b1..Clock enabled 9905 */ 9906 #define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK) 9907 9908 #define SIM_SCGC4_UART3_MASK (0x2000U) 9909 #define SIM_SCGC4_UART3_SHIFT (13U) 9910 /*! UART3 - UART3 Clock Gate Control 9911 * 0b0..Clock disabled 9912 * 0b1..Clock enabled 9913 */ 9914 #define SIM_SCGC4_UART3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK) 9915 9916 #define SIM_SCGC4_VREF_MASK (0x8000U) 9917 #define SIM_SCGC4_VREF_SHIFT (15U) 9918 /*! VREF - VREF Clock Gate Control 9919 * 0b0..Clock disabled 9920 * 0b1..Clock enabled 9921 */ 9922 #define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK) 9923 9924 #define SIM_SCGC4_CMP0_MASK (0x40000U) 9925 #define SIM_SCGC4_CMP0_SHIFT (18U) 9926 /*! CMP0 - High Speed Comparator0 Clock Gate Control. 9927 * 0b0..Clock disabled 9928 * 0b1..Clock enabled 9929 */ 9930 #define SIM_SCGC4_CMP0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP0_SHIFT)) & SIM_SCGC4_CMP0_MASK) 9931 9932 #define SIM_SCGC4_CMP1_MASK (0x80000U) 9933 #define SIM_SCGC4_CMP1_SHIFT (19U) 9934 /*! CMP1 - High Speed Comparator1 Clock Gate Control. 9935 * 0b0..Clock disabled 9936 * 0b1..Clock enabled 9937 */ 9938 #define SIM_SCGC4_CMP1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP1_SHIFT)) & SIM_SCGC4_CMP1_MASK) 9939 9940 #define SIM_SCGC4_SPI0_MASK (0x200000U) 9941 #define SIM_SCGC4_SPI0_SHIFT (21U) 9942 /*! SPI0 - SPI0 Clock Gate Control 9943 * 0b0..Clock disabled 9944 * 0b1..Clock enabled 9945 */ 9946 #define SIM_SCGC4_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_SPI0_SHIFT)) & SIM_SCGC4_SPI0_MASK) 9947 9948 #define SIM_SCGC4_SPI1_MASK (0x400000U) 9949 #define SIM_SCGC4_SPI1_SHIFT (22U) 9950 /*! SPI1 - SPI1 Clock Gate Control 9951 * 0b0..Clock disabled 9952 * 0b1..Clock enabled 9953 */ 9954 #define SIM_SCGC4_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_SPI1_SHIFT)) & SIM_SCGC4_SPI1_MASK) 9955 /*! @} */ 9956 9957 /*! @name SCGC5 - System Clock Gating Control Register 5 */ 9958 /*! @{ */ 9959 9960 #define SIM_SCGC5_SLCD_MASK (0x8U) 9961 #define SIM_SCGC5_SLCD_SHIFT (3U) 9962 /*! SLCD - Segmented LCD Clock Gate Control 9963 * 0b0..Clock disabled 9964 * 0b1..Clock enabled 9965 */ 9966 #define SIM_SCGC5_SLCD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_SLCD_SHIFT)) & SIM_SCGC5_SLCD_MASK) 9967 9968 #define SIM_SCGC5_PORTA_MASK (0x40U) 9969 #define SIM_SCGC5_PORTA_SHIFT (6U) 9970 /*! PORTA - PCTLA Clock Gate Control 9971 * 0b0..Clock disabled 9972 * 0b1..Clock enabled 9973 */ 9974 #define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK) 9975 9976 #define SIM_SCGC5_PORTB_MASK (0x80U) 9977 #define SIM_SCGC5_PORTB_SHIFT (7U) 9978 /*! PORTB - PCTLB Clock Gate Control 9979 * 0b0..Clock disabled 9980 * 0b1..Clock enabled 9981 */ 9982 #define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK) 9983 9984 #define SIM_SCGC5_PORTC_MASK (0x100U) 9985 #define SIM_SCGC5_PORTC_SHIFT (8U) 9986 /*! PORTC - PCTLC Clock Gate Control 9987 * 0b0..Clock disabled 9988 * 0b1..Clock enabled 9989 */ 9990 #define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK) 9991 9992 #define SIM_SCGC5_PORTD_MASK (0x200U) 9993 #define SIM_SCGC5_PORTD_SHIFT (9U) 9994 /*! PORTD - PCTLD Clock Gate Control 9995 * 0b0..Clock disabled 9996 * 0b1..Clock enabled 9997 */ 9998 #define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK) 9999 10000 #define SIM_SCGC5_PORTE_MASK (0x400U) 10001 #define SIM_SCGC5_PORTE_SHIFT (10U) 10002 /*! PORTE - PCTLE Clock Gate Control 10003 * 0b0..Clock disabled 10004 * 0b1..Clock enabled 10005 */ 10006 #define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK) 10007 10008 #define SIM_SCGC5_PORTF_MASK (0x800U) 10009 #define SIM_SCGC5_PORTF_SHIFT (11U) 10010 /*! PORTF - PCTLF Clock Gate Control 10011 * 0b0..Clock disabled 10012 * 0b1..Clock enabled 10013 */ 10014 #define SIM_SCGC5_PORTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTF_SHIFT)) & SIM_SCGC5_PORTF_MASK) 10015 10016 #define SIM_SCGC5_PORTG_MASK (0x1000U) 10017 #define SIM_SCGC5_PORTG_SHIFT (12U) 10018 /*! PORTG - PCTLG Clock Gate Control 10019 * 0b0..Clock disabled 10020 * 0b1..Clock enabled 10021 */ 10022 #define SIM_SCGC5_PORTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTG_SHIFT)) & SIM_SCGC5_PORTG_MASK) 10023 10024 #define SIM_SCGC5_PORTH_MASK (0x2000U) 10025 #define SIM_SCGC5_PORTH_SHIFT (13U) 10026 /*! PORTH - PCTLH Clock Gate Control 10027 * 0b0..Clock disabled 10028 * 0b1..Clock enabled 10029 */ 10030 #define SIM_SCGC5_PORTH(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTH_SHIFT)) & SIM_SCGC5_PORTH_MASK) 10031 10032 #define SIM_SCGC5_PORTI_MASK (0x4000U) 10033 #define SIM_SCGC5_PORTI_SHIFT (14U) 10034 /*! PORTI - PCTLI Clock Gate Control 10035 * 0b0..Clock disabled 10036 * 0b1..Clock enabled 10037 */ 10038 #define SIM_SCGC5_PORTI(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTI_SHIFT)) & SIM_SCGC5_PORTI_MASK) 10039 10040 #define SIM_SCGC5_IRTC_MASK (0x10000U) 10041 #define SIM_SCGC5_IRTC_SHIFT (16U) 10042 /*! IRTC - IRTC Clock Gate Control 10043 * 0b0..Clock disabled 10044 * 0b1..Clock enabled 10045 */ 10046 #define SIM_SCGC5_IRTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_IRTC_SHIFT)) & SIM_SCGC5_IRTC_MASK) 10047 10048 #define SIM_SCGC5_IRTCREGFILE_MASK (0x20000U) 10049 #define SIM_SCGC5_IRTCREGFILE_SHIFT (17U) 10050 /*! IRTCREGFILE - IRTC_REG_FILE Clock Gate Control 10051 * 0b0..Clock disabled 10052 * 0b1..Clock enabled 10053 */ 10054 #define SIM_SCGC5_IRTCREGFILE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_IRTCREGFILE_SHIFT)) & SIM_SCGC5_IRTCREGFILE_MASK) 10055 10056 #define SIM_SCGC5_WDOG_MASK (0x80000U) 10057 #define SIM_SCGC5_WDOG_SHIFT (19U) 10058 /*! WDOG - Watchdog Clock Gate Control 10059 * 0b0..Clock disabled 10060 * 0b1..Clock enabled 10061 */ 10062 #define SIM_SCGC5_WDOG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_WDOG_SHIFT)) & SIM_SCGC5_WDOG_MASK) 10063 10064 #define SIM_SCGC5_XBAR_MASK (0x200000U) 10065 #define SIM_SCGC5_XBAR_SHIFT (21U) 10066 /*! XBAR - Peripheral Crossbar Clock Gate Control 10067 * 0b0..Clock disabled 10068 * 0b1..Clock enabled 10069 */ 10070 #define SIM_SCGC5_XBAR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_XBAR_SHIFT)) & SIM_SCGC5_XBAR_MASK) 10071 10072 #define SIM_SCGC5_TMR0_MASK (0x800000U) 10073 #define SIM_SCGC5_TMR0_SHIFT (23U) 10074 /*! TMR0 - Quadtimer0 Clock Gate Control 10075 * 0b0..Clock disabled 10076 * 0b1..Clock enabled 10077 */ 10078 #define SIM_SCGC5_TMR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TMR0_SHIFT)) & SIM_SCGC5_TMR0_MASK) 10079 10080 #define SIM_SCGC5_TMR1_MASK (0x1000000U) 10081 #define SIM_SCGC5_TMR1_SHIFT (24U) 10082 /*! TMR1 - Quadtimer1 Clock Gate Control 10083 * 0b0..Clock disabled 10084 * 0b1..Clock enabled 10085 */ 10086 #define SIM_SCGC5_TMR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TMR1_SHIFT)) & SIM_SCGC5_TMR1_MASK) 10087 10088 #define SIM_SCGC5_TMR2_MASK (0x2000000U) 10089 #define SIM_SCGC5_TMR2_SHIFT (25U) 10090 /*! TMR2 - Quadtimer2 Clock Gate Control 10091 * 0b0..Clock disabled 10092 * 0b1..Clock enabled 10093 */ 10094 #define SIM_SCGC5_TMR2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TMR2_SHIFT)) & SIM_SCGC5_TMR2_MASK) 10095 10096 #define SIM_SCGC5_TMR3_MASK (0x4000000U) 10097 #define SIM_SCGC5_TMR3_SHIFT (26U) 10098 /*! TMR3 - Quadtimer3 Clock Gate Control 10099 * 0b0..Clock disabled 10100 * 0b1..Clock enabled 10101 */ 10102 #define SIM_SCGC5_TMR3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TMR3_SHIFT)) & SIM_SCGC5_TMR3_MASK) 10103 /*! @} */ 10104 10105 /*! @name SCGC6 - System Clock Gating Control Register 6 */ 10106 /*! @{ */ 10107 10108 #define SIM_SCGC6_FTFA_MASK (0x1U) 10109 #define SIM_SCGC6_FTFA_SHIFT (0U) 10110 /*! FTFA - FTFA Clock Gate Control 10111 * 0b0..Clock disabled 10112 * 0b1..Clock enabled 10113 */ 10114 #define SIM_SCGC6_FTFA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTFA_SHIFT)) & SIM_SCGC6_FTFA_MASK) 10115 10116 #define SIM_SCGC6_DMAMUX0_MASK (0x2U) 10117 #define SIM_SCGC6_DMAMUX0_SHIFT (1U) 10118 /*! DMAMUX0 - DMA MUX0 Clock Gate Control 10119 * 0b0..Clock disabled 10120 * 0b1..Clock enabled 10121 */ 10122 #define SIM_SCGC6_DMAMUX0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX0_SHIFT)) & SIM_SCGC6_DMAMUX0_MASK) 10123 10124 #define SIM_SCGC6_DMAMUX1_MASK (0x4U) 10125 #define SIM_SCGC6_DMAMUX1_SHIFT (2U) 10126 /*! DMAMUX1 - DMA MUX1 Clock Gate Control 10127 * 0b0..Clock disabled 10128 * 0b1..Clock enabled 10129 */ 10130 #define SIM_SCGC6_DMAMUX1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX1_SHIFT)) & SIM_SCGC6_DMAMUX1_MASK) 10131 10132 #define SIM_SCGC6_DMAMUX2_MASK (0x8U) 10133 #define SIM_SCGC6_DMAMUX2_SHIFT (3U) 10134 /*! DMAMUX2 - DMA MUX2 Clock Gate Control 10135 * 0b0..Clock disabled 10136 * 0b1..Clock enabled 10137 */ 10138 #define SIM_SCGC6_DMAMUX2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX2_SHIFT)) & SIM_SCGC6_DMAMUX2_MASK) 10139 10140 #define SIM_SCGC6_DMAMUX3_MASK (0x10U) 10141 #define SIM_SCGC6_DMAMUX3_SHIFT (4U) 10142 /*! DMAMUX3 - DMA MUX3 Clock Gate Control 10143 * 0b0..Clock disabled 10144 * 0b1..Clock enabled 10145 */ 10146 #define SIM_SCGC6_DMAMUX3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX3_SHIFT)) & SIM_SCGC6_DMAMUX3_MASK) 10147 10148 #define SIM_SCGC6_RNGA_MASK (0x200U) 10149 #define SIM_SCGC6_RNGA_SHIFT (9U) 10150 /*! RNGA - RNGA Clock Gate Control 10151 * 0b0..Clock disabled 10152 * 0b1..Clock enabled 10153 */ 10154 #define SIM_SCGC6_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RNGA_SHIFT)) & SIM_SCGC6_RNGA_MASK) 10155 10156 #define SIM_SCGC6_ADC_MASK (0x800U) 10157 #define SIM_SCGC6_ADC_SHIFT (11U) 10158 /*! ADC - SAR ADC Clock Gate Control 10159 * 0b0..Clock disabled 10160 * 0b1..Clock enabled 10161 */ 10162 #define SIM_SCGC6_ADC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC_SHIFT)) & SIM_SCGC6_ADC_MASK) 10163 10164 #define SIM_SCGC6_PIT0_MASK (0x2000U) 10165 #define SIM_SCGC6_PIT0_SHIFT (13U) 10166 /*! PIT0 - PIT0 Clock Gate Control 10167 * 0b0..Clock disabled 10168 * 0b1..Clock enabled 10169 */ 10170 #define SIM_SCGC6_PIT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT0_SHIFT)) & SIM_SCGC6_PIT0_MASK) 10171 10172 #define SIM_SCGC6_PIT1_MASK (0x4000U) 10173 #define SIM_SCGC6_PIT1_SHIFT (14U) 10174 /*! PIT1 - PIT1 Clock Gate Control 10175 * 0b0..Clock disabled 10176 * 0b1..Clock enabled 10177 */ 10178 #define SIM_SCGC6_PIT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT1_SHIFT)) & SIM_SCGC6_PIT1_MASK) 10179 10180 #define SIM_SCGC6_AFE_MASK (0x10000U) 10181 #define SIM_SCGC6_AFE_SHIFT (16U) 10182 /*! AFE - AFE Clock Gate Control 10183 * 0b0..Clock disabled 10184 * 0b1..Clock enabled 10185 */ 10186 #define SIM_SCGC6_AFE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_AFE_SHIFT)) & SIM_SCGC6_AFE_MASK) 10187 10188 #define SIM_SCGC6_CRC_MASK (0x100000U) 10189 #define SIM_SCGC6_CRC_SHIFT (20U) 10190 /*! CRC - Programmable CRC Clock Gate Control 10191 * 0b0..Clock disabled 10192 * 0b1..Clock enabled 10193 */ 10194 #define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK) 10195 10196 #define SIM_SCGC6_LPTMR_MASK (0x10000000U) 10197 #define SIM_SCGC6_LPTMR_SHIFT (28U) 10198 /*! LPTMR - LPTMR Clock Gate Control 10199 * 0b0..Clock disabled 10200 * 0b1..Clock enabled 10201 */ 10202 #define SIM_SCGC6_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_LPTMR_SHIFT)) & SIM_SCGC6_LPTMR_MASK) 10203 10204 #define SIM_SCGC6_SIM_LP_MASK (0x40000000U) 10205 #define SIM_SCGC6_SIM_LP_SHIFT (30U) 10206 /*! SIM_LP - SIM_LP Clock Gate Control 10207 * 0b1..Clock is enabled 10208 * 0b0..Clock is disabled 10209 */ 10210 #define SIM_SCGC6_SIM_LP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SIM_LP_SHIFT)) & SIM_SCGC6_SIM_LP_MASK) 10211 10212 #define SIM_SCGC6_SIM_HP_MASK (0x80000000U) 10213 #define SIM_SCGC6_SIM_HP_SHIFT (31U) 10214 /*! SIM_HP - SIM_HP Clock Gate Control 10215 * 0b1..Clock is always enabled to SIM 10216 */ 10217 #define SIM_SCGC6_SIM_HP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SIM_HP_SHIFT)) & SIM_SCGC6_SIM_HP_MASK) 10218 /*! @} */ 10219 10220 /*! @name SCGC7 - System Clock Gating Control Register 7 */ 10221 /*! @{ */ 10222 10223 #define SIM_SCGC7_MPU_MASK (0x1U) 10224 #define SIM_SCGC7_MPU_SHIFT (0U) 10225 /*! MPU - MPU Clock Gate control. 10226 * 0b0..Clock disabled 10227 * 0b1..Clock enabled 10228 */ 10229 #define SIM_SCGC7_MPU(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK) 10230 10231 #define SIM_SCGC7_DMA_MASK (0x2U) 10232 #define SIM_SCGC7_DMA_SHIFT (1U) 10233 /*! DMA - DMA Clock Gate control. 10234 * 0b0..Clock disabled 10235 * 0b1..Clock enabled 10236 */ 10237 #define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK) 10238 /*! @} */ 10239 10240 /*! @name CLKDIV1 - System Clock Divider Register 1 */ 10241 /*! @{ */ 10242 10243 #define SIM_CLKDIV1_SYSCLKMODE_MASK (0x8000000U) 10244 #define SIM_CLKDIV1_SYSCLKMODE_SHIFT (27U) 10245 /*! SYSCLKMODE - System Clock Mode 10246 * 0b0..1:1:1 10247 * 0b1..2:1:1 10248 */ 10249 #define SIM_CLKDIV1_SYSCLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_SYSCLKMODE_SHIFT)) & SIM_CLKDIV1_SYSCLKMODE_MASK) 10250 10251 #define SIM_CLKDIV1_SYSDIV_MASK (0xF0000000U) 10252 #define SIM_CLKDIV1_SYSDIV_SHIFT (28U) 10253 /*! SYSDIV - System Clock divider 10254 * 0b0000..Divide by 1 10255 * 0b0001..Divide by 2 10256 * 0b0010..Divide by 3 10257 * 0b0011..Divide by 4 and so on..... If FOPT[0] is 0, the divider is set to div-by-8 after system reset is 10258 * deasserted (after completion of system initialization sequence) 10259 */ 10260 #define SIM_CLKDIV1_SYSDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_SYSDIV_SHIFT)) & SIM_CLKDIV1_SYSDIV_MASK) 10261 /*! @} */ 10262 10263 /*! @name FCFG1 - Flash Configuration Register 1 */ 10264 /*! @{ */ 10265 10266 #define SIM_FCFG1_FLASHDIS_MASK (0x1U) 10267 #define SIM_FCFG1_FLASHDIS_SHIFT (0U) 10268 /*! FLASHDIS - Flash Disable 10269 * 0b0..Flash is enabled 10270 * 0b1..Flash is disabled 10271 */ 10272 #define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK) 10273 10274 #define SIM_FCFG1_FLASHDOZE_MASK (0x2U) 10275 #define SIM_FCFG1_FLASHDOZE_SHIFT (1U) 10276 /*! FLASHDOZE - Flash Doze 10277 * 0b0..Flash remains enabled during Wait mode 10278 * 0b1..Flash is disabled for the duration of Wait mode 10279 */ 10280 #define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK) 10281 10282 #define SIM_FCFG1_PFSIZE_MASK (0xF000000U) 10283 #define SIM_FCFG1_PFSIZE_SHIFT (24U) 10284 /*! PFSIZE - Program flash size 10285 * 0b0000..Reserved 10286 * 0b0001..Reserved 10287 * 0b0011..Reserved 10288 * 0b0100..Reserved 10289 * 0b0101..64 KB of program flash memory, 2 KB protection region 10290 * 0b0110..Reserved 10291 * 0b0111..128 KB of program flash memory, 4 KB protection region 10292 * 0b1000..Reserved 10293 * 0b1001..Reserved 10294 * 0b1111..(Default) 10295 */ 10296 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK) 10297 /*! @} */ 10298 10299 /*! @name FCFG2 - Flash Configuration Register 2 */ 10300 /*! @{ */ 10301 10302 #define SIM_FCFG2_MAXADDR_MASK (0x7F000000U) 10303 #define SIM_FCFG2_MAXADDR_SHIFT (24U) 10304 /*! MAXADDR - Max address block 10305 */ 10306 #define SIM_FCFG2_MAXADDR(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR_SHIFT)) & SIM_FCFG2_MAXADDR_MASK) 10307 /*! @} */ 10308 10309 /*! @name UIDH - Unique Identification Register High */ 10310 /*! @{ */ 10311 10312 #define SIM_UIDH_UID127_96_MASK (0xFFFFFFFFU) 10313 #define SIM_UIDH_UID127_96_SHIFT (0U) 10314 /*! UID127_96 - Unique Identification UID[127:96] 10315 */ 10316 #define SIM_UIDH_UID127_96(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID127_96_SHIFT)) & SIM_UIDH_UID127_96_MASK) 10317 /*! @} */ 10318 10319 /*! @name UIDMH - Unique Identification Register Mid-High */ 10320 /*! @{ */ 10321 10322 #define SIM_UIDMH_UID95_64_MASK (0xFFFFFFFFU) 10323 #define SIM_UIDMH_UID95_64_SHIFT (0U) 10324 /*! UID95_64 - Unique Identification UID[95:64] 10325 */ 10326 #define SIM_UIDMH_UID95_64(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID95_64_SHIFT)) & SIM_UIDMH_UID95_64_MASK) 10327 /*! @} */ 10328 10329 /*! @name UIDML - Unique Identification Register Mid-Low */ 10330 /*! @{ */ 10331 10332 #define SIM_UIDML_UID63_32_MASK (0xFFFFFFFFU) 10333 #define SIM_UIDML_UID63_32_SHIFT (0U) 10334 /*! UID63_32 - Unique Identification UID[63:32] 10335 */ 10336 #define SIM_UIDML_UID63_32(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID63_32_SHIFT)) & SIM_UIDML_UID63_32_MASK) 10337 /*! @} */ 10338 10339 /*! @name UIDL - Unique Identification Register Low */ 10340 /*! @{ */ 10341 10342 #define SIM_UIDL_UID31_0_MASK (0xFFFFFFFFU) 10343 #define SIM_UIDL_UID31_0_SHIFT (0U) 10344 /*! UID31_0 - Unique Identification UID[31:0] 10345 */ 10346 #define SIM_UIDL_UID31_0(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID31_0_SHIFT)) & SIM_UIDL_UID31_0_MASK) 10347 /*! @} */ 10348 10349 /*! @name MISC_CTL - Miscellaneous Control Register */ 10350 /*! @{ */ 10351 10352 #define SIM_MISC_CTL_XBARAFEMODOUTSEL_MASK (0x3U) 10353 #define SIM_MISC_CTL_XBARAFEMODOUTSEL_SHIFT (0U) 10354 /*! XBARAFEMODOUTSEL - XBAR AFE Modulator Output Select 10355 * 0b00..Sigma Delta Modulator 0 data output 10356 * 0b01..Sigma Delta Modulator 1 data output 10357 * 0b10..Sigma Delta Modulator 2 data output 10358 * 0b11..Sigma Delta Modulator 3 data output 10359 */ 10360 #define SIM_MISC_CTL_XBARAFEMODOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTL_XBARAFEMODOUTSEL_SHIFT)) & SIM_MISC_CTL_XBARAFEMODOUTSEL_MASK) 10361 10362 #define SIM_MISC_CTL_DMADONESEL_MASK (0xCU) 10363 #define SIM_MISC_CTL_DMADONESEL_SHIFT (2U) 10364 /*! DMADONESEL - DMA Done select 10365 * 0b00..DMA0 10366 * 0b01..DMA1 10367 * 0b10..DMA2 10368 * 0b11..DMA3 10369 */ 10370 #define SIM_MISC_CTL_DMADONESEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTL_DMADONESEL_SHIFT)) & SIM_MISC_CTL_DMADONESEL_MASK) 10371 10372 #define SIM_MISC_CTL_AFECLKSEL_MASK (0x30U) 10373 #define SIM_MISC_CTL_AFECLKSEL_SHIFT (4U) 10374 /*! AFECLKSEL - AFE Clock Source Select 10375 * 0b00..MCG PLL Clock selected 10376 * 0b01..MCG FLL Clock selected 10377 * 0b10..OSC Clock selected 10378 * 0b11..Disabled 10379 */ 10380 #define SIM_MISC_CTL_AFECLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTL_AFECLKSEL_SHIFT)) & SIM_MISC_CTL_AFECLKSEL_MASK) 10381 10382 #define SIM_MISC_CTL_AFECLKPADDIR_MASK (0x40U) 10383 #define SIM_MISC_CTL_AFECLKPADDIR_SHIFT (6U) 10384 /*! AFECLKPADDIR - AFE Clock Pad Direction 10385 * 0b0..AFE CLK PAD is input 10386 * 0b1..AFE CLK PAD is output 10387 */ 10388 #define SIM_MISC_CTL_AFECLKPADDIR(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTL_AFECLKPADDIR_SHIFT)) & SIM_MISC_CTL_AFECLKPADDIR_MASK) 10389 10390 #define SIM_MISC_CTL_UARTMODTYPE_MASK (0x80U) 10391 #define SIM_MISC_CTL_UARTMODTYPE_SHIFT (7U) 10392 /*! UARTMODTYPE - UART Modulation Type 10393 * 0b0..TypeA (ORed) Modulation selected for IRDA 10394 * 0b1..TypeB (ANDed) Modulation selected for IRDA 10395 */ 10396 #define SIM_MISC_CTL_UARTMODTYPE(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTL_UARTMODTYPE_SHIFT)) & SIM_MISC_CTL_UARTMODTYPE_MASK) 10397 10398 #define SIM_MISC_CTL_UART0IRSEL_MASK (0x100U) 10399 #define SIM_MISC_CTL_UART0IRSEL_SHIFT (8U) 10400 /*! UART0IRSEL - UART0 IRDA Select 10401 * 0b0..Pad RX input (PTD[0] or PTF[3], as selected in Pinmux control) selected for RX input of UART0 and UART0 TX signal is not used for modulation 10402 * 0b1..UART0 selected for IRDA modulation. UART0 TX modulated by XBAR_OUT[14] and UART0 RX input connected to XBAR_OUT[13] 10403 */ 10404 #define SIM_MISC_CTL_UART0IRSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTL_UART0IRSEL_SHIFT)) & SIM_MISC_CTL_UART0IRSEL_MASK) 10405 10406 #define SIM_MISC_CTL_UART1IRSEL_MASK (0x200U) 10407 #define SIM_MISC_CTL_UART1IRSEL_SHIFT (9U) 10408 /*! UART1IRSEL - UART1 IRDA Select 10409 * 0b0..Pad RX input (PTD[2] or PTI[0], as selected in Pinmux control) selected for RX input of UART1 and UART1 TX signal is not used for modulation 10410 * 0b1..UART1 selected for IRDA modulation. UART1 TX modulated by XBAR_OUT[14] and UART1 RX input connected to XBAR_OUT[13] 10411 */ 10412 #define SIM_MISC_CTL_UART1IRSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTL_UART1IRSEL_SHIFT)) & SIM_MISC_CTL_UART1IRSEL_MASK) 10413 10414 #define SIM_MISC_CTL_UART2IRSEL_MASK (0x400U) 10415 #define SIM_MISC_CTL_UART2IRSEL_SHIFT (10U) 10416 /*! UART2IRSEL - UART2 IRDA Select 10417 * 0b0..Pad RX input PTE[6] selected for RX input of UART2 and UART2 TX signal is not used for modulation 10418 * 0b1..UART2 selected for IRDA modulation. UART2 TX modulated by XBAR_OUT[14] and UART2 RX input connected to XBAR_OUT[13]. 10419 */ 10420 #define SIM_MISC_CTL_UART2IRSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTL_UART2IRSEL_SHIFT)) & SIM_MISC_CTL_UART2IRSEL_MASK) 10421 10422 #define SIM_MISC_CTL_UART3IRSEL_MASK (0x800U) 10423 #define SIM_MISC_CTL_UART3IRSEL_SHIFT (11U) 10424 /*! UART3IRSEL - UART3 IRDA Select 10425 * 0b0..Pad RX input (PTC[3] or PTD[7], as selected in Pinmux control) selected for RX input of UART3 and UART3 TX signal is not used for modulation 10426 * 0b1..UART3 selected for IRDA modulation. UART3 TX modulated by XBAR_OUT[14] and UART3 RX input connected to XBAR_OUT[13]. 10427 */ 10428 #define SIM_MISC_CTL_UART3IRSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTL_UART3IRSEL_SHIFT)) & SIM_MISC_CTL_UART3IRSEL_MASK) 10429 10430 #define SIM_MISC_CTL_XBARPITOUTSEL_MASK (0x3000U) 10431 #define SIM_MISC_CTL_XBARPITOUTSEL_SHIFT (12U) 10432 /*! XBARPITOUTSEL - XBAR PIT Output select 10433 * 0b00..PIT0[0] (default) 10434 * 0b01..PIT0[1] 10435 * 0b10..PIT1[0] 10436 * 0b11..PIT1[1] 10437 */ 10438 #define SIM_MISC_CTL_XBARPITOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTL_XBARPITOUTSEL_SHIFT)) & SIM_MISC_CTL_XBARPITOUTSEL_MASK) 10439 10440 #define SIM_MISC_CTL_EWMINSEL_MASK (0x4000U) 10441 #define SIM_MISC_CTL_EWMINSEL_SHIFT (14U) 10442 /*! EWMINSEL - External Watchdog Monitor Input Select 10443 * 0b0..Input from PAD (PTE[2] or PTE[4] as selected from Pinmux control ) 10444 * 0b1..Peripheral Crossbar (XBAR) Output[32] 10445 */ 10446 #define SIM_MISC_CTL_EWMINSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTL_EWMINSEL_SHIFT)) & SIM_MISC_CTL_EWMINSEL_MASK) 10447 10448 #define SIM_MISC_CTL_TMR0PLLCLKSEL_MASK (0x8000U) 10449 #define SIM_MISC_CTL_TMR0PLLCLKSEL_SHIFT (15U) 10450 /*! TMR0PLLCLKSEL - Timer CH0 PLL clock select 10451 * 0b0..Selects Bus Clock as source for the Timer CH0 10452 * 0b1..Selects the PLL_AFE clock as the source for Timer CH0. The PLL_AFE clock source is itself selected using the MISC_CTL[5:4] 10453 */ 10454 #define SIM_MISC_CTL_TMR0PLLCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTL_TMR0PLLCLKSEL_SHIFT)) & SIM_MISC_CTL_TMR0PLLCLKSEL_MASK) 10455 10456 #define SIM_MISC_CTL_TMR0SCSSEL_MASK (0x10000U) 10457 #define SIM_MISC_CTL_TMR0SCSSEL_SHIFT (16U) 10458 /*! TMR0SCSSEL - Quadtimer Channel0 Secondary Count Source Select 10459 * 0b0..Pad PTF1 or PTD5, depending upon PCTL configuration. 10460 * 0b1..Peripheral Crossbar (XBAR) Output[5] 10461 */ 10462 #define SIM_MISC_CTL_TMR0SCSSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTL_TMR0SCSSEL_SHIFT)) & SIM_MISC_CTL_TMR0SCSSEL_MASK) 10463 10464 #define SIM_MISC_CTL_TMR1SCSSEL_MASK (0x20000U) 10465 #define SIM_MISC_CTL_TMR1SCSSEL_SHIFT (17U) 10466 /*! TMR1SCSSEL - Quadtimer Channel1 Secondary Count Source Select 10467 * 0b0..Pad PTG0 or PTC6, depending upon PCTL configuration. 10468 * 0b1..Peripheral Crossbar (XBAR) Output[6] 10469 */ 10470 #define SIM_MISC_CTL_TMR1SCSSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTL_TMR1SCSSEL_SHIFT)) & SIM_MISC_CTL_TMR1SCSSEL_MASK) 10471 10472 #define SIM_MISC_CTL_TMR2SCSSEL_MASK (0x40000U) 10473 #define SIM_MISC_CTL_TMR2SCSSEL_SHIFT (18U) 10474 /*! TMR2SCSSEL - Quadtimer Channel2 Secondary Count Source Select 10475 * 0b0..Pad PTF7 or PTF0, depending upon PCTL configuration. 10476 * 0b1..Peripheral Crossbar (XBAR) Output[7] 10477 */ 10478 #define SIM_MISC_CTL_TMR2SCSSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTL_TMR2SCSSEL_SHIFT)) & SIM_MISC_CTL_TMR2SCSSEL_MASK) 10479 10480 #define SIM_MISC_CTL_TMR3SCSSEL_MASK (0x80000U) 10481 #define SIM_MISC_CTL_TMR3SCSSEL_SHIFT (19U) 10482 /*! TMR3SCSSEL - Quadtimer Channel3 Secondary Count Source Select 10483 * 0b0..Pad PTE5 or PTD1, depending upon PCTL configuration. 10484 * 0b1..Peripheral Crossbar (XBAR) Output[8] 10485 */ 10486 #define SIM_MISC_CTL_TMR3SCSSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTL_TMR3SCSSEL_SHIFT)) & SIM_MISC_CTL_TMR3SCSSEL_MASK) 10487 10488 #define SIM_MISC_CTL_TMR0PCSSEL_MASK (0x300000U) 10489 #define SIM_MISC_CTL_TMR0PCSSEL_SHIFT (20U) 10490 /*! TMR0PCSSEL - Quadtimer Channel0 Primary Count Source Select 10491 * 0b00..Bus Clock 10492 * 0b01..Peripheral Crossbar Output [9] 10493 * 0b10..Peripheral Crossbar Output [10] 10494 * 0b11..Disabled 10495 */ 10496 #define SIM_MISC_CTL_TMR0PCSSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTL_TMR0PCSSEL_SHIFT)) & SIM_MISC_CTL_TMR0PCSSEL_MASK) 10497 10498 #define SIM_MISC_CTL_TMR1PCSSEL_MASK (0xC00000U) 10499 #define SIM_MISC_CTL_TMR1PCSSEL_SHIFT (22U) 10500 /*! TMR1PCSSEL - Quadtimer Channel1 Primary Count Source Select 10501 * 0b00..Bus Clock 10502 * 0b01..Peripheral Crossbar Output [9] 10503 * 0b10..Peripheral Crossbar Output [10] 10504 * 0b11..Disabled 10505 */ 10506 #define SIM_MISC_CTL_TMR1PCSSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTL_TMR1PCSSEL_SHIFT)) & SIM_MISC_CTL_TMR1PCSSEL_MASK) 10507 10508 #define SIM_MISC_CTL_TMR2PCSSEL_MASK (0x3000000U) 10509 #define SIM_MISC_CTL_TMR2PCSSEL_SHIFT (24U) 10510 /*! TMR2PCSSEL - Quadtimer Channel2 Primary Count Source Select 10511 * 0b00..Bus Clock 10512 * 0b01..Peripheral Crossbar Output [9] 10513 * 0b10..Peripheral Crossbar Output [10] 10514 * 0b11..Disabled 10515 */ 10516 #define SIM_MISC_CTL_TMR2PCSSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTL_TMR2PCSSEL_SHIFT)) & SIM_MISC_CTL_TMR2PCSSEL_MASK) 10517 10518 #define SIM_MISC_CTL_TMR3PCSSEL_MASK (0xC000000U) 10519 #define SIM_MISC_CTL_TMR3PCSSEL_SHIFT (26U) 10520 /*! TMR3PCSSEL - Quadtimer Channel3 Primary Count Source Select 10521 * 0b00..Bus Clock 10522 * 0b01..Peripheral Crossbar Output [9] 10523 * 0b10..Peripheral Crossbar Output [10] 10524 * 0b11..Disabled 10525 */ 10526 #define SIM_MISC_CTL_TMR3PCSSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTL_TMR3PCSSEL_SHIFT)) & SIM_MISC_CTL_TMR3PCSSEL_MASK) 10527 10528 #define SIM_MISC_CTL_RTCCLKSEL_MASK (0x10000000U) 10529 #define SIM_MISC_CTL_RTCCLKSEL_SHIFT (28U) 10530 /*! RTCCLKSEL - RTC Clock select 10531 * 0b0..RTC OSC_32K clock selected 10532 * 0b1..32K IRC Clock selected 10533 */ 10534 #define SIM_MISC_CTL_RTCCLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTL_RTCCLKSEL_SHIFT)) & SIM_MISC_CTL_RTCCLKSEL_MASK) 10535 10536 #define SIM_MISC_CTL_VREFBUFOUTEN_MASK (0x20000000U) 10537 #define SIM_MISC_CTL_VREFBUFOUTEN_SHIFT (29U) 10538 /*! VREFBUFOUTEN - VrefBuffer Output Enable 10539 * 0b0..Buffer does not drive PAD 10540 * 0b1..Buffer drives selected voltage (selected by vref_buffer_sel) on pad 10541 */ 10542 #define SIM_MISC_CTL_VREFBUFOUTEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTL_VREFBUFOUTEN_SHIFT)) & SIM_MISC_CTL_VREFBUFOUTEN_MASK) 10543 10544 #define SIM_MISC_CTL_VREFBUFINSEL_MASK (0x40000000U) 10545 #define SIM_MISC_CTL_VREFBUFINSEL_SHIFT (30U) 10546 /*! VREFBUFINSEL - VrefBuffer Input Select 10547 * 0b0..Internal Reference selected as Buffer Input 10548 * 0b1..External Reference selected as Buffer Input 10549 */ 10550 #define SIM_MISC_CTL_VREFBUFINSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTL_VREFBUFINSEL_SHIFT)) & SIM_MISC_CTL_VREFBUFINSEL_MASK) 10551 10552 #define SIM_MISC_CTL_VREFBUFPD_MASK (0x80000000U) 10553 #define SIM_MISC_CTL_VREFBUFPD_SHIFT (31U) 10554 /*! VREFBUFPD - VrefBuffer Power Down 10555 * 0b0..Buffer Enabled 10556 * 0b1..Buffer Powered Down 10557 */ 10558 #define SIM_MISC_CTL_VREFBUFPD(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISC_CTL_VREFBUFPD_SHIFT)) & SIM_MISC_CTL_VREFBUFPD_MASK) 10559 /*! @} */ 10560 10561 10562 /*! 10563 * @} 10564 */ /* end of group SIM_Register_Masks */ 10565 10566 10567 /* SIM - Peripheral instance base addresses */ 10568 /** Peripheral SIM base address */ 10569 #define SIM_BASE (0x4003E000u) 10570 /** Peripheral SIM base pointer */ 10571 #define SIM ((SIM_Type *)SIM_BASE) 10572 /** Array initializer of SIM peripheral base addresses */ 10573 #define SIM_BASE_ADDRS { SIM_BASE } 10574 /** Array initializer of SIM peripheral base pointers */ 10575 #define SIM_BASE_PTRS { SIM } 10576 10577 /*! 10578 * @} 10579 */ /* end of group SIM_Peripheral_Access_Layer */ 10580 10581 10582 /* ---------------------------------------------------------------------------- 10583 -- SMC Peripheral Access Layer 10584 ---------------------------------------------------------------------------- */ 10585 10586 /*! 10587 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer 10588 * @{ 10589 */ 10590 10591 /** SMC - Register Layout Typedef */ 10592 typedef struct { 10593 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */ 10594 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */ 10595 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */ 10596 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */ 10597 } SMC_Type; 10598 10599 /* ---------------------------------------------------------------------------- 10600 -- SMC Register Masks 10601 ---------------------------------------------------------------------------- */ 10602 10603 /*! 10604 * @addtogroup SMC_Register_Masks SMC Register Masks 10605 * @{ 10606 */ 10607 10608 /*! @name PMPROT - Power Mode Protection register */ 10609 /*! @{ */ 10610 10611 #define SMC_PMPROT_AVLLS_MASK (0x2U) 10612 #define SMC_PMPROT_AVLLS_SHIFT (1U) 10613 /*! AVLLS - Allow Very-Low-Leakage Stop Mode 10614 * 0b0..Any VLLSx mode is not allowed 10615 * 0b1..Any VLLSx mode is allowed 10616 */ 10617 #define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK) 10618 10619 #define SMC_PMPROT_AVLP_MASK (0x20U) 10620 #define SMC_PMPROT_AVLP_SHIFT (5U) 10621 /*! AVLP - Allow Very-Low-Power Modes 10622 * 0b0..VLPR, VLPW, and VLPS are not allowed. 10623 * 0b1..VLPR, VLPW, and VLPS are allowed. 10624 */ 10625 #define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK) 10626 /*! @} */ 10627 10628 /*! @name PMCTRL - Power Mode Control register */ 10629 /*! @{ */ 10630 10631 #define SMC_PMCTRL_STOPM_MASK (0x7U) 10632 #define SMC_PMCTRL_STOPM_SHIFT (0U) 10633 /*! STOPM - Stop Mode Control 10634 * 0b000..Normal Stop (STOP) 10635 * 0b001..Reserved 10636 * 0b010..Very-Low-Power Stop (VLPS) 10637 * 0b011..Reserved 10638 * 0b100..Very-Low-Leakage Stop (VLLSx) 10639 * 0b101..Reserved 10640 * 0b110..Reseved 10641 * 0b111..Reserved 10642 */ 10643 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK) 10644 10645 #define SMC_PMCTRL_STOPA_MASK (0x8U) 10646 #define SMC_PMCTRL_STOPA_SHIFT (3U) 10647 /*! STOPA - Stop Aborted 10648 * 0b0..The previous stop mode entry was successful. 10649 * 0b1..The previous stop mode entry was aborted. 10650 */ 10651 #define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK) 10652 10653 #define SMC_PMCTRL_RUNM_MASK (0x60U) 10654 #define SMC_PMCTRL_RUNM_SHIFT (5U) 10655 /*! RUNM - Run Mode Control 10656 * 0b00..Normal Run mode (RUN) 10657 * 0b01..Reserved 10658 * 0b10..Very-Low-Power Run mode (VLPR) 10659 * 0b11..Reserved 10660 */ 10661 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK) 10662 /*! @} */ 10663 10664 /*! @name STOPCTRL - Stop Control Register */ 10665 /*! @{ */ 10666 10667 #define SMC_STOPCTRL_VLLSM_MASK (0x7U) 10668 #define SMC_STOPCTRL_VLLSM_SHIFT (0U) 10669 /*! VLLSM - VLLS Mode Control 10670 * 0b000..VLLS0 10671 * 0b001..VLLS1 10672 * 0b010..VLLS2 10673 * 0b011..VLLS3 10674 * 0b100..Reserved 10675 * 0b101..Reserved 10676 * 0b110..Reserved 10677 * 0b111..Reserved 10678 */ 10679 #define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_VLLSM_SHIFT)) & SMC_STOPCTRL_VLLSM_MASK) 10680 10681 #define SMC_STOPCTRL_PORPO_MASK (0x20U) 10682 #define SMC_STOPCTRL_PORPO_SHIFT (5U) 10683 /*! PORPO - POR Power Option 10684 * 0b0..POR detect circuit is enabled in VLLS0 10685 * 0b1..POR detect circuit is disabled in VLLS0 10686 */ 10687 #define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK) 10688 10689 #define SMC_STOPCTRL_PSTOPO_MASK (0xC0U) 10690 #define SMC_STOPCTRL_PSTOPO_SHIFT (6U) 10691 /*! PSTOPO - Partial Stop Option 10692 * 0b00..STOP - Normal Stop mode 10693 * 0b01..PSTOP1 - Partial Stop with both system and bus clocks disabled 10694 * 0b10..PSTOP2 - Partial Stop with system clock disabled and bus clock enabled 10695 * 0b11..Reserved 10696 */ 10697 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK) 10698 /*! @} */ 10699 10700 /*! @name PMSTAT - Power Mode Status register */ 10701 /*! @{ */ 10702 10703 #define SMC_PMSTAT_PMSTAT_MASK (0xFFU) 10704 #define SMC_PMSTAT_PMSTAT_SHIFT (0U) 10705 /*! PMSTAT - Power Mode Status 10706 */ 10707 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK) 10708 /*! @} */ 10709 10710 10711 /*! 10712 * @} 10713 */ /* end of group SMC_Register_Masks */ 10714 10715 10716 /* SMC - Peripheral instance base addresses */ 10717 /** Peripheral SMC base address */ 10718 #define SMC_BASE (0x4007E000u) 10719 /** Peripheral SMC base pointer */ 10720 #define SMC ((SMC_Type *)SMC_BASE) 10721 /** Array initializer of SMC peripheral base addresses */ 10722 #define SMC_BASE_ADDRS { SMC_BASE } 10723 /** Array initializer of SMC peripheral base pointers */ 10724 #define SMC_BASE_PTRS { SMC } 10725 10726 /*! 10727 * @} 10728 */ /* end of group SMC_Peripheral_Access_Layer */ 10729 10730 10731 /* ---------------------------------------------------------------------------- 10732 -- SPI Peripheral Access Layer 10733 ---------------------------------------------------------------------------- */ 10734 10735 /*! 10736 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer 10737 * @{ 10738 */ 10739 10740 /** SPI - Register Layout Typedef */ 10741 typedef struct { 10742 __IO uint8_t S; /**< SPI Status Register, offset: 0x0 */ 10743 __IO uint8_t BR; /**< SPI Baud Rate Register, offset: 0x1 */ 10744 __IO uint8_t C2; /**< SPI Control Register 2, offset: 0x2 */ 10745 __IO uint8_t C1; /**< SPI Control Register 1, offset: 0x3 */ 10746 __IO uint8_t ML; /**< SPI Match Register low, offset: 0x4 */ 10747 __IO uint8_t MH; /**< SPI match register high, offset: 0x5 */ 10748 __IO uint8_t DL; /**< SPI Data Register low, offset: 0x6 */ 10749 __IO uint8_t DH; /**< SPI data register high, offset: 0x7 */ 10750 uint8_t RESERVED_0[2]; 10751 __IO uint8_t CI; /**< SPI clear interrupt register, offset: 0xA */ 10752 __IO uint8_t C3; /**< SPI control register 3, offset: 0xB */ 10753 } SPI_Type; 10754 10755 /* ---------------------------------------------------------------------------- 10756 -- SPI Register Masks 10757 ---------------------------------------------------------------------------- */ 10758 10759 /*! 10760 * @addtogroup SPI_Register_Masks SPI Register Masks 10761 * @{ 10762 */ 10763 10764 /*! @name S - SPI Status Register */ 10765 /*! @{ */ 10766 10767 #define SPI_S_RFIFOEF_MASK (0x1U) 10768 #define SPI_S_RFIFOEF_SHIFT (0U) 10769 /*! RFIFOEF - SPI read FIFO empty flag 10770 * 0b0..Read FIFO has data. Reads of the DH:DL registers in 16-bit mode or the DL register in 8-bit mode will empty the read FIFO. 10771 * 0b1..Read FIFO is empty. 10772 */ 10773 #define SPI_S_RFIFOEF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_RFIFOEF_SHIFT)) & SPI_S_RFIFOEF_MASK) 10774 10775 #define SPI_S_TXFULLF_MASK (0x2U) 10776 #define SPI_S_TXFULLF_SHIFT (1U) 10777 /*! TXFULLF - Transmit FIFO full flag 10778 * 0b0..Transmit FIFO has less than 8 bytes 10779 * 0b1..Transmit FIFO has 8 bytes of data 10780 */ 10781 #define SPI_S_TXFULLF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_TXFULLF_SHIFT)) & SPI_S_TXFULLF_MASK) 10782 10783 #define SPI_S_TNEAREF_MASK (0x4U) 10784 #define SPI_S_TNEAREF_SHIFT (2U) 10785 /*! TNEAREF - Transmit FIFO nearly empty flag 10786 * 0b0..Transmit FIFO has more than 16 bits (when C3[5] is 0) or more than 32 bits (when C3[5] is 1) remaining to transmit 10787 * 0b1..Transmit FIFO has an amount of data equal to or less than 16 bits (when C3[5] is 0) or 32 bits (when C3[5] is 1) remaining to transmit 10788 */ 10789 #define SPI_S_TNEAREF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_TNEAREF_SHIFT)) & SPI_S_TNEAREF_MASK) 10790 10791 #define SPI_S_RNFULLF_MASK (0x8U) 10792 #define SPI_S_RNFULLF_SHIFT (3U) 10793 /*! RNFULLF - Receive FIFO nearly full flag 10794 * 0b0..Receive FIFO has received less than 48 bits (when C3[4] is 0) or less than 32 bits (when C3[4] is 1) 10795 * 0b1..Receive FIFO has received data of an amount equal to or greater than 48 bits (when C3[4] is 0) or 32 bits (when C3[4] is 1) 10796 */ 10797 #define SPI_S_RNFULLF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_RNFULLF_SHIFT)) & SPI_S_RNFULLF_MASK) 10798 10799 #define SPI_S_MODF_MASK (0x10U) 10800 #define SPI_S_MODF_SHIFT (4U) 10801 /*! MODF - Master Mode Fault Flag 10802 * 0b0..No mode fault error 10803 * 0b1..Mode fault error detected 10804 */ 10805 #define SPI_S_MODF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_MODF_SHIFT)) & SPI_S_MODF_MASK) 10806 10807 #define SPI_S_SPTEF_MASK (0x20U) 10808 #define SPI_S_SPTEF_SHIFT (5U) 10809 /*! SPTEF - SPI Transmit Buffer Empty Flag (when FIFO is not supported or not enabled) or SPI 10810 * transmit FIFO empty flag (when FIFO is supported and enabled) 10811 * 0b0..SPI transmit buffer not empty (when FIFOMODE is not present or is 0) or SPI FIFO not empty (when FIFOMODE is 1) 10812 * 0b1..SPI transmit buffer empty (when FIFOMODE is not present or is 0) or SPI FIFO empty (when FIFOMODE is 1) 10813 */ 10814 #define SPI_S_SPTEF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPTEF_SHIFT)) & SPI_S_SPTEF_MASK) 10815 10816 #define SPI_S_SPMF_MASK (0x40U) 10817 #define SPI_S_SPMF_SHIFT (6U) 10818 /*! SPMF - SPI Match Flag 10819 * 0b0..Value in the receive data buffer does not match the value in the MH:ML registers 10820 * 0b1..Value in the receive data buffer matches the value in the MH:ML registers 10821 */ 10822 #define SPI_S_SPMF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPMF_SHIFT)) & SPI_S_SPMF_MASK) 10823 10824 #define SPI_S_SPRF_MASK (0x80U) 10825 #define SPI_S_SPRF_SHIFT (7U) 10826 /*! SPRF - SPI Read Buffer Full Flag (when FIFO is not supported or not enabled) or SPI read FIFO 10827 * FULL flag (when FIFO is supported and enabled) 10828 * 0b0..No data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is not full (when FIFOMODE is 1) 10829 * 0b1..Data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is full (when FIFOMODE is 1) 10830 */ 10831 #define SPI_S_SPRF(x) (((uint8_t)(((uint8_t)(x)) << SPI_S_SPRF_SHIFT)) & SPI_S_SPRF_MASK) 10832 /*! @} */ 10833 10834 /*! @name BR - SPI Baud Rate Register */ 10835 /*! @{ */ 10836 10837 #define SPI_BR_SPR_MASK (0xFU) 10838 #define SPI_BR_SPR_SHIFT (0U) 10839 /*! SPR - SPI Baud Rate Divisor 10840 * 0b0000..Baud rate divisor is 2. 10841 * 0b0001..Baud rate divisor is 4. 10842 * 0b0010..Baud rate divisor is 8. 10843 * 0b0011..Baud rate divisor is 16. 10844 * 0b0100..Baud rate divisor is 32. 10845 * 0b0101..Baud rate divisor is 64. 10846 * 0b0110..Baud rate divisor is 128. 10847 * 0b0111..Baud rate divisor is 256. 10848 * 0b1000..Baud rate divisor is 512. 10849 */ 10850 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPR_SHIFT)) & SPI_BR_SPR_MASK) 10851 10852 #define SPI_BR_SPPR_MASK (0x70U) 10853 #define SPI_BR_SPPR_SHIFT (4U) 10854 /*! SPPR - SPI Baud Rate Prescale Divisor 10855 * 0b000..Baud rate prescaler divisor is 1. 10856 * 0b001..Baud rate prescaler divisor is 2. 10857 * 0b010..Baud rate prescaler divisor is 3. 10858 * 0b011..Baud rate prescaler divisor is 4. 10859 * 0b100..Baud rate prescaler divisor is 5. 10860 * 0b101..Baud rate prescaler divisor is 6. 10861 * 0b110..Baud rate prescaler divisor is 7. 10862 * 0b111..Baud rate prescaler divisor is 8. 10863 */ 10864 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x)) << SPI_BR_SPPR_SHIFT)) & SPI_BR_SPPR_MASK) 10865 /*! @} */ 10866 10867 /*! @name C2 - SPI Control Register 2 */ 10868 /*! @{ */ 10869 10870 #define SPI_C2_SPC0_MASK (0x1U) 10871 #define SPI_C2_SPC0_SHIFT (0U) 10872 /*! SPC0 - SPI Pin Control 0 10873 * 0b0..SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: 10874 * MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave 10875 * in. 10876 * 0b1..SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of 10877 * operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In 10878 * slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not 10879 * used by SPI. 10880 */ 10881 #define SPI_C2_SPC0(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPC0_SHIFT)) & SPI_C2_SPC0_MASK) 10882 10883 #define SPI_C2_SPISWAI_MASK (0x2U) 10884 #define SPI_C2_SPISWAI_SHIFT (1U) 10885 /*! SPISWAI - SPI Stop in Wait Mode 10886 * 0b0..SPI clocks continue to operate in Wait mode. 10887 * 0b1..SPI clocks stop when the MCU enters Wait mode. 10888 */ 10889 #define SPI_C2_SPISWAI(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPISWAI_SHIFT)) & SPI_C2_SPISWAI_MASK) 10890 10891 #define SPI_C2_RXDMAE_MASK (0x4U) 10892 #define SPI_C2_RXDMAE_SHIFT (2U) 10893 /*! RXDMAE - Receive DMA enable 10894 * 0b0..DMA request for receive is disabled and interrupt from SPRF is allowed 10895 * 0b1..DMA request for receive is enabled and interrupt from SPRF is disabled 10896 */ 10897 #define SPI_C2_RXDMAE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_RXDMAE_SHIFT)) & SPI_C2_RXDMAE_MASK) 10898 10899 #define SPI_C2_BIDIROE_MASK (0x8U) 10900 #define SPI_C2_BIDIROE_SHIFT (3U) 10901 /*! BIDIROE - Bidirectional Mode Output Enable 10902 * 0b0..Output driver disabled so SPI data I/O pin acts as an input 10903 * 0b1..SPI I/O pin enabled as an output 10904 */ 10905 #define SPI_C2_BIDIROE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_BIDIROE_SHIFT)) & SPI_C2_BIDIROE_MASK) 10906 10907 #define SPI_C2_MODFEN_MASK (0x10U) 10908 #define SPI_C2_MODFEN_SHIFT (4U) 10909 /*! MODFEN - Master Mode-Fault Function Enable 10910 * 0b0..Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI 10911 * 0b1..Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output 10912 */ 10913 #define SPI_C2_MODFEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_MODFEN_SHIFT)) & SPI_C2_MODFEN_MASK) 10914 10915 #define SPI_C2_TXDMAE_MASK (0x20U) 10916 #define SPI_C2_TXDMAE_SHIFT (5U) 10917 /*! TXDMAE - Transmit DMA enable 10918 * 0b0..DMA request for transmit is disabled and interrupt from SPTEF is allowed 10919 * 0b1..DMA request for transmit is enabled and interrupt from SPTEF is disabled 10920 */ 10921 #define SPI_C2_TXDMAE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_TXDMAE_SHIFT)) & SPI_C2_TXDMAE_MASK) 10922 10923 #define SPI_C2_SPIMODE_MASK (0x40U) 10924 #define SPI_C2_SPIMODE_SHIFT (6U) 10925 /*! SPIMODE - SPI 8-bit or 16-bit mode 10926 * 0b0..8-bit SPI shift register, match register, and buffers 10927 * 0b1..16-bit SPI shift register, match register, and buffers 10928 */ 10929 #define SPI_C2_SPIMODE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPIMODE_SHIFT)) & SPI_C2_SPIMODE_MASK) 10930 10931 #define SPI_C2_SPMIE_MASK (0x80U) 10932 #define SPI_C2_SPMIE_SHIFT (7U) 10933 /*! SPMIE - SPI Match Interrupt Enable 10934 * 0b0..Interrupts from SPMF inhibited (use polling) 10935 * 0b1..When SPMF is 1, requests a hardware interrupt 10936 */ 10937 #define SPI_C2_SPMIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C2_SPMIE_SHIFT)) & SPI_C2_SPMIE_MASK) 10938 /*! @} */ 10939 10940 /*! @name C1 - SPI Control Register 1 */ 10941 /*! @{ */ 10942 10943 #define SPI_C1_LSBFE_MASK (0x1U) 10944 #define SPI_C1_LSBFE_SHIFT (0U) 10945 /*! LSBFE - LSB First (shifter direction) 10946 * 0b0..SPI serial data transfers start with the most significant bit. 10947 * 0b1..SPI serial data transfers start with the least significant bit. 10948 */ 10949 #define SPI_C1_LSBFE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_LSBFE_SHIFT)) & SPI_C1_LSBFE_MASK) 10950 10951 #define SPI_C1_SSOE_MASK (0x2U) 10952 #define SPI_C1_SSOE_SHIFT (1U) 10953 /*! SSOE - Slave Select Output Enable 10954 * 0b0..When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS 10955 * pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is SS input for 10956 * mode fault. In slave mode, SS pin function is slave select input. 10957 * 0b1..When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS 10958 * pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is automatic SS 10959 * output. In slave mode: SS pin function is slave select input. 10960 */ 10961 #define SPI_C1_SSOE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SSOE_SHIFT)) & SPI_C1_SSOE_MASK) 10962 10963 #define SPI_C1_CPHA_MASK (0x4U) 10964 #define SPI_C1_CPHA_SHIFT (2U) 10965 /*! CPHA - Clock Phase 10966 * 0b0..First edge on SPSCK occurs at the middle of the first cycle of a data transfer. 10967 * 0b1..First edge on SPSCK occurs at the start of the first cycle of a data transfer. 10968 */ 10969 #define SPI_C1_CPHA(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPHA_SHIFT)) & SPI_C1_CPHA_MASK) 10970 10971 #define SPI_C1_CPOL_MASK (0x8U) 10972 #define SPI_C1_CPOL_SHIFT (3U) 10973 /*! CPOL - Clock Polarity 10974 * 0b0..Active-high SPI clock (idles low) 10975 * 0b1..Active-low SPI clock (idles high) 10976 */ 10977 #define SPI_C1_CPOL(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_CPOL_SHIFT)) & SPI_C1_CPOL_MASK) 10978 10979 #define SPI_C1_MSTR_MASK (0x10U) 10980 #define SPI_C1_MSTR_SHIFT (4U) 10981 /*! MSTR - Master/Slave Mode Select 10982 * 0b0..SPI module configured as a slave SPI device 10983 * 0b1..SPI module configured as a master SPI device 10984 */ 10985 #define SPI_C1_MSTR(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_MSTR_SHIFT)) & SPI_C1_MSTR_MASK) 10986 10987 #define SPI_C1_SPTIE_MASK (0x20U) 10988 #define SPI_C1_SPTIE_SHIFT (5U) 10989 /*! SPTIE - SPI Transmit Interrupt Enable 10990 * 0b0..Interrupts from SPTEF inhibited (use polling) 10991 * 0b1..When SPTEF is 1, hardware interrupt requested 10992 */ 10993 #define SPI_C1_SPTIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPTIE_SHIFT)) & SPI_C1_SPTIE_MASK) 10994 10995 #define SPI_C1_SPE_MASK (0x40U) 10996 #define SPI_C1_SPE_SHIFT (6U) 10997 /*! SPE - SPI System Enable 10998 * 0b0..SPI system inactive 10999 * 0b1..SPI system enabled 11000 */ 11001 #define SPI_C1_SPE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPE_SHIFT)) & SPI_C1_SPE_MASK) 11002 11003 #define SPI_C1_SPIE_MASK (0x80U) 11004 #define SPI_C1_SPIE_SHIFT (7U) 11005 /*! SPIE - SPI Interrupt Enable: for SPRF and MODF (when FIFO is not supported or not enabled) or 11006 * for read FIFO (when FIFO is supported and enabled) 11007 * 0b0..Interrupts from SPRF and MODF are inhibited-use polling (when FIFOMODE is not present or is 0) or Read 11008 * FIFO Full Interrupts are disabled (when FIFOMODE is 1) 11009 * 0b1..Request a hardware interrupt when SPRF or MODF is 1 (when FIFOMODE is not present or is 0) or Read FIFO 11010 * Full Interrupts are enabled (when FIFOMODE is 1) 11011 */ 11012 #define SPI_C1_SPIE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C1_SPIE_SHIFT)) & SPI_C1_SPIE_MASK) 11013 /*! @} */ 11014 11015 /*! @name ML - SPI Match Register low */ 11016 /*! @{ */ 11017 11018 #define SPI_ML_Bits_MASK (0xFFU) 11019 #define SPI_ML_Bits_SHIFT (0U) 11020 /*! Bits - Hardware compare value (low byte) 11021 */ 11022 #define SPI_ML_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_ML_Bits_SHIFT)) & SPI_ML_Bits_MASK) 11023 /*! @} */ 11024 11025 /*! @name MH - SPI match register high */ 11026 /*! @{ */ 11027 11028 #define SPI_MH_Bits_MASK (0xFFU) 11029 #define SPI_MH_Bits_SHIFT (0U) 11030 /*! Bits - Hardware compare value (high byte) 11031 */ 11032 #define SPI_MH_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_MH_Bits_SHIFT)) & SPI_MH_Bits_MASK) 11033 /*! @} */ 11034 11035 /*! @name DL - SPI Data Register low */ 11036 /*! @{ */ 11037 11038 #define SPI_DL_Bits_MASK (0xFFU) 11039 #define SPI_DL_Bits_SHIFT (0U) 11040 /*! Bits - Data (low byte) 11041 */ 11042 #define SPI_DL_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_DL_Bits_SHIFT)) & SPI_DL_Bits_MASK) 11043 /*! @} */ 11044 11045 /*! @name DH - SPI data register high */ 11046 /*! @{ */ 11047 11048 #define SPI_DH_Bits_MASK (0xFFU) 11049 #define SPI_DH_Bits_SHIFT (0U) 11050 /*! Bits - Data (high byte) 11051 */ 11052 #define SPI_DH_Bits(x) (((uint8_t)(((uint8_t)(x)) << SPI_DH_Bits_SHIFT)) & SPI_DH_Bits_MASK) 11053 /*! @} */ 11054 11055 /*! @name CI - SPI clear interrupt register */ 11056 /*! @{ */ 11057 11058 #define SPI_CI_SPRFCI_MASK (0x1U) 11059 #define SPI_CI_SPRFCI_SHIFT (0U) 11060 /*! SPRFCI - Receive FIFO full flag clear interrupt 11061 */ 11062 #define SPI_CI_SPRFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_SPRFCI_SHIFT)) & SPI_CI_SPRFCI_MASK) 11063 11064 #define SPI_CI_SPTEFCI_MASK (0x2U) 11065 #define SPI_CI_SPTEFCI_SHIFT (1U) 11066 /*! SPTEFCI - Transmit FIFO empty flag clear interrupt 11067 */ 11068 #define SPI_CI_SPTEFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_SPTEFCI_SHIFT)) & SPI_CI_SPTEFCI_MASK) 11069 11070 #define SPI_CI_RNFULLFCI_MASK (0x4U) 11071 #define SPI_CI_RNFULLFCI_SHIFT (2U) 11072 /*! RNFULLFCI - Receive FIFO nearly full flag clear interrupt 11073 */ 11074 #define SPI_CI_RNFULLFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RNFULLFCI_SHIFT)) & SPI_CI_RNFULLFCI_MASK) 11075 11076 #define SPI_CI_TNEAREFCI_MASK (0x8U) 11077 #define SPI_CI_TNEAREFCI_SHIFT (3U) 11078 /*! TNEAREFCI - Transmit FIFO nearly empty flag clear interrupt 11079 */ 11080 #define SPI_CI_TNEAREFCI(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TNEAREFCI_SHIFT)) & SPI_CI_TNEAREFCI_MASK) 11081 11082 #define SPI_CI_RXFOF_MASK (0x10U) 11083 #define SPI_CI_RXFOF_SHIFT (4U) 11084 /*! RXFOF - Receive FIFO overflow flag 11085 * 0b0..Receive FIFO overflow condition has not occurred 11086 * 0b1..Receive FIFO overflow condition occurred 11087 */ 11088 #define SPI_CI_RXFOF(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RXFOF_SHIFT)) & SPI_CI_RXFOF_MASK) 11089 11090 #define SPI_CI_TXFOF_MASK (0x20U) 11091 #define SPI_CI_TXFOF_SHIFT (5U) 11092 /*! TXFOF - Transmit FIFO overflow flag 11093 * 0b0..Transmit FIFO overflow condition has not occurred 11094 * 0b1..Transmit FIFO overflow condition occurred 11095 */ 11096 #define SPI_CI_TXFOF(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TXFOF_SHIFT)) & SPI_CI_TXFOF_MASK) 11097 11098 #define SPI_CI_RXFERR_MASK (0x40U) 11099 #define SPI_CI_RXFERR_SHIFT (6U) 11100 /*! RXFERR - Receive FIFO error flag 11101 * 0b0..No receive FIFO error occurred 11102 * 0b1..A receive FIFO error occurred 11103 */ 11104 #define SPI_CI_RXFERR(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_RXFERR_SHIFT)) & SPI_CI_RXFERR_MASK) 11105 11106 #define SPI_CI_TXFERR_MASK (0x80U) 11107 #define SPI_CI_TXFERR_SHIFT (7U) 11108 /*! TXFERR - Transmit FIFO error flag 11109 * 0b0..No transmit FIFO error occurred 11110 * 0b1..A transmit FIFO error occurred 11111 */ 11112 #define SPI_CI_TXFERR(x) (((uint8_t)(((uint8_t)(x)) << SPI_CI_TXFERR_SHIFT)) & SPI_CI_TXFERR_MASK) 11113 /*! @} */ 11114 11115 /*! @name C3 - SPI control register 3 */ 11116 /*! @{ */ 11117 11118 #define SPI_C3_FIFOMODE_MASK (0x1U) 11119 #define SPI_C3_FIFOMODE_SHIFT (0U) 11120 /*! FIFOMODE - FIFO mode enable 11121 * 0b0..Buffer mode disabled 11122 * 0b1..Data available in the receive data buffer 11123 */ 11124 #define SPI_C3_FIFOMODE(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_FIFOMODE_SHIFT)) & SPI_C3_FIFOMODE_MASK) 11125 11126 #define SPI_C3_RNFULLIEN_MASK (0x2U) 11127 #define SPI_C3_RNFULLIEN_SHIFT (1U) 11128 /*! RNFULLIEN - Receive FIFO nearly full interrupt enable 11129 * 0b0..No interrupt upon RNFULLF being set 11130 * 0b1..Enable interrupts upon RNFULLF being set 11131 */ 11132 #define SPI_C3_RNFULLIEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_RNFULLIEN_SHIFT)) & SPI_C3_RNFULLIEN_MASK) 11133 11134 #define SPI_C3_TNEARIEN_MASK (0x4U) 11135 #define SPI_C3_TNEARIEN_SHIFT (2U) 11136 /*! TNEARIEN - Transmit FIFO nearly empty interrupt enable 11137 * 0b0..No interrupt upon TNEAREF being set 11138 * 0b1..Enable interrupts upon TNEAREF being set 11139 */ 11140 #define SPI_C3_TNEARIEN(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_TNEARIEN_SHIFT)) & SPI_C3_TNEARIEN_MASK) 11141 11142 #define SPI_C3_INTCLR_MASK (0x8U) 11143 #define SPI_C3_INTCLR_SHIFT (3U) 11144 /*! INTCLR - Interrupt clearing mechanism select 11145 * 0b0..These interrupts are cleared when the corresponding flags are cleared depending on the state of the FIFOs 11146 * 0b1..These interrupts are cleared by writing the corresponding bits in the CI register 11147 */ 11148 #define SPI_C3_INTCLR(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_INTCLR_SHIFT)) & SPI_C3_INTCLR_MASK) 11149 11150 #define SPI_C3_RNFULLF_MARK_MASK (0x10U) 11151 #define SPI_C3_RNFULLF_MARK_SHIFT (4U) 11152 /*! RNFULLF_MARK - Receive FIFO nearly full watermark 11153 * 0b0..RNFULLF is set when the receive FIFO has 48 bits or more 11154 * 0b1..RNFULLF is set when the receive FIFO has 32 bits or more 11155 */ 11156 #define SPI_C3_RNFULLF_MARK(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_RNFULLF_MARK_SHIFT)) & SPI_C3_RNFULLF_MARK_MASK) 11157 11158 #define SPI_C3_TNEAREF_MARK_MASK (0x20U) 11159 #define SPI_C3_TNEAREF_MARK_SHIFT (5U) 11160 /*! TNEAREF_MARK - Transmit FIFO nearly empty watermark 11161 * 0b0..TNEAREF is set when the transmit FIFO has 16 bits or less 11162 * 0b1..TNEAREF is set when the transmit FIFO has 32 bits or less 11163 */ 11164 #define SPI_C3_TNEAREF_MARK(x) (((uint8_t)(((uint8_t)(x)) << SPI_C3_TNEAREF_MARK_SHIFT)) & SPI_C3_TNEAREF_MARK_MASK) 11165 /*! @} */ 11166 11167 11168 /*! 11169 * @} 11170 */ /* end of group SPI_Register_Masks */ 11171 11172 11173 /* SPI - Peripheral instance base addresses */ 11174 /** Peripheral SPI0 base address */ 11175 #define SPI0_BASE (0x40075000u) 11176 /** Peripheral SPI0 base pointer */ 11177 #define SPI0 ((SPI_Type *)SPI0_BASE) 11178 /** Peripheral SPI1 base address */ 11179 #define SPI1_BASE (0x40076000u) 11180 /** Peripheral SPI1 base pointer */ 11181 #define SPI1 ((SPI_Type *)SPI1_BASE) 11182 /** Array initializer of SPI peripheral base addresses */ 11183 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE } 11184 /** Array initializer of SPI peripheral base pointers */ 11185 #define SPI_BASE_PTRS { SPI0, SPI1 } 11186 /** Interrupt vectors for the SPI peripheral type */ 11187 #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn } 11188 11189 /*! 11190 * @} 11191 */ /* end of group SPI_Peripheral_Access_Layer */ 11192 11193 11194 /* ---------------------------------------------------------------------------- 11195 -- SYSMPU Peripheral Access Layer 11196 ---------------------------------------------------------------------------- */ 11197 11198 /*! 11199 * @addtogroup SYSMPU_Peripheral_Access_Layer SYSMPU Peripheral Access Layer 11200 * @{ 11201 */ 11202 11203 /** SYSMPU - Register Layout Typedef */ 11204 typedef struct { 11205 __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */ 11206 uint8_t RESERVED_0[12]; 11207 struct { /* offset: 0x10, array step: 0x8 */ 11208 __I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */ 11209 __I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */ 11210 } SP[2]; 11211 uint8_t RESERVED_1[992]; 11212 __IO uint32_t WORD[8][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */ 11213 uint8_t RESERVED_2[896]; 11214 __IO uint32_t RGDAAC[8]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */ 11215 } SYSMPU_Type; 11216 11217 /* ---------------------------------------------------------------------------- 11218 -- SYSMPU Register Masks 11219 ---------------------------------------------------------------------------- */ 11220 11221 /*! 11222 * @addtogroup SYSMPU_Register_Masks SYSMPU Register Masks 11223 * @{ 11224 */ 11225 11226 /*! @name CESR - Control/Error Status Register */ 11227 /*! @{ */ 11228 11229 #define SYSMPU_CESR_VLD_MASK (0x1U) 11230 #define SYSMPU_CESR_VLD_SHIFT (0U) 11231 /*! VLD - Valid 11232 * 0b0..MPU is disabled. All accesses from all bus masters are allowed. 11233 * 0b1..MPU is enabled 11234 */ 11235 #define SYSMPU_CESR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_VLD_SHIFT)) & SYSMPU_CESR_VLD_MASK) 11236 11237 #define SYSMPU_CESR_NRGD_MASK (0xF00U) 11238 #define SYSMPU_CESR_NRGD_SHIFT (8U) 11239 /*! NRGD - Number Of Region Descriptors 11240 * 0b0000..8 region descriptors 11241 * 0b0001..12 region descriptors 11242 * 0b0010..16 region descriptors 11243 */ 11244 #define SYSMPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK) 11245 11246 #define SYSMPU_CESR_NSP_MASK (0xF000U) 11247 #define SYSMPU_CESR_NSP_SHIFT (12U) 11248 /*! NSP - Number Of Slave Ports 11249 */ 11250 #define SYSMPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NSP_SHIFT)) & SYSMPU_CESR_NSP_MASK) 11251 11252 #define SYSMPU_CESR_HRL_MASK (0xF0000U) 11253 #define SYSMPU_CESR_HRL_SHIFT (16U) 11254 /*! HRL - Hardware Revision Level 11255 */ 11256 #define SYSMPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_HRL_SHIFT)) & SYSMPU_CESR_HRL_MASK) 11257 11258 #define SYSMPU_CESR_SPERR_MASK (0xC0000000U) 11259 #define SYSMPU_CESR_SPERR_SHIFT (30U) 11260 /*! SPERR - Slave Port n Error 11261 * 0b00..No error has occurred for slave port n. 11262 * 0b01..An error has occurred for slave port n. 11263 */ 11264 #define SYSMPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK) 11265 /*! @} */ 11266 11267 /*! @name EAR - Error Address Register, slave port n */ 11268 /*! @{ */ 11269 11270 #define SYSMPU_EAR_EADDR_MASK (0xFFFFFFFFU) 11271 #define SYSMPU_EAR_EADDR_SHIFT (0U) 11272 /*! EADDR - Error Address 11273 */ 11274 #define SYSMPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EAR_EADDR_SHIFT)) & SYSMPU_EAR_EADDR_MASK) 11275 /*! @} */ 11276 11277 /* The count of SYSMPU_EAR */ 11278 #define SYSMPU_EAR_COUNT (2U) 11279 11280 /*! @name EDR - Error Detail Register, slave port n */ 11281 /*! @{ */ 11282 11283 #define SYSMPU_EDR_ERW_MASK (0x1U) 11284 #define SYSMPU_EDR_ERW_SHIFT (0U) 11285 /*! ERW - Error Read/Write 11286 * 0b0..Read 11287 * 0b1..Write 11288 */ 11289 #define SYSMPU_EDR_ERW(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_ERW_SHIFT)) & SYSMPU_EDR_ERW_MASK) 11290 11291 #define SYSMPU_EDR_EATTR_MASK (0xEU) 11292 #define SYSMPU_EDR_EATTR_SHIFT (1U) 11293 /*! EATTR - Error Attributes 11294 * 0b000..User mode, instruction access 11295 * 0b001..User mode, data access 11296 * 0b010..Supervisor mode, instruction access 11297 * 0b011..Supervisor mode, data access 11298 */ 11299 #define SYSMPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK) 11300 11301 #define SYSMPU_EDR_EMN_MASK (0xF0U) 11302 #define SYSMPU_EDR_EMN_SHIFT (4U) 11303 /*! EMN - Error Master Number 11304 */ 11305 #define SYSMPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EMN_SHIFT)) & SYSMPU_EDR_EMN_MASK) 11306 11307 #define SYSMPU_EDR_EPID_MASK (0xFF00U) 11308 #define SYSMPU_EDR_EPID_SHIFT (8U) 11309 /*! EPID - Error Process Identification 11310 */ 11311 #define SYSMPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EPID_SHIFT)) & SYSMPU_EDR_EPID_MASK) 11312 11313 #define SYSMPU_EDR_EACD_MASK (0xFFFF0000U) 11314 #define SYSMPU_EDR_EACD_SHIFT (16U) 11315 /*! EACD - Error Access Control Detail 11316 */ 11317 #define SYSMPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EACD_SHIFT)) & SYSMPU_EDR_EACD_MASK) 11318 /*! @} */ 11319 11320 /* The count of SYSMPU_EDR */ 11321 #define SYSMPU_EDR_COUNT (2U) 11322 11323 /*! @name WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3 */ 11324 /*! @{ */ 11325 11326 #define SYSMPU_WORD_M0UM_MASK (0x7U) 11327 #define SYSMPU_WORD_M0UM_SHIFT (0U) 11328 /*! M0UM - Bus Master 0 User Mode Access Control 11329 */ 11330 #define SYSMPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0UM_SHIFT)) & SYSMPU_WORD_M0UM_MASK) 11331 11332 #define SYSMPU_WORD_VLD_MASK (0x1U) 11333 #define SYSMPU_WORD_VLD_SHIFT (0U) 11334 /*! VLD - Valid 11335 * 0b0..Region descriptor is invalid 11336 * 0b1..Region descriptor is valid 11337 */ 11338 #define SYSMPU_WORD_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK) 11339 11340 #define SYSMPU_WORD_M0SM_MASK (0x18U) 11341 #define SYSMPU_WORD_M0SM_SHIFT (3U) 11342 /*! M0SM - Bus Master 0 Supervisor Mode Access Control 11343 */ 11344 #define SYSMPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0SM_SHIFT)) & SYSMPU_WORD_M0SM_MASK) 11345 11346 #define SYSMPU_WORD_ENDADDR_MASK (0xFFFFFFE0U) 11347 #define SYSMPU_WORD_ENDADDR_SHIFT (5U) 11348 /*! ENDADDR - End Address 11349 */ 11350 #define SYSMPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_ENDADDR_SHIFT)) & SYSMPU_WORD_ENDADDR_MASK) 11351 11352 #define SYSMPU_WORD_M0PE_MASK (0x20U) 11353 #define SYSMPU_WORD_M0PE_SHIFT (5U) 11354 /*! M0PE - Bus Master 0 Process Identifier enable 11355 */ 11356 #define SYSMPU_WORD_M0PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0PE_SHIFT)) & SYSMPU_WORD_M0PE_MASK) 11357 11358 #define SYSMPU_WORD_SRTADDR_MASK (0xFFFFFFE0U) 11359 #define SYSMPU_WORD_SRTADDR_SHIFT (5U) 11360 /*! SRTADDR - Start Address 11361 */ 11362 #define SYSMPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_SRTADDR_SHIFT)) & SYSMPU_WORD_SRTADDR_MASK) 11363 11364 #define SYSMPU_WORD_M1UM_MASK (0x1C0U) 11365 #define SYSMPU_WORD_M1UM_SHIFT (6U) 11366 /*! M1UM - Bus Master 1 User Mode Access Control 11367 */ 11368 #define SYSMPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1UM_SHIFT)) & SYSMPU_WORD_M1UM_MASK) 11369 11370 #define SYSMPU_WORD_M1SM_MASK (0x600U) 11371 #define SYSMPU_WORD_M1SM_SHIFT (9U) 11372 /*! M1SM - Bus Master 1 Supervisor Mode Access Control 11373 */ 11374 #define SYSMPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1SM_SHIFT)) & SYSMPU_WORD_M1SM_MASK) 11375 11376 #define SYSMPU_WORD_M1PE_MASK (0x800U) 11377 #define SYSMPU_WORD_M1PE_SHIFT (11U) 11378 /*! M1PE - Bus Master 1 Process Identifier enable 11379 */ 11380 #define SYSMPU_WORD_M1PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1PE_SHIFT)) & SYSMPU_WORD_M1PE_MASK) 11381 11382 #define SYSMPU_WORD_M2UM_MASK (0x7000U) 11383 #define SYSMPU_WORD_M2UM_SHIFT (12U) 11384 /*! M2UM - Bus Master 2 User Mode Access control 11385 */ 11386 #define SYSMPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2UM_SHIFT)) & SYSMPU_WORD_M2UM_MASK) 11387 11388 #define SYSMPU_WORD_M2SM_MASK (0x18000U) 11389 #define SYSMPU_WORD_M2SM_SHIFT (15U) 11390 /*! M2SM - Bus Master 2 Supervisor Mode Access Control 11391 */ 11392 #define SYSMPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2SM_SHIFT)) & SYSMPU_WORD_M2SM_MASK) 11393 11394 #define SYSMPU_WORD_PIDMASK_MASK (0xFF0000U) 11395 #define SYSMPU_WORD_PIDMASK_SHIFT (16U) 11396 /*! PIDMASK - Process Identifier Mask 11397 */ 11398 #define SYSMPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PIDMASK_SHIFT)) & SYSMPU_WORD_PIDMASK_MASK) 11399 11400 #define SYSMPU_WORD_M2PE_MASK (0x20000U) 11401 #define SYSMPU_WORD_M2PE_SHIFT (17U) 11402 /*! M2PE - Bus Master 2 Process Identifier Enable 11403 */ 11404 #define SYSMPU_WORD_M2PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2PE_SHIFT)) & SYSMPU_WORD_M2PE_MASK) 11405 11406 #define SYSMPU_WORD_M3UM_MASK (0x1C0000U) 11407 #define SYSMPU_WORD_M3UM_SHIFT (18U) 11408 /*! M3UM - Bus Master 3 User Mode Access Control 11409 * 0b000..An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. 11410 * 0b001..Allows the given access type to occur 11411 */ 11412 #define SYSMPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK) 11413 11414 #define SYSMPU_WORD_M3SM_MASK (0x600000U) 11415 #define SYSMPU_WORD_M3SM_SHIFT (21U) 11416 /*! M3SM - Bus Master 3 Supervisor Mode Access Control 11417 * 0b00..r/w/x; read, write and execute allowed 11418 * 0b01..r/x; read and execute allowed, but no write 11419 * 0b10..r/w; read and write allowed, but no execute 11420 * 0b11..Same as User mode defined in M3UM 11421 */ 11422 #define SYSMPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK) 11423 11424 #define SYSMPU_WORD_M3PE_MASK (0x800000U) 11425 #define SYSMPU_WORD_M3PE_SHIFT (23U) 11426 /*! M3PE - Bus Master 3 Process Identifier Enable 11427 * 0b0..Do not include the process identifier in the evaluation 11428 * 0b1..Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation 11429 */ 11430 #define SYSMPU_WORD_M3PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3PE_SHIFT)) & SYSMPU_WORD_M3PE_MASK) 11431 11432 #define SYSMPU_WORD_M4WE_MASK (0x1000000U) 11433 #define SYSMPU_WORD_M4WE_SHIFT (24U) 11434 /*! M4WE - Bus Master 4 Write Enable 11435 * 0b0..Bus master 4 writes terminate with an access error and the write is not performed 11436 * 0b1..Bus master 4 writes allowed 11437 */ 11438 #define SYSMPU_WORD_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK) 11439 11440 #define SYSMPU_WORD_PID_MASK (0xFF000000U) 11441 #define SYSMPU_WORD_PID_SHIFT (24U) 11442 /*! PID - Process Identifier 11443 */ 11444 #define SYSMPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PID_SHIFT)) & SYSMPU_WORD_PID_MASK) 11445 11446 #define SYSMPU_WORD_M4RE_MASK (0x2000000U) 11447 #define SYSMPU_WORD_M4RE_SHIFT (25U) 11448 /*! M4RE - Bus Master 4 Read Enable 11449 * 0b0..Bus master 4 reads terminate with an access error and the read is not performed 11450 * 0b1..Bus master 4 reads allowed 11451 */ 11452 #define SYSMPU_WORD_M4RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4RE_SHIFT)) & SYSMPU_WORD_M4RE_MASK) 11453 11454 #define SYSMPU_WORD_M5WE_MASK (0x4000000U) 11455 #define SYSMPU_WORD_M5WE_SHIFT (26U) 11456 /*! M5WE - Bus Master 5 Write Enable 11457 * 0b0..Bus master 5 writes terminate with an access error and the write is not performed 11458 * 0b1..Bus master 5 writes allowed 11459 */ 11460 #define SYSMPU_WORD_M5WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5WE_SHIFT)) & SYSMPU_WORD_M5WE_MASK) 11461 11462 #define SYSMPU_WORD_M5RE_MASK (0x8000000U) 11463 #define SYSMPU_WORD_M5RE_SHIFT (27U) 11464 /*! M5RE - Bus Master 5 Read Enable 11465 * 0b0..Bus master 5 reads terminate with an access error and the read is not performed 11466 * 0b1..Bus master 5 reads allowed 11467 */ 11468 #define SYSMPU_WORD_M5RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5RE_SHIFT)) & SYSMPU_WORD_M5RE_MASK) 11469 11470 #define SYSMPU_WORD_M6WE_MASK (0x10000000U) 11471 #define SYSMPU_WORD_M6WE_SHIFT (28U) 11472 /*! M6WE - Bus Master 6 Write Enable 11473 * 0b0..Bus master 6 writes terminate with an access error and the write is not performed 11474 * 0b1..Bus master 6 writes allowed 11475 */ 11476 #define SYSMPU_WORD_M6WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6WE_SHIFT)) & SYSMPU_WORD_M6WE_MASK) 11477 11478 #define SYSMPU_WORD_M6RE_MASK (0x20000000U) 11479 #define SYSMPU_WORD_M6RE_SHIFT (29U) 11480 /*! M6RE - Bus Master 6 Read Enable 11481 * 0b0..Bus master 6 reads terminate with an access error and the read is not performed 11482 * 0b1..Bus master 6 reads allowed 11483 */ 11484 #define SYSMPU_WORD_M6RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6RE_SHIFT)) & SYSMPU_WORD_M6RE_MASK) 11485 11486 #define SYSMPU_WORD_M7WE_MASK (0x40000000U) 11487 #define SYSMPU_WORD_M7WE_SHIFT (30U) 11488 /*! M7WE - Bus Master 7 Write Enable 11489 * 0b0..Bus master 7 writes terminate with an access error and the write is not performed 11490 * 0b1..Bus master 7 writes allowed 11491 */ 11492 #define SYSMPU_WORD_M7WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7WE_SHIFT)) & SYSMPU_WORD_M7WE_MASK) 11493 11494 #define SYSMPU_WORD_M7RE_MASK (0x80000000U) 11495 #define SYSMPU_WORD_M7RE_SHIFT (31U) 11496 /*! M7RE - Bus Master 7 Read Enable 11497 * 0b0..Bus master 7 reads terminate with an access error and the read is not performed 11498 * 0b1..Bus master 7 reads allowed 11499 */ 11500 #define SYSMPU_WORD_M7RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7RE_SHIFT)) & SYSMPU_WORD_M7RE_MASK) 11501 /*! @} */ 11502 11503 /* The count of SYSMPU_WORD */ 11504 #define SYSMPU_WORD_COUNT (8U) 11505 11506 /* The count of SYSMPU_WORD */ 11507 #define SYSMPU_WORD_COUNT2 (4U) 11508 11509 /*! @name RGDAAC - Region Descriptor Alternate Access Control n */ 11510 /*! @{ */ 11511 11512 #define SYSMPU_RGDAAC_M0UM_MASK (0x7U) 11513 #define SYSMPU_RGDAAC_M0UM_SHIFT (0U) 11514 /*! M0UM - Bus Master 0 User Mode Access Control 11515 */ 11516 #define SYSMPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0UM_SHIFT)) & SYSMPU_RGDAAC_M0UM_MASK) 11517 11518 #define SYSMPU_RGDAAC_M0SM_MASK (0x18U) 11519 #define SYSMPU_RGDAAC_M0SM_SHIFT (3U) 11520 /*! M0SM - Bus Master 0 Supervisor Mode Access Control 11521 */ 11522 #define SYSMPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0SM_SHIFT)) & SYSMPU_RGDAAC_M0SM_MASK) 11523 11524 #define SYSMPU_RGDAAC_M0PE_MASK (0x20U) 11525 #define SYSMPU_RGDAAC_M0PE_SHIFT (5U) 11526 /*! M0PE - Bus Master 0 Process Identifier Enable 11527 */ 11528 #define SYSMPU_RGDAAC_M0PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0PE_SHIFT)) & SYSMPU_RGDAAC_M0PE_MASK) 11529 11530 #define SYSMPU_RGDAAC_M1UM_MASK (0x1C0U) 11531 #define SYSMPU_RGDAAC_M1UM_SHIFT (6U) 11532 /*! M1UM - Bus Master 1 User Mode Access Control 11533 */ 11534 #define SYSMPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1UM_SHIFT)) & SYSMPU_RGDAAC_M1UM_MASK) 11535 11536 #define SYSMPU_RGDAAC_M1SM_MASK (0x600U) 11537 #define SYSMPU_RGDAAC_M1SM_SHIFT (9U) 11538 /*! M1SM - Bus Master 1 Supervisor Mode Access Control 11539 */ 11540 #define SYSMPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1SM_SHIFT)) & SYSMPU_RGDAAC_M1SM_MASK) 11541 11542 #define SYSMPU_RGDAAC_M1PE_MASK (0x800U) 11543 #define SYSMPU_RGDAAC_M1PE_SHIFT (11U) 11544 /*! M1PE - Bus Master 1 Process Identifier Enable 11545 */ 11546 #define SYSMPU_RGDAAC_M1PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1PE_SHIFT)) & SYSMPU_RGDAAC_M1PE_MASK) 11547 11548 #define SYSMPU_RGDAAC_M2UM_MASK (0x7000U) 11549 #define SYSMPU_RGDAAC_M2UM_SHIFT (12U) 11550 /*! M2UM - Bus Master 2 User Mode Access Control 11551 */ 11552 #define SYSMPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2UM_SHIFT)) & SYSMPU_RGDAAC_M2UM_MASK) 11553 11554 #define SYSMPU_RGDAAC_M2SM_MASK (0x18000U) 11555 #define SYSMPU_RGDAAC_M2SM_SHIFT (15U) 11556 /*! M2SM - Bus Master 2 Supervisor Mode Access Control 11557 */ 11558 #define SYSMPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2SM_SHIFT)) & SYSMPU_RGDAAC_M2SM_MASK) 11559 11560 #define SYSMPU_RGDAAC_M2PE_MASK (0x20000U) 11561 #define SYSMPU_RGDAAC_M2PE_SHIFT (17U) 11562 /*! M2PE - Bus Master 2 Process Identifier Enable 11563 */ 11564 #define SYSMPU_RGDAAC_M2PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2PE_SHIFT)) & SYSMPU_RGDAAC_M2PE_MASK) 11565 11566 #define SYSMPU_RGDAAC_M3UM_MASK (0x1C0000U) 11567 #define SYSMPU_RGDAAC_M3UM_SHIFT (18U) 11568 /*! M3UM - Bus Master 3 User Mode Access Control 11569 * 0b000..An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. 11570 * 0b001..Allows the given access type to occur 11571 */ 11572 #define SYSMPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK) 11573 11574 #define SYSMPU_RGDAAC_M3SM_MASK (0x600000U) 11575 #define SYSMPU_RGDAAC_M3SM_SHIFT (21U) 11576 /*! M3SM - Bus Master 3 Supervisor Mode Access Control 11577 * 0b00..r/w/x; read, write and execute allowed 11578 * 0b01..r/x; read and execute allowed, but no write 11579 * 0b10..r/w; read and write allowed, but no execute 11580 * 0b11..Same as User mode defined in M3UM 11581 */ 11582 #define SYSMPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK) 11583 11584 #define SYSMPU_RGDAAC_M3PE_MASK (0x800000U) 11585 #define SYSMPU_RGDAAC_M3PE_SHIFT (23U) 11586 /*! M3PE - Bus Master 3 Process Identifier Enable 11587 * 0b0..Do not include the process identifier in the evaluation 11588 * 0b1..Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation 11589 */ 11590 #define SYSMPU_RGDAAC_M3PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3PE_SHIFT)) & SYSMPU_RGDAAC_M3PE_MASK) 11591 11592 #define SYSMPU_RGDAAC_M4WE_MASK (0x1000000U) 11593 #define SYSMPU_RGDAAC_M4WE_SHIFT (24U) 11594 /*! M4WE - Bus Master 4 Write Enable 11595 * 0b0..Bus master 4 writes terminate with an access error and the write is not performed 11596 * 0b1..Bus master 4 writes allowed 11597 */ 11598 #define SYSMPU_RGDAAC_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4WE_SHIFT)) & SYSMPU_RGDAAC_M4WE_MASK) 11599 11600 #define SYSMPU_RGDAAC_M4RE_MASK (0x2000000U) 11601 #define SYSMPU_RGDAAC_M4RE_SHIFT (25U) 11602 /*! M4RE - Bus Master 4 Read Enable 11603 * 0b0..Bus master 4 reads terminate with an access error and the read is not performed 11604 * 0b1..Bus master 4 reads allowed 11605 */ 11606 #define SYSMPU_RGDAAC_M4RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4RE_SHIFT)) & SYSMPU_RGDAAC_M4RE_MASK) 11607 11608 #define SYSMPU_RGDAAC_M5WE_MASK (0x4000000U) 11609 #define SYSMPU_RGDAAC_M5WE_SHIFT (26U) 11610 /*! M5WE - Bus Master 5 Write Enable 11611 * 0b0..Bus master 5 writes terminate with an access error and the write is not performed 11612 * 0b1..Bus master 5 writes allowed 11613 */ 11614 #define SYSMPU_RGDAAC_M5WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5WE_SHIFT)) & SYSMPU_RGDAAC_M5WE_MASK) 11615 11616 #define SYSMPU_RGDAAC_M5RE_MASK (0x8000000U) 11617 #define SYSMPU_RGDAAC_M5RE_SHIFT (27U) 11618 /*! M5RE - Bus Master 5 Read Enable 11619 * 0b0..Bus master 5 reads terminate with an access error and the read is not performed 11620 * 0b1..Bus master 5 reads allowed 11621 */ 11622 #define SYSMPU_RGDAAC_M5RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5RE_SHIFT)) & SYSMPU_RGDAAC_M5RE_MASK) 11623 11624 #define SYSMPU_RGDAAC_M6WE_MASK (0x10000000U) 11625 #define SYSMPU_RGDAAC_M6WE_SHIFT (28U) 11626 /*! M6WE - Bus Master 6 Write Enable 11627 * 0b0..Bus master 6 writes terminate with an access error and the write is not performed 11628 * 0b1..Bus master 6 writes allowed 11629 */ 11630 #define SYSMPU_RGDAAC_M6WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6WE_SHIFT)) & SYSMPU_RGDAAC_M6WE_MASK) 11631 11632 #define SYSMPU_RGDAAC_M6RE_MASK (0x20000000U) 11633 #define SYSMPU_RGDAAC_M6RE_SHIFT (29U) 11634 /*! M6RE - Bus Master 6 Read Enable 11635 * 0b0..Bus master 6 reads terminate with an access error and the read is not performed 11636 * 0b1..Bus master 6 reads allowed 11637 */ 11638 #define SYSMPU_RGDAAC_M6RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6RE_SHIFT)) & SYSMPU_RGDAAC_M6RE_MASK) 11639 11640 #define SYSMPU_RGDAAC_M7WE_MASK (0x40000000U) 11641 #define SYSMPU_RGDAAC_M7WE_SHIFT (30U) 11642 /*! M7WE - Bus Master 7 Write Enable 11643 * 0b0..Bus master 7 writes terminate with an access error and the write is not performed 11644 * 0b1..Bus master 7 writes allowed 11645 */ 11646 #define SYSMPU_RGDAAC_M7WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7WE_SHIFT)) & SYSMPU_RGDAAC_M7WE_MASK) 11647 11648 #define SYSMPU_RGDAAC_M7RE_MASK (0x80000000U) 11649 #define SYSMPU_RGDAAC_M7RE_SHIFT (31U) 11650 /*! M7RE - Bus Master 7 Read Enable 11651 * 0b0..Bus master 7 reads terminate with an access error and the read is not performed 11652 * 0b1..Bus master 7 reads allowed 11653 */ 11654 #define SYSMPU_RGDAAC_M7RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7RE_SHIFT)) & SYSMPU_RGDAAC_M7RE_MASK) 11655 /*! @} */ 11656 11657 /* The count of SYSMPU_RGDAAC */ 11658 #define SYSMPU_RGDAAC_COUNT (8U) 11659 11660 11661 /*! 11662 * @} 11663 */ /* end of group SYSMPU_Register_Masks */ 11664 11665 11666 /* SYSMPU - Peripheral instance base addresses */ 11667 /** Peripheral SYSMPU base address */ 11668 #define SYSMPU_BASE (0x4000A000u) 11669 /** Peripheral SYSMPU base pointer */ 11670 #define SYSMPU ((SYSMPU_Type *)SYSMPU_BASE) 11671 /** Array initializer of SYSMPU peripheral base addresses */ 11672 #define SYSMPU_BASE_ADDRS { SYSMPU_BASE } 11673 /** Array initializer of SYSMPU peripheral base pointers */ 11674 #define SYSMPU_BASE_PTRS { SYSMPU } 11675 11676 /*! 11677 * @} 11678 */ /* end of group SYSMPU_Peripheral_Access_Layer */ 11679 11680 11681 /* ---------------------------------------------------------------------------- 11682 -- TMR Peripheral Access Layer 11683 ---------------------------------------------------------------------------- */ 11684 11685 /*! 11686 * @addtogroup TMR_Peripheral_Access_Layer TMR Peripheral Access Layer 11687 * @{ 11688 */ 11689 11690 /** TMR - Register Layout Typedef */ 11691 typedef struct { 11692 __IO uint16_t COMP1; /**< Timer Channel Compare Register 1, offset: 0x0 */ 11693 __IO uint16_t COMP2; /**< Timer Channel Compare Register 2, offset: 0x2 */ 11694 __IO uint16_t CAPT; /**< Timer Channel Capture Register, offset: 0x4 */ 11695 __IO uint16_t LOAD; /**< Timer Channel Load Register, offset: 0x6 */ 11696 __IO uint16_t HOLD; /**< Timer Channel Hold Register, offset: 0x8 */ 11697 __IO uint16_t CNTR; /**< Timer Channel Counter Register, offset: 0xA */ 11698 __IO uint16_t CTRL; /**< Timer Channel Control Register, offset: 0xC */ 11699 __IO uint16_t SCTRL; /**< Timer Channel Status and Control Register, offset: 0xE */ 11700 __IO uint16_t CMPLD1; /**< Timer Channel Comparator Load Register 1, offset: 0x10 */ 11701 __IO uint16_t CMPLD2; /**< Timer Channel Comparator Load Register 2, offset: 0x12 */ 11702 __IO uint16_t CSCTRL; /**< Timer Channel Comparator Status and Control Register, offset: 0x14 */ 11703 __IO uint16_t FILT; /**< Timer Channel Input Filter Register, offset: 0x16 */ 11704 uint8_t RESERVED_0[6]; 11705 __IO uint16_t ENBL; /**< Timer Channel Enable Register, offset: 0x1E */ 11706 } TMR_Type; 11707 11708 /* ---------------------------------------------------------------------------- 11709 -- TMR Register Masks 11710 ---------------------------------------------------------------------------- */ 11711 11712 /*! 11713 * @addtogroup TMR_Register_Masks TMR Register Masks 11714 * @{ 11715 */ 11716 11717 /*! @name COMP1 - Timer Channel Compare Register 1 */ 11718 /*! @{ */ 11719 11720 #define TMR_COMP1_COMPARISON_1_MASK (0xFFFFU) 11721 #define TMR_COMP1_COMPARISON_1_SHIFT (0U) 11722 /*! COMPARISON_1 - Comparison Value 1 11723 */ 11724 #define TMR_COMP1_COMPARISON_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK) 11725 /*! @} */ 11726 11727 /*! @name COMP2 - Timer Channel Compare Register 2 */ 11728 /*! @{ */ 11729 11730 #define TMR_COMP2_COMPARISON_2_MASK (0xFFFFU) 11731 #define TMR_COMP2_COMPARISON_2_SHIFT (0U) 11732 /*! COMPARISON_2 - Comparison Value 2 11733 */ 11734 #define TMR_COMP2_COMPARISON_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK) 11735 /*! @} */ 11736 11737 /*! @name CAPT - Timer Channel Capture Register */ 11738 /*! @{ */ 11739 11740 #define TMR_CAPT_CAPTURE_MASK (0xFFFFU) 11741 #define TMR_CAPT_CAPTURE_SHIFT (0U) 11742 /*! CAPTURE - Capture Value 11743 */ 11744 #define TMR_CAPT_CAPTURE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK) 11745 /*! @} */ 11746 11747 /*! @name LOAD - Timer Channel Load Register */ 11748 /*! @{ */ 11749 11750 #define TMR_LOAD_LOAD_MASK (0xFFFFU) 11751 #define TMR_LOAD_LOAD_SHIFT (0U) 11752 /*! LOAD - Timer Load Register 11753 */ 11754 #define TMR_LOAD_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK) 11755 /*! @} */ 11756 11757 /*! @name HOLD - Timer Channel Hold Register */ 11758 /*! @{ */ 11759 11760 #define TMR_HOLD_HOLD_MASK (0xFFFFU) 11761 #define TMR_HOLD_HOLD_SHIFT (0U) 11762 #define TMR_HOLD_HOLD(x) (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK) 11763 /*! @} */ 11764 11765 /*! @name CNTR - Timer Channel Counter Register */ 11766 /*! @{ */ 11767 11768 #define TMR_CNTR_COUNTER_MASK (0xFFFFU) 11769 #define TMR_CNTR_COUNTER_SHIFT (0U) 11770 #define TMR_CNTR_COUNTER(x) (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK) 11771 /*! @} */ 11772 11773 /*! @name CTRL - Timer Channel Control Register */ 11774 /*! @{ */ 11775 11776 #define TMR_CTRL_OUTMODE_MASK (0x7U) 11777 #define TMR_CTRL_OUTMODE_SHIFT (0U) 11778 /*! OUTMODE - Output Mode 11779 * 0b000..Asserted while counter is active 11780 * 0b001..Clear OFLAG output on successful compare 11781 * 0b010..Set OFLAG output on successful compare 11782 * 0b011..Toggle OFLAG output on successful compare 11783 * 0b100..Toggle OFLAG output using alternating compare registers 11784 * 0b101..Set on compare, cleared on secondary source input edge 11785 * 0b110..Set on compare, cleared on counter rollover 11786 * 0b111..Enable gated clock output while counter is active 11787 */ 11788 #define TMR_CTRL_OUTMODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK) 11789 11790 #define TMR_CTRL_COINIT_MASK (0x8U) 11791 #define TMR_CTRL_COINIT_SHIFT (3U) 11792 /*! COINIT - Co-Channel Initialization 11793 * 0b0..Co-channel counter/timers cannot force a re-initialization of this counter/timer 11794 * 0b1..Co-channel counter/timers may force a re-initialization of this counter/timer 11795 */ 11796 #define TMR_CTRL_COINIT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK) 11797 11798 #define TMR_CTRL_DIR_MASK (0x10U) 11799 #define TMR_CTRL_DIR_SHIFT (4U) 11800 /*! DIR - Count Direction 11801 * 0b0..Count up. 11802 * 0b1..Count down. 11803 */ 11804 #define TMR_CTRL_DIR(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK) 11805 11806 #define TMR_CTRL_LENGTH_MASK (0x20U) 11807 #define TMR_CTRL_LENGTH_SHIFT (5U) 11808 /*! LENGTH - Count Length 11809 * 0b0..Roll over. 11810 * 0b1..Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter 11811 * reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. 11812 * When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful 11813 * comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 11814 * value is reached, re-initializes, counts until COMP1 value is reached, and so on. 11815 */ 11816 #define TMR_CTRL_LENGTH(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK) 11817 11818 #define TMR_CTRL_ONCE_MASK (0x40U) 11819 #define TMR_CTRL_ONCE_SHIFT (6U) 11820 /*! ONCE - Count Once 11821 * 0b0..Count repeatedly. 11822 * 0b1..Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a 11823 * COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When 11824 * output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to 11825 * the COMP2 value, and then stops. 11826 */ 11827 #define TMR_CTRL_ONCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK) 11828 11829 #define TMR_CTRL_SCS_MASK (0x180U) 11830 #define TMR_CTRL_SCS_SHIFT (7U) 11831 /*! SCS - Secondary Count Source 11832 * 0b00..Counter 0 input pin 11833 * 0b01..Counter 1 input pin 11834 * 0b10..Counter 2 input pin 11835 * 0b11..Counter 3 input pin 11836 */ 11837 #define TMR_CTRL_SCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK) 11838 11839 #define TMR_CTRL_PCS_MASK (0x1E00U) 11840 #define TMR_CTRL_PCS_SHIFT (9U) 11841 /*! PCS - Primary Count Source 11842 * 0b0000..Counter 0 input pin 11843 * 0b0001..Counter 1 input pin 11844 * 0b0010..Counter 2 input pin 11845 * 0b0011..Counter 3 input pin 11846 * 0b0100..Counter 0 output 11847 * 0b0101..Counter 1 output 11848 * 0b0110..Counter 2 output 11849 * 0b0111..Counter 3 output 11850 * 0b1000..IP bus clock divide by 1 prescaler 11851 * 0b1001..IP bus clock divide by 2 prescaler 11852 * 0b1010..IP bus clock divide by 4 prescaler 11853 * 0b1011..IP bus clock divide by 8 prescaler 11854 * 0b1100..IP bus clock divide by 16 prescaler 11855 * 0b1101..IP bus clock divide by 32 prescaler 11856 * 0b1110..IP bus clock divide by 64 prescaler 11857 * 0b1111..IP bus clock divide by 128 prescaler 11858 */ 11859 #define TMR_CTRL_PCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK) 11860 11861 #define TMR_CTRL_CM_MASK (0xE000U) 11862 #define TMR_CTRL_CM_SHIFT (13U) 11863 /*! CM - Count Mode 11864 * 0b000..No operation 11865 * 0b001..Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges 11866 * are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising 11867 * edges are counted regardless of the value of SCTRL[IPS]. 11868 * 0b010..Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode. 11869 * 0b011..Count rising edges of primary source while secondary input high active 11870 * 0b100..Quadrature count mode, uses primary and secondary sources 11871 * 0b101..Count rising edges of primary source; secondary source specifies directionRising edges are counted only 11872 * when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. 11873 * 0b110..Edge of secondary source triggers primary count until compare 11874 * 0b111..Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs. 11875 */ 11876 #define TMR_CTRL_CM(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK) 11877 /*! @} */ 11878 11879 /*! @name SCTRL - Timer Channel Status and Control Register */ 11880 /*! @{ */ 11881 11882 #define TMR_SCTRL_OEN_MASK (0x1U) 11883 #define TMR_SCTRL_OEN_SHIFT (0U) 11884 /*! OEN - Output Enable 11885 * 0b0..The external pin is configured as an input. 11886 * 0b1..The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as 11887 * their input see the driven value. The polarity of the signal is determined by OPS. 11888 */ 11889 #define TMR_SCTRL_OEN(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK) 11890 11891 #define TMR_SCTRL_OPS_MASK (0x2U) 11892 #define TMR_SCTRL_OPS_SHIFT (1U) 11893 /*! OPS - Output Polarity Select 11894 * 0b0..True polarity. 11895 * 0b1..Inverted polarity. 11896 */ 11897 #define TMR_SCTRL_OPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK) 11898 11899 #define TMR_SCTRL_FORCE_MASK (0x4U) 11900 #define TMR_SCTRL_FORCE_SHIFT (2U) 11901 /*! FORCE - Force OFLAG Output 11902 */ 11903 #define TMR_SCTRL_FORCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK) 11904 11905 #define TMR_SCTRL_VAL_MASK (0x8U) 11906 #define TMR_SCTRL_VAL_SHIFT (3U) 11907 /*! VAL - Forced OFLAG Value 11908 */ 11909 #define TMR_SCTRL_VAL(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK) 11910 11911 #define TMR_SCTRL_EEOF_MASK (0x10U) 11912 #define TMR_SCTRL_EEOF_SHIFT (4U) 11913 /*! EEOF - Enable External OFLAG Force 11914 */ 11915 #define TMR_SCTRL_EEOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK) 11916 11917 #define TMR_SCTRL_MSTR_MASK (0x20U) 11918 #define TMR_SCTRL_MSTR_SHIFT (5U) 11919 /*! MSTR - Master Mode 11920 */ 11921 #define TMR_SCTRL_MSTR(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK) 11922 11923 #define TMR_SCTRL_CAPTURE_MODE_MASK (0xC0U) 11924 #define TMR_SCTRL_CAPTURE_MODE_SHIFT (6U) 11925 /*! CAPTURE_MODE - Input Capture Mode 11926 * 0b00..Capture function is disabled 11927 * 0b01..Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input 11928 * 0b10..Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input 11929 * 0b11..Load capture register on both edges of input 11930 */ 11931 #define TMR_SCTRL_CAPTURE_MODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK) 11932 11933 #define TMR_SCTRL_INPUT_MASK (0x100U) 11934 #define TMR_SCTRL_INPUT_SHIFT (8U) 11935 /*! INPUT - External Input Signal 11936 */ 11937 #define TMR_SCTRL_INPUT(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK) 11938 11939 #define TMR_SCTRL_IPS_MASK (0x200U) 11940 #define TMR_SCTRL_IPS_SHIFT (9U) 11941 /*! IPS - Input Polarity Select 11942 */ 11943 #define TMR_SCTRL_IPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK) 11944 11945 #define TMR_SCTRL_IEFIE_MASK (0x400U) 11946 #define TMR_SCTRL_IEFIE_SHIFT (10U) 11947 /*! IEFIE - Input Edge Flag Interrupt Enable 11948 */ 11949 #define TMR_SCTRL_IEFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK) 11950 11951 #define TMR_SCTRL_IEF_MASK (0x800U) 11952 #define TMR_SCTRL_IEF_SHIFT (11U) 11953 /*! IEF - Input Edge Flag 11954 */ 11955 #define TMR_SCTRL_IEF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK) 11956 11957 #define TMR_SCTRL_TOFIE_MASK (0x1000U) 11958 #define TMR_SCTRL_TOFIE_SHIFT (12U) 11959 /*! TOFIE - Timer Overflow Flag Interrupt Enable 11960 */ 11961 #define TMR_SCTRL_TOFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK) 11962 11963 #define TMR_SCTRL_TOF_MASK (0x2000U) 11964 #define TMR_SCTRL_TOF_SHIFT (13U) 11965 /*! TOF - Timer Overflow Flag 11966 */ 11967 #define TMR_SCTRL_TOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK) 11968 11969 #define TMR_SCTRL_TCFIE_MASK (0x4000U) 11970 #define TMR_SCTRL_TCFIE_SHIFT (14U) 11971 /*! TCFIE - Timer Compare Flag Interrupt Enable 11972 */ 11973 #define TMR_SCTRL_TCFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK) 11974 11975 #define TMR_SCTRL_TCF_MASK (0x8000U) 11976 #define TMR_SCTRL_TCF_SHIFT (15U) 11977 /*! TCF - Timer Compare Flag 11978 */ 11979 #define TMR_SCTRL_TCF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK) 11980 /*! @} */ 11981 11982 /*! @name CMPLD1 - Timer Channel Comparator Load Register 1 */ 11983 /*! @{ */ 11984 11985 #define TMR_CMPLD1_COMPARATOR_LOAD_1_MASK (0xFFFFU) 11986 #define TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT (0U) 11987 #define TMR_CMPLD1_COMPARATOR_LOAD_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK) 11988 /*! @} */ 11989 11990 /*! @name CMPLD2 - Timer Channel Comparator Load Register 2 */ 11991 /*! @{ */ 11992 11993 #define TMR_CMPLD2_COMPARATOR_LOAD_2_MASK (0xFFFFU) 11994 #define TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT (0U) 11995 #define TMR_CMPLD2_COMPARATOR_LOAD_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK) 11996 /*! @} */ 11997 11998 /*! @name CSCTRL - Timer Channel Comparator Status and Control Register */ 11999 /*! @{ */ 12000 12001 #define TMR_CSCTRL_CL1_MASK (0x3U) 12002 #define TMR_CSCTRL_CL1_SHIFT (0U) 12003 /*! CL1 - Compare Load Control 1 12004 * 0b00..Never preload 12005 * 0b01..Load upon successful compare with the value in COMP1 12006 * 0b10..Load upon successful compare with the value in COMP2 12007 * 0b11..Reserved 12008 */ 12009 #define TMR_CSCTRL_CL1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK) 12010 12011 #define TMR_CSCTRL_CL2_MASK (0xCU) 12012 #define TMR_CSCTRL_CL2_SHIFT (2U) 12013 /*! CL2 - Compare Load Control 2 12014 * 0b00..Never preload 12015 * 0b01..Load upon successful compare with the value in COMP1 12016 * 0b10..Load upon successful compare with the value in COMP2 12017 * 0b11..Reserved 12018 */ 12019 #define TMR_CSCTRL_CL2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK) 12020 12021 #define TMR_CSCTRL_TCF1_MASK (0x10U) 12022 #define TMR_CSCTRL_TCF1_SHIFT (4U) 12023 /*! TCF1 - Timer Compare 1 Interrupt Flag 12024 */ 12025 #define TMR_CSCTRL_TCF1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK) 12026 12027 #define TMR_CSCTRL_TCF2_MASK (0x20U) 12028 #define TMR_CSCTRL_TCF2_SHIFT (5U) 12029 /*! TCF2 - Timer Compare 2 Interrupt Flag 12030 */ 12031 #define TMR_CSCTRL_TCF2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK) 12032 12033 #define TMR_CSCTRL_TCF1EN_MASK (0x40U) 12034 #define TMR_CSCTRL_TCF1EN_SHIFT (6U) 12035 /*! TCF1EN - Timer Compare 1 Interrupt Enable 12036 */ 12037 #define TMR_CSCTRL_TCF1EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK) 12038 12039 #define TMR_CSCTRL_TCF2EN_MASK (0x80U) 12040 #define TMR_CSCTRL_TCF2EN_SHIFT (7U) 12041 /*! TCF2EN - Timer Compare 2 Interrupt Enable 12042 */ 12043 #define TMR_CSCTRL_TCF2EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK) 12044 12045 #define TMR_CSCTRL_UP_MASK (0x200U) 12046 #define TMR_CSCTRL_UP_SHIFT (9U) 12047 /*! UP - Counting Direction Indicator 12048 * 0b0..The last count was in the DOWN direction. 12049 * 0b1..The last count was in the UP direction. 12050 */ 12051 #define TMR_CSCTRL_UP(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK) 12052 12053 #define TMR_CSCTRL_TCI_MASK (0x400U) 12054 #define TMR_CSCTRL_TCI_SHIFT (10U) 12055 /*! TCI - Triggered Count Initialization Control 12056 * 0b0..Stop counter upon receiving a second trigger event while still counting from the first trigger event. 12057 * 0b1..Reload the counter upon receiving a second trigger event while still counting from the first trigger event. 12058 */ 12059 #define TMR_CSCTRL_TCI(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK) 12060 12061 #define TMR_CSCTRL_ROC_MASK (0x800U) 12062 #define TMR_CSCTRL_ROC_SHIFT (11U) 12063 /*! ROC - Reload on Capture 12064 * 0b0..Do not reload the counter on a capture event. 12065 * 0b1..Reload the counter on a capture event. 12066 */ 12067 #define TMR_CSCTRL_ROC(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK) 12068 12069 #define TMR_CSCTRL_ALT_LOAD_MASK (0x1000U) 12070 #define TMR_CSCTRL_ALT_LOAD_SHIFT (12U) 12071 /*! ALT_LOAD - Alternative Load Enable 12072 * 0b0..Counter can be re-initialized only with the LOAD register. 12073 * 0b1..Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction. 12074 */ 12075 #define TMR_CSCTRL_ALT_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK) 12076 12077 #define TMR_CSCTRL_FAULT_MASK (0x2000U) 12078 #define TMR_CSCTRL_FAULT_SHIFT (13U) 12079 /*! FAULT - Fault Enable 12080 * 0b0..Fault function disabled. 12081 * 0b1..Fault function enabled. 12082 */ 12083 #define TMR_CSCTRL_FAULT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK) 12084 12085 #define TMR_CSCTRL_DBG_EN_MASK (0xC000U) 12086 #define TMR_CSCTRL_DBG_EN_SHIFT (14U) 12087 /*! DBG_EN - Debug Actions Enable 12088 * 0b00..Continue with normal operation during debug mode. (default) 12089 * 0b01..Halt TMR counter during debug mode. 12090 * 0b10..Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]). 12091 * 0b11..Both halt counter and force output to 0 during debug mode. 12092 */ 12093 #define TMR_CSCTRL_DBG_EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK) 12094 /*! @} */ 12095 12096 /*! @name FILT - Timer Channel Input Filter Register */ 12097 /*! @{ */ 12098 12099 #define TMR_FILT_FILT_PER_MASK (0xFFU) 12100 #define TMR_FILT_FILT_PER_SHIFT (0U) 12101 /*! FILT_PER - Input Filter Sample Period 12102 */ 12103 #define TMR_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK) 12104 12105 #define TMR_FILT_FILT_CNT_MASK (0x700U) 12106 #define TMR_FILT_FILT_CNT_SHIFT (8U) 12107 /*! FILT_CNT - Input Filter Sample Count 12108 */ 12109 #define TMR_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK) 12110 /*! @} */ 12111 12112 /*! @name ENBL - Timer Channel Enable Register */ 12113 /*! @{ */ 12114 12115 #define TMR_ENBL_ENBL_MASK (0xFU) 12116 #define TMR_ENBL_ENBL_SHIFT (0U) 12117 /*! ENBL - Timer Channel Enable 12118 * 0b0000..Timer channel is disabled. 12119 * 0b0001..Timer channel is enabled. (default) 12120 */ 12121 #define TMR_ENBL_ENBL(x) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK) 12122 /*! @} */ 12123 12124 12125 /*! 12126 * @} 12127 */ /* end of group TMR_Register_Masks */ 12128 12129 12130 /* TMR - Peripheral instance base addresses */ 12131 /** Peripheral TMR0 base address */ 12132 #define TMR0_BASE (0x40057000u) 12133 /** Peripheral TMR0 base pointer */ 12134 #define TMR0 ((TMR_Type *)TMR0_BASE) 12135 /** Peripheral TMR1 base address */ 12136 #define TMR1_BASE (0x40058000u) 12137 /** Peripheral TMR1 base pointer */ 12138 #define TMR1 ((TMR_Type *)TMR1_BASE) 12139 /** Peripheral TMR2 base address */ 12140 #define TMR2_BASE (0x40059000u) 12141 /** Peripheral TMR2 base pointer */ 12142 #define TMR2 ((TMR_Type *)TMR2_BASE) 12143 /** Peripheral TMR3 base address */ 12144 #define TMR3_BASE (0x4005A000u) 12145 /** Peripheral TMR3 base pointer */ 12146 #define TMR3 ((TMR_Type *)TMR3_BASE) 12147 /** Array initializer of TMR peripheral base addresses */ 12148 #define TMR_BASE_ADDRS { TMR0_BASE, TMR1_BASE, TMR2_BASE, TMR3_BASE } 12149 /** Array initializer of TMR peripheral base pointers */ 12150 #define TMR_BASE_PTRS { TMR0, TMR1, TMR2, TMR3 } 12151 /** Interrupt vectors for the TMR peripheral type */ 12152 #define TMR_IRQS { TMR0_IRQn, TMR1_IRQn, TMR2_IRQn, TMR3_IRQn } 12153 12154 /*! 12155 * @} 12156 */ /* end of group TMR_Peripheral_Access_Layer */ 12157 12158 12159 /* ---------------------------------------------------------------------------- 12160 -- UART Peripheral Access Layer 12161 ---------------------------------------------------------------------------- */ 12162 12163 /*! 12164 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer 12165 * @{ 12166 */ 12167 12168 /** UART - Register Layout Typedef */ 12169 typedef struct { 12170 __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */ 12171 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */ 12172 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */ 12173 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */ 12174 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */ 12175 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */ 12176 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */ 12177 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */ 12178 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */ 12179 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */ 12180 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */ 12181 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */ 12182 __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */ 12183 __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */ 12184 uint8_t RESERVED_0[2]; 12185 __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */ 12186 __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */ 12187 __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */ 12188 __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */ 12189 __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */ 12190 __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */ 12191 __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */ 12192 uint8_t RESERVED_1[1]; 12193 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */ 12194 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */ 12195 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */ 12196 union { /* offset: 0x1B */ 12197 __IO uint8_t WP7816T0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */ 12198 __IO uint8_t WP7816T1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */ 12199 }; 12200 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */ 12201 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */ 12202 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */ 12203 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */ 12204 } UART_Type; 12205 12206 /* ---------------------------------------------------------------------------- 12207 -- UART Register Masks 12208 ---------------------------------------------------------------------------- */ 12209 12210 /*! 12211 * @addtogroup UART_Register_Masks UART Register Masks 12212 * @{ 12213 */ 12214 12215 /*! @name BDH - UART Baud Rate Registers: High */ 12216 /*! @{ */ 12217 12218 #define UART_BDH_SBR_MASK (0x1FU) 12219 #define UART_BDH_SBR_SHIFT (0U) 12220 /*! SBR - UART Baud Rate Bits 12221 */ 12222 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK) 12223 12224 #define UART_BDH_RXEDGIE_MASK (0x40U) 12225 #define UART_BDH_RXEDGIE_SHIFT (6U) 12226 /*! RXEDGIE - RxD Input Active Edge Interrupt Enable 12227 * 0b0..Hardware interrupts from RXEDGIF disabled using polling. 12228 * 0b1..RXEDGIF interrupt request enabled. 12229 */ 12230 #define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK) 12231 /*! @} */ 12232 12233 /*! @name BDL - UART Baud Rate Registers: Low */ 12234 /*! @{ */ 12235 12236 #define UART_BDL_SBR_MASK (0xFFU) 12237 #define UART_BDL_SBR_SHIFT (0U) 12238 /*! SBR - UART Baud Rate Bits 12239 */ 12240 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK) 12241 /*! @} */ 12242 12243 /*! @name C1 - UART Control Register 1 */ 12244 /*! @{ */ 12245 12246 #define UART_C1_PT_MASK (0x1U) 12247 #define UART_C1_PT_SHIFT (0U) 12248 /*! PT - Parity Type 12249 * 0b0..Even parity. 12250 * 0b1..Odd parity. 12251 */ 12252 #define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK) 12253 12254 #define UART_C1_PE_MASK (0x2U) 12255 #define UART_C1_PE_SHIFT (1U) 12256 /*! PE - Parity Enable 12257 * 0b0..Parity function disabled. 12258 * 0b1..Parity function enabled. 12259 */ 12260 #define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK) 12261 12262 #define UART_C1_ILT_MASK (0x4U) 12263 #define UART_C1_ILT_SHIFT (2U) 12264 /*! ILT - Idle Line Type Select 12265 * 0b0..Idle character bit count starts after start bit. 12266 * 0b1..Idle character bit count starts after stop bit. 12267 */ 12268 #define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK) 12269 12270 #define UART_C1_WAKE_MASK (0x8U) 12271 #define UART_C1_WAKE_SHIFT (3U) 12272 /*! WAKE - Receiver Wakeup Method Select 12273 * 0b0..Idle line wakeup. 12274 * 0b1..Address mark wakeup. 12275 */ 12276 #define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK) 12277 12278 #define UART_C1_M_MASK (0x10U) 12279 #define UART_C1_M_SHIFT (4U) 12280 /*! M - 9-bit or 8-bit Mode Select 12281 * 0b0..Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. 12282 * 0b1..Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. 12283 */ 12284 #define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK) 12285 12286 #define UART_C1_RSRC_MASK (0x20U) 12287 #define UART_C1_RSRC_SHIFT (5U) 12288 /*! RSRC - Receiver Source Select 12289 * 0b0..Selects internal loop back mode. The receiver input is internally connected to transmitter output. 12290 * 0b1..Single wire UART mode where the receiver input is connected to the transmit pin input signal. 12291 */ 12292 #define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK) 12293 12294 #define UART_C1_LOOPS_MASK (0x80U) 12295 #define UART_C1_LOOPS_SHIFT (7U) 12296 /*! LOOPS - Loop Mode Select 12297 * 0b0..Normal operation. 12298 * 0b1..Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC. 12299 */ 12300 #define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK) 12301 /*! @} */ 12302 12303 /*! @name C2 - UART Control Register 2 */ 12304 /*! @{ */ 12305 12306 #define UART_C2_SBK_MASK (0x1U) 12307 #define UART_C2_SBK_SHIFT (0U) 12308 /*! SBK - Send Break 12309 * 0b0..Normal transmitter operation. 12310 * 0b1..Queue break characters to be sent. 12311 */ 12312 #define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK) 12313 12314 #define UART_C2_RWU_MASK (0x2U) 12315 #define UART_C2_RWU_SHIFT (1U) 12316 /*! RWU - Receiver Wakeup Control 12317 * 0b0..Normal operation. 12318 * 0b1..RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware 12319 * wakes the receiver by automatically clearing RWU. 12320 */ 12321 #define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK) 12322 12323 #define UART_C2_RE_MASK (0x4U) 12324 #define UART_C2_RE_SHIFT (2U) 12325 /*! RE - Receiver Enable 12326 * 0b0..Receiver off. 12327 * 0b1..Receiver on. 12328 */ 12329 #define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK) 12330 12331 #define UART_C2_TE_MASK (0x8U) 12332 #define UART_C2_TE_SHIFT (3U) 12333 /*! TE - Transmitter Enable 12334 * 0b0..Transmitter off. 12335 * 0b1..Transmitter on. 12336 */ 12337 #define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK) 12338 12339 #define UART_C2_ILIE_MASK (0x10U) 12340 #define UART_C2_ILIE_SHIFT (4U) 12341 /*! ILIE - Idle Line Interrupt Enable 12342 * 0b0..IDLE interrupt requests disabled. 12343 * 0b1..IDLE interrupt requests enabled. 12344 */ 12345 #define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK) 12346 12347 #define UART_C2_RIE_MASK (0x20U) 12348 #define UART_C2_RIE_SHIFT (5U) 12349 /*! RIE - Receiver Full Interrupt or DMA Transfer Enable 12350 * 0b0..RDRF interrupt and DMA transfer requests disabled. 12351 * 0b1..RDRF interrupt or DMA transfer requests enabled. 12352 */ 12353 #define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK) 12354 12355 #define UART_C2_TCIE_MASK (0x40U) 12356 #define UART_C2_TCIE_SHIFT (6U) 12357 /*! TCIE - Transmission Complete Interrupt Enable 12358 * 0b0..TC interrupt requests disabled. 12359 * 0b1..TC interrupt requests enabled. 12360 */ 12361 #define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK) 12362 12363 #define UART_C2_TIE_MASK (0x80U) 12364 #define UART_C2_TIE_SHIFT (7U) 12365 /*! TIE - Transmitter Interrupt or DMA Transfer Enable. 12366 * 0b0..TDRE interrupt and DMA transfer requests disabled. 12367 * 0b1..TDRE interrupt or DMA transfer requests enabled. 12368 */ 12369 #define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK) 12370 /*! @} */ 12371 12372 /*! @name S1 - UART Status Register 1 */ 12373 /*! @{ */ 12374 12375 #define UART_S1_PF_MASK (0x1U) 12376 #define UART_S1_PF_SHIFT (0U) 12377 /*! PF - Parity Error Flag 12378 * 0b0..No parity error detected since the last time this flag was cleared. If the receive buffer has a depth 12379 * greater than 1, then there may be data in the receive buffer what was received with a parity error. 12380 * 0b1..At least one dataword was received with a parity error since the last time this flag was cleared. 12381 */ 12382 #define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK) 12383 12384 #define UART_S1_FE_MASK (0x2U) 12385 #define UART_S1_FE_SHIFT (1U) 12386 /*! FE - Framing Error Flag 12387 * 0b0..No framing error detected. 12388 * 0b1..Framing error. 12389 */ 12390 #define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK) 12391 12392 #define UART_S1_NF_MASK (0x4U) 12393 #define UART_S1_NF_SHIFT (2U) 12394 /*! NF - Noise Flag 12395 * 0b0..No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater 12396 * than 1 then there may be data in the receiver buffer that was received with noise. 12397 * 0b1..At least one dataword was received with noise detected since the last time the flag was cleared. 12398 */ 12399 #define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK) 12400 12401 #define UART_S1_OR_MASK (0x8U) 12402 #define UART_S1_OR_SHIFT (3U) 12403 /*! OR - Receiver Overrun Flag 12404 * 0b0..No overrun has occurred since the last time the flag was cleared. 12405 * 0b1..Overrun has occurred or the overrun flag has not been cleared since the last overrun occured. 12406 */ 12407 #define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK) 12408 12409 #define UART_S1_IDLE_MASK (0x10U) 12410 #define UART_S1_IDLE_SHIFT (4U) 12411 /*! IDLE - Idle Line Flag 12412 * 0b0..Receiver input is either active now or has never become active since the IDLE flag was last cleared. 12413 * 0b1..Receiver input has become idle or the flag has not been cleared since it last asserted. 12414 */ 12415 #define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK) 12416 12417 #define UART_S1_RDRF_MASK (0x20U) 12418 #define UART_S1_RDRF_SHIFT (5U) 12419 /*! RDRF - Receive Data Register Full Flag 12420 * 0b0..The number of datawords in the receive buffer is less than the number indicated by RXWATER. 12421 * 0b1..The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER 12422 * at some point in time since this flag was last cleared. 12423 */ 12424 #define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK) 12425 12426 #define UART_S1_TC_MASK (0x40U) 12427 #define UART_S1_TC_SHIFT (6U) 12428 /*! TC - Transmit Complete Flag 12429 * 0b0..Transmitter active (sending data, a preamble, or a break). 12430 * 0b1..Transmitter idle (transmission activity complete). 12431 */ 12432 #define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK) 12433 12434 #define UART_S1_TDRE_MASK (0x80U) 12435 #define UART_S1_TDRE_SHIFT (7U) 12436 /*! TDRE - Transmit Data Register Empty Flag 12437 * 0b0..The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER]. 12438 * 0b1..The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] 12439 * at some point in time since the flag has been cleared. 12440 */ 12441 #define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK) 12442 /*! @} */ 12443 12444 /*! @name S2 - UART Status Register 2 */ 12445 /*! @{ */ 12446 12447 #define UART_S2_RAF_MASK (0x1U) 12448 #define UART_S2_RAF_SHIFT (0U) 12449 /*! RAF - Receiver Active Flag 12450 * 0b0..UART receiver idle/inactive waiting for a start bit. 12451 * 0b1..UART receiver active, RxD input not idle. 12452 */ 12453 #define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK) 12454 12455 #define UART_S2_BRK13_MASK (0x4U) 12456 #define UART_S2_BRK13_SHIFT (2U) 12457 /*! BRK13 - Break Transmit Character Length 12458 * 0b0..Break character is 10, 11, or 12 bits long. 12459 * 0b1..Break character is 13 or 14 bits long. 12460 */ 12461 #define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK) 12462 12463 #define UART_S2_RWUID_MASK (0x8U) 12464 #define UART_S2_RWUID_SHIFT (3U) 12465 /*! RWUID - Receive Wakeup Idle Detect 12466 * 0b0..S1[IDLE] is not set upon detection of an idle character. 12467 * 0b1..S1[IDLE] is set upon detection of an idle character. 12468 */ 12469 #define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK) 12470 12471 #define UART_S2_RXINV_MASK (0x10U) 12472 #define UART_S2_RXINV_SHIFT (4U) 12473 /*! RXINV - Receive Data Inversion 12474 * 0b0..Receive data is not inverted. 12475 * 0b1..Receive data is inverted. 12476 */ 12477 #define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK) 12478 12479 #define UART_S2_MSBF_MASK (0x20U) 12480 #define UART_S2_MSBF_SHIFT (5U) 12481 /*! MSBF - Most Significant Bit First 12482 * 0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received 12483 * after the start bit is identified as bit0. 12484 * 0b1..MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the 12485 * setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, 12486 * bit7, or bit6, depending on the setting of C1[M] and C1[PE]. 12487 */ 12488 #define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK) 12489 12490 #define UART_S2_RXEDGIF_MASK (0x40U) 12491 #define UART_S2_RXEDGIF_SHIFT (6U) 12492 /*! RXEDGIF - RxD Pin Active Edge Interrupt Flag 12493 * 0b0..No active edge on the receive pin has occurred. 12494 * 0b1..An active edge on the receive pin has occurred. 12495 */ 12496 #define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK) 12497 /*! @} */ 12498 12499 /*! @name C3 - UART Control Register 3 */ 12500 /*! @{ */ 12501 12502 #define UART_C3_PEIE_MASK (0x1U) 12503 #define UART_C3_PEIE_SHIFT (0U) 12504 /*! PEIE - Parity Error Interrupt Enable 12505 * 0b0..PF interrupt requests are disabled. 12506 * 0b1..PF interrupt requests are enabled. 12507 */ 12508 #define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK) 12509 12510 #define UART_C3_FEIE_MASK (0x2U) 12511 #define UART_C3_FEIE_SHIFT (1U) 12512 /*! FEIE - Framing Error Interrupt Enable 12513 * 0b0..FE interrupt requests are disabled. 12514 * 0b1..FE interrupt requests are enabled. 12515 */ 12516 #define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK) 12517 12518 #define UART_C3_NEIE_MASK (0x4U) 12519 #define UART_C3_NEIE_SHIFT (2U) 12520 /*! NEIE - Noise Error Interrupt Enable 12521 * 0b0..NF interrupt requests are disabled. 12522 * 0b1..NF interrupt requests are enabled. 12523 */ 12524 #define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK) 12525 12526 #define UART_C3_ORIE_MASK (0x8U) 12527 #define UART_C3_ORIE_SHIFT (3U) 12528 /*! ORIE - Overrun Error Interrupt Enable 12529 * 0b0..OR interrupts are disabled. 12530 * 0b1..OR interrupt requests are enabled. 12531 */ 12532 #define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK) 12533 12534 #define UART_C3_TXINV_MASK (0x10U) 12535 #define UART_C3_TXINV_SHIFT (4U) 12536 /*! TXINV - Transmit Data Inversion. 12537 * 0b0..Transmit data is not inverted. 12538 * 0b1..Transmit data is inverted. 12539 */ 12540 #define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK) 12541 12542 #define UART_C3_TXDIR_MASK (0x20U) 12543 #define UART_C3_TXDIR_SHIFT (5U) 12544 /*! TXDIR - Transmitter Pin Data Direction in Single-Wire mode 12545 * 0b0..TXD pin is an input in single wire mode. 12546 * 0b1..TXD pin is an output in single wire mode. 12547 */ 12548 #define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK) 12549 12550 #define UART_C3_T8_MASK (0x40U) 12551 #define UART_C3_T8_SHIFT (6U) 12552 /*! T8 - Transmit Bit 8 12553 */ 12554 #define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK) 12555 12556 #define UART_C3_R8_MASK (0x80U) 12557 #define UART_C3_R8_SHIFT (7U) 12558 /*! R8 - Received Bit 8 12559 */ 12560 #define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK) 12561 /*! @} */ 12562 12563 /*! @name D - UART Data Register */ 12564 /*! @{ */ 12565 12566 #define UART_D_RT_MASK (0xFFU) 12567 #define UART_D_RT_SHIFT (0U) 12568 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK) 12569 /*! @} */ 12570 12571 /*! @name MA1 - UART Match Address Registers 1 */ 12572 /*! @{ */ 12573 12574 #define UART_MA1_MA_MASK (0xFFU) 12575 #define UART_MA1_MA_SHIFT (0U) 12576 /*! MA - Match Address 12577 */ 12578 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK) 12579 /*! @} */ 12580 12581 /*! @name MA2 - UART Match Address Registers 2 */ 12582 /*! @{ */ 12583 12584 #define UART_MA2_MA_MASK (0xFFU) 12585 #define UART_MA2_MA_SHIFT (0U) 12586 /*! MA - Match Address 12587 */ 12588 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK) 12589 /*! @} */ 12590 12591 /*! @name C4 - UART Control Register 4 */ 12592 /*! @{ */ 12593 12594 #define UART_C4_BRFA_MASK (0x1FU) 12595 #define UART_C4_BRFA_SHIFT (0U) 12596 /*! BRFA - Baud Rate Fine Adjust 12597 */ 12598 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK) 12599 12600 #define UART_C4_M10_MASK (0x20U) 12601 #define UART_C4_M10_SHIFT (5U) 12602 /*! M10 - 10-bit Mode select 12603 * 0b0..The parity bit is the ninth bit in the serial transmission. 12604 * 0b1..The parity bit is the tenth bit in the serial transmission. 12605 */ 12606 #define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK) 12607 12608 #define UART_C4_MAEN2_MASK (0x40U) 12609 #define UART_C4_MAEN2_SHIFT (6U) 12610 /*! MAEN2 - Match Address Mode Enable 2 12611 * 0b0..All data received is transferred to the data buffer if MAEN1 is cleared. 12612 * 0b1..All data received with the most significant bit cleared, is discarded. All data received with the most 12613 * significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. 12614 * If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] 12615 * is set/enabled. 12616 */ 12617 #define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK) 12618 12619 #define UART_C4_MAEN1_MASK (0x80U) 12620 #define UART_C4_MAEN1_SHIFT (7U) 12621 /*! MAEN1 - Match Address Mode Enable 1 12622 * 0b0..All data received is transferred to the data buffer if MAEN2 is cleared. 12623 * 0b1..All data received with the most significant bit cleared, is discarded. All data received with the most 12624 * significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. 12625 * If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is 12626 * set/enabled. 12627 */ 12628 #define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK) 12629 /*! @} */ 12630 12631 /*! @name C5 - UART Control Register 5 */ 12632 /*! @{ */ 12633 12634 #define UART_C5_RDMAS_MASK (0x20U) 12635 #define UART_C5_RDMAS_SHIFT (5U) 12636 /*! RDMAS - Receiver Full DMA Select 12637 * 0b0..If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service. 12638 * 0b1..If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer. 12639 */ 12640 #define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK) 12641 12642 #define UART_C5_TDMAS_MASK (0x80U) 12643 #define UART_C5_TDMAS_SHIFT (7U) 12644 /*! TDMAS - Transmitter DMA Select 12645 * 0b0..If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service. 12646 * 0b1..If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. 12647 */ 12648 #define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK) 12649 /*! @} */ 12650 12651 /*! @name ED - UART Extended Data Register */ 12652 /*! @{ */ 12653 12654 #define UART_ED_PARITYE_MASK (0x40U) 12655 #define UART_ED_PARITYE_SHIFT (6U) 12656 /*! PARITYE 12657 * 0b0..The dataword was received without a parity error. 12658 * 0b1..The dataword was received with a parity error. 12659 */ 12660 #define UART_ED_PARITYE(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_PARITYE_SHIFT)) & UART_ED_PARITYE_MASK) 12661 12662 #define UART_ED_NOISY_MASK (0x80U) 12663 #define UART_ED_NOISY_SHIFT (7U) 12664 /*! NOISY 12665 * 0b0..The dataword was received without noise. 12666 * 0b1..The data was received with noise. 12667 */ 12668 #define UART_ED_NOISY(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_NOISY_SHIFT)) & UART_ED_NOISY_MASK) 12669 /*! @} */ 12670 12671 /*! @name MODEM - UART Modem Register */ 12672 /*! @{ */ 12673 12674 #define UART_MODEM_TXCTSE_MASK (0x1U) 12675 #define UART_MODEM_TXCTSE_SHIFT (0U) 12676 /*! TXCTSE - Transmitter clear-to-send enable 12677 * 0b0..CTS has no effect on the transmitter. 12678 * 0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a 12679 * character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the 12680 * mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent 12681 * do not affect its transmission. 12682 */ 12683 #define UART_MODEM_TXCTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXCTSE_SHIFT)) & UART_MODEM_TXCTSE_MASK) 12684 12685 #define UART_MODEM_TXRTSE_MASK (0x2U) 12686 #define UART_MODEM_TXRTSE_SHIFT (1U) 12687 /*! TXRTSE - Transmitter request-to-send enable 12688 * 0b0..The transmitter has no effect on RTS. 12689 * 0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the 12690 * start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and 12691 * shift register are completely sent, including the last stop bit. (FIFO) Ensure that C2[TE] is asserted 12692 * before assertion of this bit. 12693 */ 12694 #define UART_MODEM_TXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSE_SHIFT)) & UART_MODEM_TXRTSE_MASK) 12695 12696 #define UART_MODEM_TXRTSPOL_MASK (0x4U) 12697 #define UART_MODEM_TXRTSPOL_SHIFT (2U) 12698 /*! TXRTSPOL - Transmitter request-to-send polarity 12699 * 0b0..Transmitter RTS is active low. 12700 * 0b1..Transmitter RTS is active high. 12701 */ 12702 #define UART_MODEM_TXRTSPOL(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSPOL_SHIFT)) & UART_MODEM_TXRTSPOL_MASK) 12703 12704 #define UART_MODEM_RXRTSE_MASK (0x8U) 12705 #define UART_MODEM_RXRTSE_SHIFT (3U) 12706 /*! RXRTSE - Receiver request-to-send enable 12707 * 0b0..The receiver has no effect on RTS. 12708 * 0b1..RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater 12709 * than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) 12710 * is less than RWFIFO[RXWATER]. See Hardware flow control 12711 */ 12712 #define UART_MODEM_RXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_RXRTSE_SHIFT)) & UART_MODEM_RXRTSE_MASK) 12713 /*! @} */ 12714 12715 /*! @name PFIFO - UART FIFO Parameters */ 12716 /*! @{ */ 12717 12718 #define UART_PFIFO_RXFIFOSIZE_MASK (0x7U) 12719 #define UART_PFIFO_RXFIFOSIZE_SHIFT (0U) 12720 /*! RXFIFOSIZE - Receive FIFO. Buffer Depth 12721 * 0b000..Receive FIFO/Buffer depth = 1 dataword. 12722 * 0b001..Receive FIFO/Buffer depth = 4 datawords. 12723 * 0b010..Receive FIFO/Buffer depth = 8 datawords. 12724 * 0b011..Receive FIFO/Buffer depth = 16 datawords. 12725 * 0b100..Receive FIFO/Buffer depth = 32 datawords. 12726 * 0b101..Receive FIFO/Buffer depth = 64 datawords. 12727 * 0b110..Receive FIFO/Buffer depth = 128 datawords. 12728 * 0b111..Reserved. 12729 */ 12730 #define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK) 12731 12732 #define UART_PFIFO_RXFE_MASK (0x8U) 12733 #define UART_PFIFO_RXFE_SHIFT (3U) 12734 /*! RXFE - Receive FIFO Enable 12735 * 0b0..Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) 12736 * 0b1..Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. 12737 */ 12738 #define UART_PFIFO_RXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFE_SHIFT)) & UART_PFIFO_RXFE_MASK) 12739 12740 #define UART_PFIFO_TXFIFOSIZE_MASK (0x70U) 12741 #define UART_PFIFO_TXFIFOSIZE_SHIFT (4U) 12742 /*! TXFIFOSIZE - Transmit FIFO. Buffer Depth 12743 * 0b000..Transmit FIFO/Buffer depth = 1 dataword. 12744 * 0b001..Transmit FIFO/Buffer depth = 4 datawords. 12745 * 0b010..Transmit FIFO/Buffer depth = 8 datawords. 12746 * 0b011..Transmit FIFO/Buffer depth = 16 datawords. 12747 * 0b100..Transmit FIFO/Buffer depth = 32 datawords. 12748 * 0b101..Transmit FIFO/Buffer depth = 64 datawords. 12749 * 0b110..Transmit FIFO/Buffer depth = 128 datawords. 12750 * 0b111..Reserved. 12751 */ 12752 #define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK) 12753 12754 #define UART_PFIFO_TXFE_MASK (0x80U) 12755 #define UART_PFIFO_TXFE_SHIFT (7U) 12756 /*! TXFE - Transmit FIFO Enable 12757 * 0b0..Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). 12758 * 0b1..Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. 12759 */ 12760 #define UART_PFIFO_TXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFE_SHIFT)) & UART_PFIFO_TXFE_MASK) 12761 /*! @} */ 12762 12763 /*! @name CFIFO - UART FIFO Control Register */ 12764 /*! @{ */ 12765 12766 #define UART_CFIFO_RXUFE_MASK (0x1U) 12767 #define UART_CFIFO_RXUFE_SHIFT (0U) 12768 /*! RXUFE - Receive FIFO Underflow Interrupt Enable 12769 * 0b0..RXUF flag does not generate an interrupt to the host. 12770 * 0b1..RXUF flag generates an interrupt to the host. 12771 */ 12772 #define UART_CFIFO_RXUFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXUFE_SHIFT)) & UART_CFIFO_RXUFE_MASK) 12773 12774 #define UART_CFIFO_TXOFE_MASK (0x2U) 12775 #define UART_CFIFO_TXOFE_SHIFT (1U) 12776 /*! TXOFE - Transmit FIFO Overflow Interrupt Enable 12777 * 0b0..TXOF flag does not generate an interrupt to the host. 12778 * 0b1..TXOF flag generates an interrupt to the host. 12779 */ 12780 #define UART_CFIFO_TXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXOFE_SHIFT)) & UART_CFIFO_TXOFE_MASK) 12781 12782 #define UART_CFIFO_RXOFE_MASK (0x4U) 12783 #define UART_CFIFO_RXOFE_SHIFT (2U) 12784 /*! RXOFE - Receive FIFO Overflow Interrupt Enable 12785 * 0b0..RXOF flag does not generate an interrupt to the host. 12786 * 0b1..RXOF flag generates an interrupt to the host. 12787 */ 12788 #define UART_CFIFO_RXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXOFE_SHIFT)) & UART_CFIFO_RXOFE_MASK) 12789 12790 #define UART_CFIFO_RXFLUSH_MASK (0x40U) 12791 #define UART_CFIFO_RXFLUSH_SHIFT (6U) 12792 /*! RXFLUSH - Receive FIFO/Buffer Flush 12793 * 0b0..No flush operation occurs. 12794 * 0b1..All data in the receive FIFO/buffer is cleared out. 12795 */ 12796 #define UART_CFIFO_RXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXFLUSH_SHIFT)) & UART_CFIFO_RXFLUSH_MASK) 12797 12798 #define UART_CFIFO_TXFLUSH_MASK (0x80U) 12799 #define UART_CFIFO_TXFLUSH_SHIFT (7U) 12800 /*! TXFLUSH - Transmit FIFO/Buffer Flush 12801 * 0b0..No flush operation occurs. 12802 * 0b1..All data in the transmit FIFO/Buffer is cleared out. 12803 */ 12804 #define UART_CFIFO_TXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXFLUSH_SHIFT)) & UART_CFIFO_TXFLUSH_MASK) 12805 /*! @} */ 12806 12807 /*! @name SFIFO - UART FIFO Status Register */ 12808 /*! @{ */ 12809 12810 #define UART_SFIFO_RXUF_MASK (0x1U) 12811 #define UART_SFIFO_RXUF_SHIFT (0U) 12812 /*! RXUF - Receiver Buffer Underflow Flag 12813 * 0b0..No receive buffer underflow has occurred since the last time the flag was cleared. 12814 * 0b1..At least one receive buffer underflow has occurred since the last time the flag was cleared. 12815 */ 12816 #define UART_SFIFO_RXUF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXUF_SHIFT)) & UART_SFIFO_RXUF_MASK) 12817 12818 #define UART_SFIFO_TXOF_MASK (0x2U) 12819 #define UART_SFIFO_TXOF_SHIFT (1U) 12820 /*! TXOF - Transmitter Buffer Overflow Flag 12821 * 0b0..No transmit buffer overflow has occurred since the last time the flag was cleared. 12822 * 0b1..At least one transmit buffer overflow has occurred since the last time the flag was cleared. 12823 */ 12824 #define UART_SFIFO_TXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXOF_SHIFT)) & UART_SFIFO_TXOF_MASK) 12825 12826 #define UART_SFIFO_RXOF_MASK (0x4U) 12827 #define UART_SFIFO_RXOF_SHIFT (2U) 12828 /*! RXOF - Receiver Buffer Overflow Flag 12829 * 0b0..No receive buffer overflow has occurred since the last time the flag was cleared. 12830 * 0b1..At least one receive buffer overflow has occurred since the last time the flag was cleared. 12831 */ 12832 #define UART_SFIFO_RXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXOF_SHIFT)) & UART_SFIFO_RXOF_MASK) 12833 12834 #define UART_SFIFO_RXEMPT_MASK (0x40U) 12835 #define UART_SFIFO_RXEMPT_SHIFT (6U) 12836 /*! RXEMPT - Receive Buffer/FIFO Empty 12837 * 0b0..Receive buffer is not empty. 12838 * 0b1..Receive buffer is empty. 12839 */ 12840 #define UART_SFIFO_RXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXEMPT_SHIFT)) & UART_SFIFO_RXEMPT_MASK) 12841 12842 #define UART_SFIFO_TXEMPT_MASK (0x80U) 12843 #define UART_SFIFO_TXEMPT_SHIFT (7U) 12844 /*! TXEMPT - Transmit Buffer/FIFO Empty 12845 * 0b0..Transmit buffer is not empty. 12846 * 0b1..Transmit buffer is empty. 12847 */ 12848 #define UART_SFIFO_TXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXEMPT_SHIFT)) & UART_SFIFO_TXEMPT_MASK) 12849 /*! @} */ 12850 12851 /*! @name TWFIFO - UART FIFO Transmit Watermark */ 12852 /*! @{ */ 12853 12854 #define UART_TWFIFO_TXWATER_MASK (0xFFU) 12855 #define UART_TWFIFO_TXWATER_SHIFT (0U) 12856 /*! TXWATER - Transmit Watermark 12857 */ 12858 #define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK) 12859 /*! @} */ 12860 12861 /*! @name TCFIFO - UART FIFO Transmit Count */ 12862 /*! @{ */ 12863 12864 #define UART_TCFIFO_TXCOUNT_MASK (0xFFU) 12865 #define UART_TCFIFO_TXCOUNT_SHIFT (0U) 12866 /*! TXCOUNT - Transmit Counter 12867 */ 12868 #define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK) 12869 /*! @} */ 12870 12871 /*! @name RWFIFO - UART FIFO Receive Watermark */ 12872 /*! @{ */ 12873 12874 #define UART_RWFIFO_RXWATER_MASK (0xFFU) 12875 #define UART_RWFIFO_RXWATER_SHIFT (0U) 12876 /*! RXWATER - Receive Watermark 12877 */ 12878 #define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK) 12879 /*! @} */ 12880 12881 /*! @name RCFIFO - UART FIFO Receive Count */ 12882 /*! @{ */ 12883 12884 #define UART_RCFIFO_RXCOUNT_MASK (0xFFU) 12885 #define UART_RCFIFO_RXCOUNT_SHIFT (0U) 12886 /*! RXCOUNT - Receive Counter 12887 */ 12888 #define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK) 12889 /*! @} */ 12890 12891 /*! @name C7816 - UART 7816 Control Register */ 12892 /*! @{ */ 12893 12894 #define UART_C7816_ISO_7816E_MASK (0x1U) 12895 #define UART_C7816_ISO_7816E_SHIFT (0U) 12896 /*! ISO_7816E - ISO-7816 Functionality Enabled 12897 * 0b0..ISO-7816 functionality is turned off/not enabled. 12898 * 0b1..ISO-7816 functionality is turned on/enabled. 12899 */ 12900 #define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK) 12901 12902 #define UART_C7816_TTYPE_MASK (0x2U) 12903 #define UART_C7816_TTYPE_SHIFT (1U) 12904 /*! TTYPE - Transfer Type 12905 * 0b0..T = 0 per the ISO-7816 specification. 12906 * 0b1..T = 1 per the ISO-7816 specification. 12907 */ 12908 #define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK) 12909 12910 #define UART_C7816_INIT_MASK (0x4U) 12911 #define UART_C7816_INIT_SHIFT (2U) 12912 /*! INIT - Detect Initial Character 12913 * 0b0..Normal operating mode. Receiver does not seek to identify initial character. 12914 * 0b1..Receiver searches for initial character. 12915 */ 12916 #define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK) 12917 12918 #define UART_C7816_ANACK_MASK (0x8U) 12919 #define UART_C7816_ANACK_SHIFT (3U) 12920 /*! ANACK - Generate NACK on Error 12921 * 0b0..No NACK is automatically generated. 12922 * 0b1..A NACK is automatically generated if a parity error is detected or if an invalid initial character is detected. 12923 */ 12924 #define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK) 12925 12926 #define UART_C7816_ONACK_MASK (0x10U) 12927 #define UART_C7816_ONACK_SHIFT (4U) 12928 /*! ONACK - Generate NACK on Overflow 12929 * 0b0..The received data does not generate a NACK when the receipt of the data results in an overflow event. 12930 * 0b1..If the receiver buffer overflows, a NACK is automatically sent on a received character. 12931 */ 12932 #define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK) 12933 /*! @} */ 12934 12935 /*! @name IE7816 - UART 7816 Interrupt Enable Register */ 12936 /*! @{ */ 12937 12938 #define UART_IE7816_RXTE_MASK (0x1U) 12939 #define UART_IE7816_RXTE_SHIFT (0U) 12940 /*! RXTE - Receive Threshold Exceeded Interrupt Enable 12941 * 0b0..The assertion of IS7816[RXT] does not result in the generation of an interrupt. 12942 * 0b1..The assertion of IS7816[RXT] results in the generation of an interrupt. 12943 */ 12944 #define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK) 12945 12946 #define UART_IE7816_TXTE_MASK (0x2U) 12947 #define UART_IE7816_TXTE_SHIFT (1U) 12948 /*! TXTE - Transmit Threshold Exceeded Interrupt Enable 12949 * 0b0..The assertion of IS7816[TXT] does not result in the generation of an interrupt. 12950 * 0b1..The assertion of IS7816[TXT] results in the generation of an interrupt. 12951 */ 12952 #define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK) 12953 12954 #define UART_IE7816_GTVE_MASK (0x4U) 12955 #define UART_IE7816_GTVE_SHIFT (2U) 12956 /*! GTVE - Guard Timer Violated Interrupt Enable 12957 * 0b0..The assertion of IS7816[GTV] does not result in the generation of an interrupt. 12958 * 0b1..The assertion of IS7816[GTV] results in the generation of an interrupt. 12959 */ 12960 #define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK) 12961 12962 #define UART_IE7816_INITDE_MASK (0x10U) 12963 #define UART_IE7816_INITDE_SHIFT (4U) 12964 /*! INITDE - Initial Character Detected Interrupt Enable 12965 * 0b0..The assertion of IS7816[INITD] does not result in the generation of an interrupt. 12966 * 0b1..The assertion of IS7816[INITD] results in the generation of an interrupt. 12967 */ 12968 #define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK) 12969 12970 #define UART_IE7816_BWTE_MASK (0x20U) 12971 #define UART_IE7816_BWTE_SHIFT (5U) 12972 /*! BWTE - Block Wait Timer Interrupt Enable 12973 * 0b0..The assertion of IS7816[BWT] does not result in the generation of an interrupt. 12974 * 0b1..The assertion of IS7816[BWT] results in the generation of an interrupt. 12975 */ 12976 #define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK) 12977 12978 #define UART_IE7816_CWTE_MASK (0x40U) 12979 #define UART_IE7816_CWTE_SHIFT (6U) 12980 /*! CWTE - Character Wait Timer Interrupt Enable 12981 * 0b0..The assertion of IS7816[CWT] does not result in the generation of an interrupt. 12982 * 0b1..The assertion of IS7816[CWT] results in the generation of an interrupt. 12983 */ 12984 #define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK) 12985 12986 #define UART_IE7816_WTE_MASK (0x80U) 12987 #define UART_IE7816_WTE_SHIFT (7U) 12988 /*! WTE - Wait Timer Interrupt Enable 12989 * 0b0..The assertion of IS7816[WT] does not result in the generation of an interrupt. 12990 * 0b1..The assertion of IS7816[WT] results in the generation of an interrupt. 12991 */ 12992 #define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK) 12993 /*! @} */ 12994 12995 /*! @name IS7816 - UART 7816 Interrupt Status Register */ 12996 /*! @{ */ 12997 12998 #define UART_IS7816_RXT_MASK (0x1U) 12999 #define UART_IS7816_RXT_SHIFT (0U) 13000 /*! RXT - Receive Threshold Exceeded Interrupt 13001 * 0b0..The number of consecutive NACKS generated as a result of parity errors and buffer overruns is less than 13002 * or equal to the value in ET7816[RXTHRESHOLD]. 13003 * 0b1..The number of consecutive NACKS generated as a result of parity errors and buffer overruns is greater than the value in ET7816[RXTHRESHOLD]. 13004 */ 13005 #define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK) 13006 13007 #define UART_IS7816_TXT_MASK (0x2U) 13008 #define UART_IS7816_TXT_SHIFT (1U) 13009 /*! TXT - Transmit Threshold Exceeded Interrupt 13010 * 0b0..The number of retries and corresponding NACKS does not exceed the value in ET7816[TXTHRESHOLD]. 13011 * 0b1..The number of retries and corresponding NACKS exceeds the value in ET7816[TXTHRESHOLD]. 13012 */ 13013 #define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK) 13014 13015 #define UART_IS7816_GTV_MASK (0x4U) 13016 #define UART_IS7816_GTV_SHIFT (2U) 13017 /*! GTV - Guard Timer Violated Interrupt 13018 * 0b0..A guard time (GT, CGT, or BGT) has not been violated. 13019 * 0b1..A guard time (GT, CGT, or BGT) has been violated. 13020 */ 13021 #define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK) 13022 13023 #define UART_IS7816_INITD_MASK (0x10U) 13024 #define UART_IS7816_INITD_SHIFT (4U) 13025 /*! INITD - Initial Character Detected Interrupt 13026 * 0b0..A valid initial character has not been received. 13027 * 0b1..A valid initial character has been received. 13028 */ 13029 #define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK) 13030 13031 #define UART_IS7816_BWT_MASK (0x20U) 13032 #define UART_IS7816_BWT_SHIFT (5U) 13033 /*! BWT - Block Wait Timer Interrupt 13034 * 0b0..Block wait time (BWT) has not been violated. 13035 * 0b1..Block wait time (BWT) has been violated. 13036 */ 13037 #define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK) 13038 13039 #define UART_IS7816_CWT_MASK (0x40U) 13040 #define UART_IS7816_CWT_SHIFT (6U) 13041 /*! CWT - Character Wait Timer Interrupt 13042 * 0b0..Character wait time (CWT) has not been violated. 13043 * 0b1..Character wait time (CWT) has been violated. 13044 */ 13045 #define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK) 13046 13047 #define UART_IS7816_WT_MASK (0x80U) 13048 #define UART_IS7816_WT_SHIFT (7U) 13049 /*! WT - Wait Timer Interrupt 13050 * 0b0..Wait time (WT) has not been violated. 13051 * 0b1..Wait time (WT) has been violated. 13052 */ 13053 #define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK) 13054 /*! @} */ 13055 13056 /*! @name WP7816T0 - UART 7816 Wait Parameter Register */ 13057 /*! @{ */ 13058 13059 #define UART_WP7816T0_WI_MASK (0xFFU) 13060 #define UART_WP7816T0_WI_SHIFT (0U) 13061 /*! WI - Wait Time Integer (C7816[TTYPE] = 0) 13062 */ 13063 #define UART_WP7816T0_WI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T0_WI_SHIFT)) & UART_WP7816T0_WI_MASK) 13064 /*! @} */ 13065 13066 /*! @name WP7816T1 - UART 7816 Wait Parameter Register */ 13067 /*! @{ */ 13068 13069 #define UART_WP7816T1_BWI_MASK (0xFU) 13070 #define UART_WP7816T1_BWI_SHIFT (0U) 13071 /*! BWI - Block Wait Time Integer(C7816[TTYPE] = 1) 13072 */ 13073 #define UART_WP7816T1_BWI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_BWI_SHIFT)) & UART_WP7816T1_BWI_MASK) 13074 13075 #define UART_WP7816T1_CWI_MASK (0xF0U) 13076 #define UART_WP7816T1_CWI_SHIFT (4U) 13077 /*! CWI - Character Wait Time Integer (C7816[TTYPE] = 1) 13078 */ 13079 #define UART_WP7816T1_CWI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_CWI_SHIFT)) & UART_WP7816T1_CWI_MASK) 13080 /*! @} */ 13081 13082 /*! @name WN7816 - UART 7816 Wait N Register */ 13083 /*! @{ */ 13084 13085 #define UART_WN7816_GTN_MASK (0xFFU) 13086 #define UART_WN7816_GTN_SHIFT (0U) 13087 /*! GTN - Guard Band N 13088 */ 13089 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK) 13090 /*! @} */ 13091 13092 /*! @name WF7816 - UART 7816 Wait FD Register */ 13093 /*! @{ */ 13094 13095 #define UART_WF7816_GTFD_MASK (0xFFU) 13096 #define UART_WF7816_GTFD_SHIFT (0U) 13097 /*! GTFD - FD Multiplier 13098 */ 13099 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK) 13100 /*! @} */ 13101 13102 /*! @name ET7816 - UART 7816 Error Threshold Register */ 13103 /*! @{ */ 13104 13105 #define UART_ET7816_RXTHRESHOLD_MASK (0xFU) 13106 #define UART_ET7816_RXTHRESHOLD_SHIFT (0U) 13107 /*! RXTHRESHOLD - Receive NACK Threshold 13108 */ 13109 #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK) 13110 13111 #define UART_ET7816_TXTHRESHOLD_MASK (0xF0U) 13112 #define UART_ET7816_TXTHRESHOLD_SHIFT (4U) 13113 /*! TXTHRESHOLD - Transmit NACK Threshold 13114 * 0b0000..TXT asserts on the first NACK that is received. 13115 * 0b0001..TXT asserts on the second NACK that is received. 13116 */ 13117 #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK) 13118 /*! @} */ 13119 13120 /*! @name TL7816 - UART 7816 Transmit Length Register */ 13121 /*! @{ */ 13122 13123 #define UART_TL7816_TLEN_MASK (0xFFU) 13124 #define UART_TL7816_TLEN_SHIFT (0U) 13125 /*! TLEN - Transmit Length 13126 */ 13127 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK) 13128 /*! @} */ 13129 13130 13131 /*! 13132 * @} 13133 */ /* end of group UART_Register_Masks */ 13134 13135 13136 /* UART - Peripheral instance base addresses */ 13137 /** Peripheral UART0 base address */ 13138 #define UART0_BASE (0x4006A000u) 13139 /** Peripheral UART0 base pointer */ 13140 #define UART0 ((UART_Type *)UART0_BASE) 13141 /** Peripheral UART1 base address */ 13142 #define UART1_BASE (0x4006B000u) 13143 /** Peripheral UART1 base pointer */ 13144 #define UART1 ((UART_Type *)UART1_BASE) 13145 /** Peripheral UART2 base address */ 13146 #define UART2_BASE (0x4006C000u) 13147 /** Peripheral UART2 base pointer */ 13148 #define UART2 ((UART_Type *)UART2_BASE) 13149 /** Peripheral UART3 base address */ 13150 #define UART3_BASE (0x4006D000u) 13151 /** Peripheral UART3 base pointer */ 13152 #define UART3 ((UART_Type *)UART3_BASE) 13153 /** Array initializer of UART peripheral base addresses */ 13154 #define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE } 13155 /** Array initializer of UART peripheral base pointers */ 13156 #define UART_BASE_PTRS { UART0, UART1, UART2, UART3 } 13157 /** Interrupt vectors for the UART peripheral type */ 13158 #define UART_RX_TX_IRQS { UART0_UART1_IRQn, UART0_UART1_IRQn, UART2_UART3_IRQn, UART2_UART3_IRQn } 13159 #define UART_ERR_IRQS { UART0_UART1_IRQn, UART0_UART1_IRQn, UART2_UART3_IRQn, UART2_UART3_IRQn } 13160 13161 /*! 13162 * @} 13163 */ /* end of group UART_Peripheral_Access_Layer */ 13164 13165 13166 /* ---------------------------------------------------------------------------- 13167 -- VREF Peripheral Access Layer 13168 ---------------------------------------------------------------------------- */ 13169 13170 /*! 13171 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer 13172 * @{ 13173 */ 13174 13175 /** VREF - Register Layout Typedef */ 13176 typedef struct { 13177 __IO uint8_t VREFH_TRM; /**< VREF Trim Register, offset: 0x0 */ 13178 __IO uint8_t VREFH_SC; /**< VREF Status and Control Register, offset: 0x1 */ 13179 uint8_t RESERVED_0[3]; 13180 __IO uint8_t VREFL_TRM; /**< VREFL TRIM Register, offset: 0x5 */ 13181 } VREF_Type; 13182 13183 /* ---------------------------------------------------------------------------- 13184 -- VREF Register Masks 13185 ---------------------------------------------------------------------------- */ 13186 13187 /*! 13188 * @addtogroup VREF_Register_Masks VREF Register Masks 13189 * @{ 13190 */ 13191 13192 /*! @name VREFH_TRM - VREF Trim Register */ 13193 /*! @{ */ 13194 13195 #define VREF_VREFH_TRM_TRIM_MASK (0x3FU) 13196 #define VREF_VREFH_TRM_TRIM_SHIFT (0U) 13197 /*! TRIM - Trim bits 13198 * 0b000000..Min 13199 * 0b111111..Max 13200 */ 13201 #define VREF_VREFH_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_VREFH_TRM_TRIM_SHIFT)) & VREF_VREFH_TRM_TRIM_MASK) 13202 13203 #define VREF_VREFH_TRM_CHOPEN_MASK (0x40U) 13204 #define VREF_VREFH_TRM_CHOPEN_SHIFT (6U) 13205 /*! CHOPEN - Chop oscillator enable. When set, internal chopping operation is enabled and the 13206 * internal analog offset will be minimized. 13207 * 0b0..Chop oscillator is disabled. 13208 * 0b1..Chop oscillator is enabled. 13209 */ 13210 #define VREF_VREFH_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_VREFH_TRM_CHOPEN_SHIFT)) & VREF_VREFH_TRM_CHOPEN_MASK) 13211 /*! @} */ 13212 13213 /*! @name VREFH_SC - VREF Status and Control Register */ 13214 /*! @{ */ 13215 13216 #define VREF_VREFH_SC_MODE_LV_MASK (0x3U) 13217 #define VREF_VREFH_SC_MODE_LV_SHIFT (0U) 13218 /*! MODE_LV - Buffer Mode selection 13219 * 0b00..Bandgap on only, for stabilization and startup 13220 * 0b01..High power buffer mode enabled 13221 * 0b10..Low-power buffer mode enabled 13222 * 0b11..Reserved 13223 */ 13224 #define VREF_VREFH_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_VREFH_SC_MODE_LV_SHIFT)) & VREF_VREFH_SC_MODE_LV_MASK) 13225 13226 #define VREF_VREFH_SC_VREFST_MASK (0x4U) 13227 #define VREF_VREFH_SC_VREFST_SHIFT (2U) 13228 /*! VREFST - Internal Voltage Reference stable 13229 * 0b0..The module is disabled or not stable. 13230 * 0b1..The module is stable. 13231 */ 13232 #define VREF_VREFH_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_VREFH_SC_VREFST_SHIFT)) & VREF_VREFH_SC_VREFST_MASK) 13233 13234 #define VREF_VREFH_SC_ICOMPEN_MASK (0x20U) 13235 #define VREF_VREFH_SC_ICOMPEN_SHIFT (5U) 13236 /*! ICOMPEN - Second order curvature compensation enable 13237 * 0b0..Disabled 13238 * 0b1..Enabled 13239 */ 13240 #define VREF_VREFH_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_VREFH_SC_ICOMPEN_SHIFT)) & VREF_VREFH_SC_ICOMPEN_MASK) 13241 13242 #define VREF_VREFH_SC_REGEN_MASK (0x40U) 13243 #define VREF_VREFH_SC_REGEN_SHIFT (6U) 13244 /*! REGEN - Regulator enable 13245 * 0b0..Internal 1.75 V regulator is disabled. 13246 * 0b1..Internal 1.75 V regulator is enabled. 13247 */ 13248 #define VREF_VREFH_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_VREFH_SC_REGEN_SHIFT)) & VREF_VREFH_SC_REGEN_MASK) 13249 13250 #define VREF_VREFH_SC_VREFEN_MASK (0x80U) 13251 #define VREF_VREFH_SC_VREFEN_SHIFT (7U) 13252 /*! VREFEN - Internal Voltage Reference enable 13253 * 0b0..The module is disabled. 13254 * 0b1..The module is enabled. 13255 */ 13256 #define VREF_VREFH_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_VREFH_SC_VREFEN_SHIFT)) & VREF_VREFH_SC_VREFEN_MASK) 13257 /*! @} */ 13258 13259 /*! @name VREFL_TRM - VREFL TRIM Register */ 13260 /*! @{ */ 13261 13262 #define VREF_VREFL_TRM_VREFL_TRIM_MASK (0x7U) 13263 #define VREF_VREFL_TRM_VREFL_TRIM_SHIFT (0U) 13264 #define VREF_VREFL_TRM_VREFL_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_VREFL_TRM_VREFL_TRIM_SHIFT)) & VREF_VREFL_TRM_VREFL_TRIM_MASK) 13265 13266 #define VREF_VREFL_TRM_VREFL_EN_MASK (0x8U) 13267 #define VREF_VREFL_TRM_VREFL_EN_SHIFT (3U) 13268 /*! VREFL_EN 13269 * 0b0..Disable 13270 * 0b1..Enable 13271 */ 13272 #define VREF_VREFL_TRM_VREFL_EN(x) (((uint8_t)(((uint8_t)(x)) << VREF_VREFL_TRM_VREFL_EN_SHIFT)) & VREF_VREFL_TRM_VREFL_EN_MASK) 13273 13274 #define VREF_VREFL_TRM_VREFL_SEL_MASK (0x10U) 13275 #define VREF_VREFL_TRM_VREFL_SEL_SHIFT (4U) 13276 /*! VREFL_SEL 13277 * 0b0..Internal reference 13278 * 0b1..External reference 13279 */ 13280 #define VREF_VREFL_TRM_VREFL_SEL(x) (((uint8_t)(((uint8_t)(x)) << VREF_VREFL_TRM_VREFL_SEL_SHIFT)) & VREF_VREFL_TRM_VREFL_SEL_MASK) 13281 /*! @} */ 13282 13283 13284 /*! 13285 * @} 13286 */ /* end of group VREF_Register_Masks */ 13287 13288 13289 /* VREF - Peripheral instance base addresses */ 13290 /** Peripheral VREF base address */ 13291 #define VREF_BASE (0x4006F000u) 13292 /** Peripheral VREF base pointer */ 13293 #define VREF ((VREF_Type *)VREF_BASE) 13294 /** Array initializer of VREF peripheral base addresses */ 13295 #define VREF_BASE_ADDRS { VREF_BASE } 13296 /** Array initializer of VREF peripheral base pointers */ 13297 #define VREF_BASE_PTRS { VREF } 13298 13299 /*! 13300 * @} 13301 */ /* end of group VREF_Peripheral_Access_Layer */ 13302 13303 13304 /* ---------------------------------------------------------------------------- 13305 -- WDOG Peripheral Access Layer 13306 ---------------------------------------------------------------------------- */ 13307 13308 /*! 13309 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer 13310 * @{ 13311 */ 13312 13313 /** WDOG - Register Layout Typedef */ 13314 typedef struct { 13315 __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */ 13316 __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */ 13317 __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */ 13318 __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */ 13319 __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */ 13320 __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */ 13321 __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */ 13322 __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */ 13323 __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */ 13324 __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */ 13325 __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */ 13326 __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */ 13327 } WDOG_Type; 13328 13329 /* ---------------------------------------------------------------------------- 13330 -- WDOG Register Masks 13331 ---------------------------------------------------------------------------- */ 13332 13333 /*! 13334 * @addtogroup WDOG_Register_Masks WDOG Register Masks 13335 * @{ 13336 */ 13337 13338 /*! @name STCTRLH - Watchdog Status and Control Register High */ 13339 /*! @{ */ 13340 13341 #define WDOG_STCTRLH_WDOGEN_MASK (0x1U) 13342 #define WDOG_STCTRLH_WDOGEN_SHIFT (0U) 13343 /*! WDOGEN 13344 * 0b0..WDOG is disabled. 13345 * 0b1..WDOG is enabled. 13346 */ 13347 #define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK) 13348 13349 #define WDOG_STCTRLH_CLKSRC_MASK (0x2U) 13350 #define WDOG_STCTRLH_CLKSRC_SHIFT (1U) 13351 /*! CLKSRC 13352 * 0b0..WDOG clock sourced from LPO . 13353 * 0b1..WDOG clock sourced from alternate clock source. 13354 */ 13355 #define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK) 13356 13357 #define WDOG_STCTRLH_IRQRSTEN_MASK (0x4U) 13358 #define WDOG_STCTRLH_IRQRSTEN_SHIFT (2U) 13359 /*! IRQRSTEN 13360 * 0b0..WDOG time-out generates reset only. 13361 * 0b1..WDOG time-out initially generates an interrupt. After WCT, it generates a reset. 13362 */ 13363 #define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK) 13364 13365 #define WDOG_STCTRLH_WINEN_MASK (0x8U) 13366 #define WDOG_STCTRLH_WINEN_SHIFT (3U) 13367 /*! WINEN 13368 * 0b0..Windowing mode is disabled. 13369 * 0b1..Windowing mode is enabled. 13370 */ 13371 #define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK) 13372 13373 #define WDOG_STCTRLH_ALLOWUPDATE_MASK (0x10U) 13374 #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT (4U) 13375 /*! ALLOWUPDATE 13376 * 0b0..No further updates allowed to WDOG write-once registers. 13377 * 0b1..WDOG write-once registers can be unlocked for updating. 13378 */ 13379 #define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK) 13380 13381 #define WDOG_STCTRLH_DBGEN_MASK (0x20U) 13382 #define WDOG_STCTRLH_DBGEN_SHIFT (5U) 13383 /*! DBGEN 13384 * 0b0..WDOG is disabled in CPU Debug mode. 13385 * 0b1..WDOG is enabled in CPU Debug mode. 13386 */ 13387 #define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK) 13388 13389 #define WDOG_STCTRLH_STOPEN_MASK (0x40U) 13390 #define WDOG_STCTRLH_STOPEN_SHIFT (6U) 13391 /*! STOPEN 13392 * 0b0..WDOG is disabled in CPU Stop mode. 13393 * 0b1..WDOG is enabled in CPU Stop mode. 13394 */ 13395 #define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK) 13396 13397 #define WDOG_STCTRLH_TESTWDOG_MASK (0x400U) 13398 #define WDOG_STCTRLH_TESTWDOG_SHIFT (10U) 13399 #define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK) 13400 13401 #define WDOG_STCTRLH_TESTSEL_MASK (0x800U) 13402 #define WDOG_STCTRLH_TESTSEL_SHIFT (11U) 13403 /*! TESTSEL 13404 * 0b0..Quick test. The timer runs in normal operation. You can load a small time-out value to do a quick test. 13405 * 0b1..Byte test. Puts the timer in the byte test mode where individual bytes of the timer are enabled for 13406 * operation and are compared for time-out against the corresponding byte of the programmed time-out value. Select 13407 * the byte through BYTESEL[1:0] for testing. 13408 */ 13409 #define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK) 13410 13411 #define WDOG_STCTRLH_BYTESEL_MASK (0x3000U) 13412 #define WDOG_STCTRLH_BYTESEL_SHIFT (12U) 13413 /*! BYTESEL 13414 * 0b00..Byte 0 selected 13415 * 0b01..Byte 1 selected 13416 * 0b10..Byte 2 selected 13417 * 0b11..Byte 3 selected 13418 */ 13419 #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK) 13420 13421 #define WDOG_STCTRLH_DISTESTWDOG_MASK (0x4000U) 13422 #define WDOG_STCTRLH_DISTESTWDOG_SHIFT (14U) 13423 /*! DISTESTWDOG 13424 * 0b0..WDOG functional test mode is not disabled. 13425 * 0b1..WDOG functional test mode is disabled permanently until reset. 13426 */ 13427 #define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK) 13428 /*! @} */ 13429 13430 /*! @name STCTRLL - Watchdog Status and Control Register Low */ 13431 /*! @{ */ 13432 13433 #define WDOG_STCTRLL_INTFLG_MASK (0x8000U) 13434 #define WDOG_STCTRLL_INTFLG_SHIFT (15U) 13435 #define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK) 13436 /*! @} */ 13437 13438 /*! @name TOVALH - Watchdog Time-out Value Register High */ 13439 /*! @{ */ 13440 13441 #define WDOG_TOVALH_TOVALHIGH_MASK (0xFFFFU) 13442 #define WDOG_TOVALH_TOVALHIGH_SHIFT (0U) 13443 #define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK) 13444 /*! @} */ 13445 13446 /*! @name TOVALL - Watchdog Time-out Value Register Low */ 13447 /*! @{ */ 13448 13449 #define WDOG_TOVALL_TOVALLOW_MASK (0xFFFFU) 13450 #define WDOG_TOVALL_TOVALLOW_SHIFT (0U) 13451 #define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK) 13452 /*! @} */ 13453 13454 /*! @name WINH - Watchdog Window Register High */ 13455 /*! @{ */ 13456 13457 #define WDOG_WINH_WINHIGH_MASK (0xFFFFU) 13458 #define WDOG_WINH_WINHIGH_SHIFT (0U) 13459 #define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK) 13460 /*! @} */ 13461 13462 /*! @name WINL - Watchdog Window Register Low */ 13463 /*! @{ */ 13464 13465 #define WDOG_WINL_WINLOW_MASK (0xFFFFU) 13466 #define WDOG_WINL_WINLOW_SHIFT (0U) 13467 #define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK) 13468 /*! @} */ 13469 13470 /*! @name REFRESH - Watchdog Refresh register */ 13471 /*! @{ */ 13472 13473 #define WDOG_REFRESH_WDOGREFRESH_MASK (0xFFFFU) 13474 #define WDOG_REFRESH_WDOGREFRESH_SHIFT (0U) 13475 #define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK) 13476 /*! @} */ 13477 13478 /*! @name UNLOCK - Watchdog Unlock register */ 13479 /*! @{ */ 13480 13481 #define WDOG_UNLOCK_WDOGUNLOCK_MASK (0xFFFFU) 13482 #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT (0U) 13483 #define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK) 13484 /*! @} */ 13485 13486 /*! @name TMROUTH - Watchdog Timer Output Register High */ 13487 /*! @{ */ 13488 13489 #define WDOG_TMROUTH_TIMEROUTHIGH_MASK (0xFFFFU) 13490 #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT (0U) 13491 #define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK) 13492 /*! @} */ 13493 13494 /*! @name TMROUTL - Watchdog Timer Output Register Low */ 13495 /*! @{ */ 13496 13497 #define WDOG_TMROUTL_TIMEROUTLOW_MASK (0xFFFFU) 13498 #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT (0U) 13499 #define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK) 13500 /*! @} */ 13501 13502 /*! @name RSTCNT - Watchdog Reset Count register */ 13503 /*! @{ */ 13504 13505 #define WDOG_RSTCNT_RSTCNT_MASK (0xFFFFU) 13506 #define WDOG_RSTCNT_RSTCNT_SHIFT (0U) 13507 #define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK) 13508 /*! @} */ 13509 13510 /*! @name PRESC - Watchdog Prescaler register */ 13511 /*! @{ */ 13512 13513 #define WDOG_PRESC_PRESCVAL_MASK (0x700U) 13514 #define WDOG_PRESC_PRESCVAL_SHIFT (8U) 13515 #define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK) 13516 /*! @} */ 13517 13518 13519 /*! 13520 * @} 13521 */ /* end of group WDOG_Register_Masks */ 13522 13523 13524 /* WDOG - Peripheral instance base addresses */ 13525 /** Peripheral WDOG base address */ 13526 #define WDOG_BASE (0x40053000u) 13527 /** Peripheral WDOG base pointer */ 13528 #define WDOG ((WDOG_Type *)WDOG_BASE) 13529 /** Array initializer of WDOG peripheral base addresses */ 13530 #define WDOG_BASE_ADDRS { WDOG_BASE } 13531 /** Array initializer of WDOG peripheral base pointers */ 13532 #define WDOG_BASE_PTRS { WDOG } 13533 /** Interrupt vectors for the WDOG peripheral type */ 13534 #define WDOG_IRQS { WDOG_IRQn } 13535 13536 /*! 13537 * @} 13538 */ /* end of group WDOG_Peripheral_Access_Layer */ 13539 13540 13541 /* ---------------------------------------------------------------------------- 13542 -- XBAR Peripheral Access Layer 13543 ---------------------------------------------------------------------------- */ 13544 13545 /*! 13546 * @addtogroup XBAR_Peripheral_Access_Layer XBAR Peripheral Access Layer 13547 * @{ 13548 */ 13549 13550 /** XBAR - Register Layout Typedef */ 13551 typedef struct { 13552 __IO uint16_t SEL0; /**< Crossbar Select Register 0, offset: 0x0 */ 13553 __IO uint16_t SEL1; /**< Crossbar Select Register 1, offset: 0x2 */ 13554 __IO uint16_t SEL2; /**< Crossbar Select Register 2, offset: 0x4 */ 13555 __IO uint16_t SEL3; /**< Crossbar Select Register 3, offset: 0x6 */ 13556 __IO uint16_t SEL4; /**< Crossbar Select Register 4, offset: 0x8 */ 13557 __IO uint16_t SEL5; /**< Crossbar Select Register 5, offset: 0xA */ 13558 __IO uint16_t SEL6; /**< Crossbar Select Register 6, offset: 0xC */ 13559 __IO uint16_t SEL7; /**< Crossbar Select Register 7, offset: 0xE */ 13560 __IO uint16_t SEL8; /**< Crossbar Select Register 8, offset: 0x10 */ 13561 __IO uint16_t SEL9; /**< Crossbar Select Register 9, offset: 0x12 */ 13562 __IO uint16_t SEL10; /**< Crossbar Select Register 10, offset: 0x14 */ 13563 __IO uint16_t SEL11; /**< Crossbar Select Register 11, offset: 0x16 */ 13564 __IO uint16_t SEL12; /**< Crossbar Select Register 12, offset: 0x18 */ 13565 __IO uint16_t SEL13; /**< Crossbar Select Register 13, offset: 0x1A */ 13566 __IO uint16_t SEL14; /**< Crossbar Select Register 14, offset: 0x1C */ 13567 __IO uint16_t SEL15; /**< Crossbar Select Register 15, offset: 0x1E */ 13568 __IO uint16_t SEL16; /**< Crossbar Select Register 16, offset: 0x20 */ 13569 __IO uint16_t CTRL0; /**< Crossbar Control Register 0, offset: 0x22 */ 13570 } XBAR_Type; 13571 13572 /* ---------------------------------------------------------------------------- 13573 -- XBAR Register Masks 13574 ---------------------------------------------------------------------------- */ 13575 13576 /*! 13577 * @addtogroup XBAR_Register_Masks XBAR Register Masks 13578 * @{ 13579 */ 13580 13581 /*! @name SEL0 - Crossbar Select Register 0 */ 13582 /*! @{ */ 13583 13584 #define XBAR_SEL0_SEL0_MASK (0x3FU) 13585 #define XBAR_SEL0_SEL0_SHIFT (0U) 13586 /*! SEL0 13587 * 0b000000..Logic 1 (VDD) 13588 * 0b000001..Logic 0 (VSS) 13589 * 0b000010..AFE modulator clock output 13590 * 0b000011..AFE modulator data output 13591 * 0b000100..LPTimer Output 13592 * 0b000101..Clock Output 13593 * 0b000110..Quad Timer channel 0 output 13594 * 0b000111..Quad Timer channel 1 output 13595 * 0b001000..Quad Timer channel 2 output 13596 * 0b001001..Quad Timer channel 3 output 13597 * 0b001010..iRTC Clock Output 13598 * 0b001011..CMP0 Output 13599 * 0b001100..CMP1 Output 13600 * 0b001101..iRTC Alarm Output 13601 * 0b001110..UART TX Output (after modulation) 13602 * 0b001111..EWM Output (EWM_OUT) 13603 * 0b010000..PIT Output 13604 * 0b010001..XBAR Input pin 0 13605 * 0b010010..XBAR Input pin 1 13606 * 0b010011..XBAR Input pin 2 13607 * 0b010100..XBAR Input pin 3 13608 * 0b010101..XBAR Input pin 4 13609 * 0b010110..XBAR Input pin 5 13610 * 0b010111..XBAR Input pin 6 13611 * 0b011000..XBAR Input pin 7 13612 * 0b011001..XBAR Input pin 8 13613 * 0b011010..ORed conversion complete flag for all SAR ADC channels 13614 * 0b011011..ORed conversion complete flag for all AFE channels 13615 * 0b011100..AFE Channel 0 conversion complete 13616 * 0b011101..AFE Channel 1 conversion complete 13617 * 0b011110..AFE Channel 2 conversion complete 13618 * 0b011111..AFE Channel 3 conversion complete 13619 * 0b100000..DMA Done Signal 13620 */ 13621 #define XBAR_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL0_SEL0_SHIFT)) & XBAR_SEL0_SEL0_MASK) 13622 13623 #define XBAR_SEL0_SEL1_MASK (0x3F00U) 13624 #define XBAR_SEL0_SEL1_SHIFT (8U) 13625 /*! SEL1 13626 * 0b000000..Logic 1 (VDD) 13627 * 0b000001..Logic 0 (VSS) 13628 * 0b000010..AFE modulator clock output 13629 * 0b000011..AFE modulator data output 13630 * 0b000100..LPTimer Output 13631 * 0b000101..Clock Output 13632 * 0b000110..Quad Timer channel 0 output 13633 * 0b000111..Quad Timer channel 1 output 13634 * 0b001000..Quad Timer channel 2 output 13635 * 0b001001..Quad Timer channel 3 output 13636 * 0b001010..iRTC Clock Output 13637 * 0b001011..CMP0 Output 13638 * 0b001100..CMP1 Output 13639 * 0b001101..iRTC Alarm Output 13640 * 0b001110..UART TX Output (after modulation) 13641 * 0b001111..EWM Output (EWM_OUT) 13642 * 0b010000..PIT Output 13643 * 0b010001..XBAR Input pin 0 13644 * 0b010010..XBAR Input pin 1 13645 * 0b010011..XBAR Input pin 2 13646 * 0b010100..XBAR Input pin 3 13647 * 0b010101..XBAR Input pin 4 13648 * 0b010110..XBAR Input pin 5 13649 * 0b010111..XBAR Input pin 6 13650 * 0b011000..XBAR Input pin 7 13651 * 0b011001..XBAR Input pin 8 13652 * 0b011010..ORed conversion complete flag for all SAR ADC channels 13653 * 0b011011..ORed conversion complete flag for all AFE channels 13654 * 0b011100..AFE Channel 0 conversion complete 13655 * 0b011101..AFE Channel 1 conversion complete 13656 * 0b011110..AFE Channel 2 conversion complete 13657 * 0b011111..AFE Channel 3 conversion complete 13658 * 0b100000..DMA Done Signal 13659 */ 13660 #define XBAR_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL0_SEL1_SHIFT)) & XBAR_SEL0_SEL1_MASK) 13661 /*! @} */ 13662 13663 /*! @name SEL1 - Crossbar Select Register 1 */ 13664 /*! @{ */ 13665 13666 #define XBAR_SEL1_SEL2_MASK (0x3FU) 13667 #define XBAR_SEL1_SEL2_SHIFT (0U) 13668 /*! SEL2 13669 * 0b000000..Logic 1 (VDD) 13670 * 0b000001..Logic 0 (VSS) 13671 * 0b000010..AFE modulator clock output 13672 * 0b000011..AFE modulator data output 13673 * 0b000100..LPTimer Output 13674 * 0b000101..Clock Output 13675 * 0b000110..Quad Timer channel 0 output 13676 * 0b000111..Quad Timer channel 1 output 13677 * 0b001000..Quad Timer channel 2 output 13678 * 0b001001..Quad Timer channel 3 output 13679 * 0b001010..iRTC Clock Output 13680 * 0b001011..CMP0 Output 13681 * 0b001100..CMP1 Output 13682 * 0b001101..iRTC Alarm Output 13683 * 0b001110..UART TX Output (after modulation) 13684 * 0b001111..EWM Output (EWM_OUT) 13685 * 0b010000..PIT Output 13686 * 0b010001..XBAR Input pin 0 13687 * 0b010010..XBAR Input pin 1 13688 * 0b010011..XBAR Input pin 2 13689 * 0b010100..XBAR Input pin 3 13690 * 0b010101..XBAR Input pin 4 13691 * 0b010110..XBAR Input pin 5 13692 * 0b010111..XBAR Input pin 6 13693 * 0b011000..XBAR Input pin 7 13694 * 0b011001..XBAR Input pin 8 13695 * 0b011010..ORed conversion complete flag for all SAR ADC channels 13696 * 0b011011..ORed conversion complete flag for all AFE channels 13697 * 0b011100..AFE Channel 0 conversion complete 13698 * 0b011101..AFE Channel 1 conversion complete 13699 * 0b011110..AFE Channel 2 conversion complete 13700 * 0b011111..AFE Channel 3 conversion complete 13701 * 0b100000..DMA Done Signal 13702 */ 13703 #define XBAR_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL1_SEL2_SHIFT)) & XBAR_SEL1_SEL2_MASK) 13704 13705 #define XBAR_SEL1_SEL3_MASK (0x3F00U) 13706 #define XBAR_SEL1_SEL3_SHIFT (8U) 13707 /*! SEL3 13708 * 0b000000..Logic 1 (VDD) 13709 * 0b000001..Logic 0 (VSS) 13710 * 0b000010..AFE modulator clock output 13711 * 0b000011..AFE modulator data output 13712 * 0b000100..LPTimer Output 13713 * 0b000101..Clock Output 13714 * 0b000110..Quad Timer channel 0 output 13715 * 0b000111..Quad Timer channel 1 output 13716 * 0b001000..Quad Timer channel 2 output 13717 * 0b001001..Quad Timer channel 3 output 13718 * 0b001010..iRTC Clock Output 13719 * 0b001011..CMP0 Output 13720 * 0b001100..CMP1 Output 13721 * 0b001101..iRTC Alarm Output 13722 * 0b001110..UART TX Output (after modulation) 13723 * 0b001111..EWM Output (EWM_OUT) 13724 * 0b010000..PIT Output 13725 * 0b010001..XBAR Input pin 0 13726 * 0b010010..XBAR Input pin 1 13727 * 0b010011..XBAR Input pin 2 13728 * 0b010100..XBAR Input pin 3 13729 * 0b010101..XBAR Input pin 4 13730 * 0b010110..XBAR Input pin 5 13731 * 0b010111..XBAR Input pin 6 13732 * 0b011000..XBAR Input pin 7 13733 * 0b011001..XBAR Input pin 8 13734 * 0b011010..ORed conversion complete flag for all SAR ADC channels 13735 * 0b011011..ORed conversion complete flag for all AFE channels 13736 * 0b011100..AFE Channel 0 conversion complete 13737 * 0b011101..AFE Channel 1 conversion complete 13738 * 0b011110..AFE Channel 2 conversion complete 13739 * 0b011111..AFE Channel 3 conversion complete 13740 * 0b100000..DMA Done Signal 13741 */ 13742 #define XBAR_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL1_SEL3_SHIFT)) & XBAR_SEL1_SEL3_MASK) 13743 /*! @} */ 13744 13745 /*! @name SEL2 - Crossbar Select Register 2 */ 13746 /*! @{ */ 13747 13748 #define XBAR_SEL2_SEL4_MASK (0x3FU) 13749 #define XBAR_SEL2_SEL4_SHIFT (0U) 13750 /*! SEL4 13751 * 0b000000..Logic 1 (VDD) 13752 * 0b000001..Logic 0 (VSS) 13753 * 0b000010..AFE modulator clock output 13754 * 0b000011..AFE modulator data output 13755 * 0b000100..LPTimer Output 13756 * 0b000101..Clock Output 13757 * 0b000110..Quad Timer channel 0 output 13758 * 0b000111..Quad Timer channel 1 output 13759 * 0b001000..Quad Timer channel 2 output 13760 * 0b001001..Quad Timer channel 3 output 13761 * 0b001010..iRTC Clock Output 13762 * 0b001011..CMP0 Output 13763 * 0b001100..CMP1 Output 13764 * 0b001101..iRTC Alarm Output 13765 * 0b001110..UART TX Output (after modulation) 13766 * 0b001111..EWM Output (EWM_OUT) 13767 * 0b010000..PIT Output 13768 * 0b010001..XBAR Input pin 0 13769 * 0b010010..XBAR Input pin 1 13770 * 0b010011..XBAR Input pin 2 13771 * 0b010100..XBAR Input pin 3 13772 * 0b010101..XBAR Input pin 4 13773 * 0b010110..XBAR Input pin 5 13774 * 0b010111..XBAR Input pin 6 13775 * 0b011000..XBAR Input pin 7 13776 * 0b011001..XBAR Input pin 8 13777 * 0b011010..ORed conversion complete flag for all SAR ADC channels 13778 * 0b011011..ORed conversion complete flag for all AFE channels 13779 * 0b011100..AFE Channel 0 conversion complete 13780 * 0b011101..AFE Channel 1 conversion complete 13781 * 0b011110..AFE Channel 2 conversion complete 13782 * 0b011111..AFE Channel 3 conversion complete 13783 * 0b100000..DMA Done Signal 13784 */ 13785 #define XBAR_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL2_SEL4_SHIFT)) & XBAR_SEL2_SEL4_MASK) 13786 13787 #define XBAR_SEL2_SEL5_MASK (0x3F00U) 13788 #define XBAR_SEL2_SEL5_SHIFT (8U) 13789 /*! SEL5 13790 * 0b000000..Logic 1 (VDD) 13791 * 0b000001..Logic 0 (VSS) 13792 * 0b000010..AFE modulator clock output 13793 * 0b000011..AFE modulator data output 13794 * 0b000100..LPTimer Output 13795 * 0b000101..Clock Output 13796 * 0b000110..Quad Timer channel 0 output 13797 * 0b000111..Quad Timer channel 1 output 13798 * 0b001000..Quad Timer channel 2 output 13799 * 0b001001..Quad Timer channel 3 output 13800 * 0b001010..iRTC Clock Output 13801 * 0b001011..CMP0 Output 13802 * 0b001100..CMP1 Output 13803 * 0b001101..iRTC Alarm Output 13804 * 0b001110..UART TX Output (after modulation) 13805 * 0b001111..EWM Output (EWM_OUT) 13806 * 0b010000..PIT Output 13807 * 0b010001..XBAR Input pin 0 13808 * 0b010010..XBAR Input pin 1 13809 * 0b010011..XBAR Input pin 2 13810 * 0b010100..XBAR Input pin 3 13811 * 0b010101..XBAR Input pin 4 13812 * 0b010110..XBAR Input pin 5 13813 * 0b010111..XBAR Input pin 6 13814 * 0b011000..XBAR Input pin 7 13815 * 0b011001..XBAR Input pin 8 13816 * 0b011010..ORed conversion complete flag for all SAR ADC channels 13817 * 0b011011..ORed conversion complete flag for all AFE channels 13818 * 0b011100..AFE Channel 0 conversion complete 13819 * 0b011101..AFE Channel 1 conversion complete 13820 * 0b011110..AFE Channel 2 conversion complete 13821 * 0b011111..AFE Channel 3 conversion complete 13822 * 0b100000..DMA Done Signal 13823 */ 13824 #define XBAR_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL2_SEL5_SHIFT)) & XBAR_SEL2_SEL5_MASK) 13825 /*! @} */ 13826 13827 /*! @name SEL3 - Crossbar Select Register 3 */ 13828 /*! @{ */ 13829 13830 #define XBAR_SEL3_SEL6_MASK (0x3FU) 13831 #define XBAR_SEL3_SEL6_SHIFT (0U) 13832 /*! SEL6 13833 * 0b000000..Logic 1 (VDD) 13834 * 0b000001..Logic 0 (VSS) 13835 * 0b000010..AFE modulator clock output 13836 * 0b000011..AFE modulator data output 13837 * 0b000100..LPTimer Output 13838 * 0b000101..Clock Output 13839 * 0b000110..Quad Timer channel 0 output 13840 * 0b000111..Quad Timer channel 1 output 13841 * 0b001000..Quad Timer channel 2 output 13842 * 0b001001..Quad Timer channel 3 output 13843 * 0b001010..iRTC Clock Output 13844 * 0b001011..CMP0 Output 13845 * 0b001100..CMP1 Output 13846 * 0b001101..iRTC Alarm Output 13847 * 0b001110..UART TX Output (after modulation) 13848 * 0b001111..EWM Output (EWM_OUT) 13849 * 0b010000..PIT Output 13850 * 0b010001..XBAR Input pin 0 13851 * 0b010010..XBAR Input pin 1 13852 * 0b010011..XBAR Input pin 2 13853 * 0b010100..XBAR Input pin 3 13854 * 0b010101..XBAR Input pin 4 13855 * 0b010110..XBAR Input pin 5 13856 * 0b010111..XBAR Input pin 6 13857 * 0b011000..XBAR Input pin 7 13858 * 0b011001..XBAR Input pin 8 13859 * 0b011010..ORed conversion complete flag for all SAR ADC channels 13860 * 0b011011..ORed conversion complete flag for all AFE channels 13861 * 0b011100..AFE Channel 0 conversion complete 13862 * 0b011101..AFE Channel 1 conversion complete 13863 * 0b011110..AFE Channel 2 conversion complete 13864 * 0b011111..AFE Channel 3 conversion complete 13865 * 0b100000..DMA Done Signal 13866 */ 13867 #define XBAR_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL3_SEL6_SHIFT)) & XBAR_SEL3_SEL6_MASK) 13868 13869 #define XBAR_SEL3_SEL7_MASK (0x3F00U) 13870 #define XBAR_SEL3_SEL7_SHIFT (8U) 13871 /*! SEL7 13872 * 0b000000..Logic 1 (VDD) 13873 * 0b000001..Logic 0 (VSS) 13874 * 0b000010..AFE modulator clock output 13875 * 0b000011..AFE modulator data output 13876 * 0b000100..LPTimer Output 13877 * 0b000101..Clock Output 13878 * 0b000110..Quad Timer channel 0 output 13879 * 0b000111..Quad Timer channel 1 output 13880 * 0b001000..Quad Timer channel 2 output 13881 * 0b001001..Quad Timer channel 3 output 13882 * 0b001010..iRTC Clock Output 13883 * 0b001011..CMP0 Output 13884 * 0b001100..CMP1 Output 13885 * 0b001101..iRTC Alarm Output 13886 * 0b001110..UART TX Output (after modulation) 13887 * 0b001111..EWM Output (EWM_OUT) 13888 * 0b010000..PIT Output 13889 * 0b010001..XBAR Input pin 0 13890 * 0b010010..XBAR Input pin 1 13891 * 0b010011..XBAR Input pin 2 13892 * 0b010100..XBAR Input pin 3 13893 * 0b010101..XBAR Input pin 4 13894 * 0b010110..XBAR Input pin 5 13895 * 0b010111..XBAR Input pin 6 13896 * 0b011000..XBAR Input pin 7 13897 * 0b011001..XBAR Input pin 8 13898 * 0b011010..ORed conversion complete flag for all SAR ADC channels 13899 * 0b011011..ORed conversion complete flag for all AFE channels 13900 * 0b011100..AFE Channel 0 conversion complete 13901 * 0b011101..AFE Channel 1 conversion complete 13902 * 0b011110..AFE Channel 2 conversion complete 13903 * 0b011111..AFE Channel 3 conversion complete 13904 * 0b100000..DMA Done Signal 13905 */ 13906 #define XBAR_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL3_SEL7_SHIFT)) & XBAR_SEL3_SEL7_MASK) 13907 /*! @} */ 13908 13909 /*! @name SEL4 - Crossbar Select Register 4 */ 13910 /*! @{ */ 13911 13912 #define XBAR_SEL4_SEL8_MASK (0x3FU) 13913 #define XBAR_SEL4_SEL8_SHIFT (0U) 13914 /*! SEL8 13915 * 0b000000..Logic 1 (VDD) 13916 * 0b000001..Logic 0 (VSS) 13917 * 0b000010..AFE modulator clock output 13918 * 0b000011..AFE modulator data output 13919 * 0b000100..LPTimer Output 13920 * 0b000101..Clock Output 13921 * 0b000110..Quad Timer channel 0 output 13922 * 0b000111..Quad Timer channel 1 output 13923 * 0b001000..Quad Timer channel 2 output 13924 * 0b001001..Quad Timer channel 3 output 13925 * 0b001010..iRTC Clock Output 13926 * 0b001011..CMP0 Output 13927 * 0b001100..CMP1 Output 13928 * 0b001101..iRTC Alarm Output 13929 * 0b001110..UART TX Output (after modulation) 13930 * 0b001111..EWM Output (EWM_OUT) 13931 * 0b010000..PIT Output 13932 * 0b010001..XBAR Input pin 0 13933 * 0b010010..XBAR Input pin 1 13934 * 0b010011..XBAR Input pin 2 13935 * 0b010100..XBAR Input pin 3 13936 * 0b010101..XBAR Input pin 4 13937 * 0b010110..XBAR Input pin 5 13938 * 0b010111..XBAR Input pin 6 13939 * 0b011000..XBAR Input pin 7 13940 * 0b011001..XBAR Input pin 8 13941 * 0b011010..ORed conversion complete flag for all SAR ADC channels 13942 * 0b011011..ORed conversion complete flag for all AFE channels 13943 * 0b011100..AFE Channel 0 conversion complete 13944 * 0b011101..AFE Channel 1 conversion complete 13945 * 0b011110..AFE Channel 2 conversion complete 13946 * 0b011111..AFE Channel 3 conversion complete 13947 * 0b100000..DMA Done Signal 13948 */ 13949 #define XBAR_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL4_SEL8_SHIFT)) & XBAR_SEL4_SEL8_MASK) 13950 13951 #define XBAR_SEL4_SEL9_MASK (0x3F00U) 13952 #define XBAR_SEL4_SEL9_SHIFT (8U) 13953 /*! SEL9 13954 * 0b000000..Logic 1 (VDD) 13955 * 0b000001..Logic 0 (VSS) 13956 * 0b000010..AFE modulator clock output 13957 * 0b000011..AFE modulator data output 13958 * 0b000100..LPTimer Output 13959 * 0b000101..Clock Output 13960 * 0b000110..Quad Timer channel 0 output 13961 * 0b000111..Quad Timer channel 1 output 13962 * 0b001000..Quad Timer channel 2 output 13963 * 0b001001..Quad Timer channel 3 output 13964 * 0b001010..iRTC Clock Output 13965 * 0b001011..CMP0 Output 13966 * 0b001100..CMP1 Output 13967 * 0b001101..iRTC Alarm Output 13968 * 0b001110..UART TX Output (after modulation) 13969 * 0b001111..EWM Output (EWM_OUT) 13970 * 0b010000..PIT Output 13971 * 0b010001..XBAR Input pin 0 13972 * 0b010010..XBAR Input pin 1 13973 * 0b010011..XBAR Input pin 2 13974 * 0b010100..XBAR Input pin 3 13975 * 0b010101..XBAR Input pin 4 13976 * 0b010110..XBAR Input pin 5 13977 * 0b010111..XBAR Input pin 6 13978 * 0b011000..XBAR Input pin 7 13979 * 0b011001..XBAR Input pin 8 13980 * 0b011010..ORed conversion complete flag for all SAR ADC channels 13981 * 0b011011..ORed conversion complete flag for all AFE channels 13982 * 0b011100..AFE Channel 0 conversion complete 13983 * 0b011101..AFE Channel 1 conversion complete 13984 * 0b011110..AFE Channel 2 conversion complete 13985 * 0b011111..AFE Channel 3 conversion complete 13986 * 0b100000..DMA Done Signal 13987 */ 13988 #define XBAR_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL4_SEL9_SHIFT)) & XBAR_SEL4_SEL9_MASK) 13989 /*! @} */ 13990 13991 /*! @name SEL5 - Crossbar Select Register 5 */ 13992 /*! @{ */ 13993 13994 #define XBAR_SEL5_SEL10_MASK (0x3FU) 13995 #define XBAR_SEL5_SEL10_SHIFT (0U) 13996 /*! SEL10 13997 * 0b000000..Logic 1 (VDD) 13998 * 0b000001..Logic 0 (VSS) 13999 * 0b000010..AFE modulator clock output 14000 * 0b000011..AFE modulator data output 14001 * 0b000100..LPTimer Output 14002 * 0b000101..Clock Output 14003 * 0b000110..Quad Timer channel 0 output 14004 * 0b000111..Quad Timer channel 1 output 14005 * 0b001000..Quad Timer channel 2 output 14006 * 0b001001..Quad Timer channel 3 output 14007 * 0b001010..iRTC Clock Output 14008 * 0b001011..CMP0 Output 14009 * 0b001100..CMP1 Output 14010 * 0b001101..iRTC Alarm Output 14011 * 0b001110..UART TX Output (after modulation) 14012 * 0b001111..EWM Output (EWM_OUT) 14013 * 0b010000..PIT Output 14014 * 0b010001..XBAR Input pin 0 14015 * 0b010010..XBAR Input pin 1 14016 * 0b010011..XBAR Input pin 2 14017 * 0b010100..XBAR Input pin 3 14018 * 0b010101..XBAR Input pin 4 14019 * 0b010110..XBAR Input pin 5 14020 * 0b010111..XBAR Input pin 6 14021 * 0b011000..XBAR Input pin 7 14022 * 0b011001..XBAR Input pin 8 14023 * 0b011010..ORed conversion complete flag for all SAR ADC channels 14024 * 0b011011..ORed conversion complete flag for all AFE channels 14025 * 0b011100..AFE Channel 0 conversion complete 14026 * 0b011101..AFE Channel 1 conversion complete 14027 * 0b011110..AFE Channel 2 conversion complete 14028 * 0b011111..AFE Channel 3 conversion complete 14029 * 0b100000..DMA Done Signal 14030 */ 14031 #define XBAR_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL5_SEL10_SHIFT)) & XBAR_SEL5_SEL10_MASK) 14032 14033 #define XBAR_SEL5_SEL11_MASK (0x3F00U) 14034 #define XBAR_SEL5_SEL11_SHIFT (8U) 14035 /*! SEL11 14036 * 0b000000..Logic 1 (VDD) 14037 * 0b000001..Logic 0 (VSS) 14038 * 0b000010..AFE modulator clock output 14039 * 0b000011..AFE modulator data output 14040 * 0b000100..LPTimer Output 14041 * 0b000101..Clock Output 14042 * 0b000110..Quad Timer channel 0 output 14043 * 0b000111..Quad Timer channel 1 output 14044 * 0b001000..Quad Timer channel 2 output 14045 * 0b001001..Quad Timer channel 3 output 14046 * 0b001010..iRTC Clock Output 14047 * 0b001011..CMP0 Output 14048 * 0b001100..CMP1 Output 14049 * 0b001101..iRTC Alarm Output 14050 * 0b001110..UART TX Output (after modulation) 14051 * 0b001111..EWM Output (EWM_OUT) 14052 * 0b010000..PIT Output 14053 * 0b010001..XBAR Input pin 0 14054 * 0b010010..XBAR Input pin 1 14055 * 0b010011..XBAR Input pin 2 14056 * 0b010100..XBAR Input pin 3 14057 * 0b010101..XBAR Input pin 4 14058 * 0b010110..XBAR Input pin 5 14059 * 0b010111..XBAR Input pin 6 14060 * 0b011000..XBAR Input pin 7 14061 * 0b011001..XBAR Input pin 8 14062 * 0b011010..ORed conversion complete flag for all SAR ADC channels 14063 * 0b011011..ORed conversion complete flag for all AFE channels 14064 * 0b011100..AFE Channel 0 conversion complete 14065 * 0b011101..AFE Channel 1 conversion complete 14066 * 0b011110..AFE Channel 2 conversion complete 14067 * 0b011111..AFE Channel 3 conversion complete 14068 * 0b100000..DMA Done Signal 14069 */ 14070 #define XBAR_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL5_SEL11_SHIFT)) & XBAR_SEL5_SEL11_MASK) 14071 /*! @} */ 14072 14073 /*! @name SEL6 - Crossbar Select Register 6 */ 14074 /*! @{ */ 14075 14076 #define XBAR_SEL6_SEL12_MASK (0x3FU) 14077 #define XBAR_SEL6_SEL12_SHIFT (0U) 14078 /*! SEL12 14079 * 0b000000..Logic 1 (VDD) 14080 * 0b000001..Logic 0 (VSS) 14081 * 0b000010..AFE modulator clock output 14082 * 0b000011..AFE modulator data output 14083 * 0b000100..LPTimer Output 14084 * 0b000101..Clock Output 14085 * 0b000110..Quad Timer channel 0 output 14086 * 0b000111..Quad Timer channel 1 output 14087 * 0b001000..Quad Timer channel 2 output 14088 * 0b001001..Quad Timer channel 3 output 14089 * 0b001010..iRTC Clock Output 14090 * 0b001011..CMP0 Output 14091 * 0b001100..CMP1 Output 14092 * 0b001101..iRTC Alarm Output 14093 * 0b001110..UART TX Output (after modulation) 14094 * 0b001111..EWM Output (EWM_OUT) 14095 * 0b010000..PIT Output 14096 * 0b010001..XBAR Input pin 0 14097 * 0b010010..XBAR Input pin 1 14098 * 0b010011..XBAR Input pin 2 14099 * 0b010100..XBAR Input pin 3 14100 * 0b010101..XBAR Input pin 4 14101 * 0b010110..XBAR Input pin 5 14102 * 0b010111..XBAR Input pin 6 14103 * 0b011000..XBAR Input pin 7 14104 * 0b011001..XBAR Input pin 8 14105 * 0b011010..ORed conversion complete flag for all SAR ADC channels 14106 * 0b011011..ORed conversion complete flag for all AFE channels 14107 * 0b011100..AFE Channel 0 conversion complete 14108 * 0b011101..AFE Channel 1 conversion complete 14109 * 0b011110..AFE Channel 2 conversion complete 14110 * 0b011111..AFE Channel 3 conversion complete 14111 * 0b100000..DMA Done Signal 14112 */ 14113 #define XBAR_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL6_SEL12_SHIFT)) & XBAR_SEL6_SEL12_MASK) 14114 14115 #define XBAR_SEL6_SEL13_MASK (0x3F00U) 14116 #define XBAR_SEL6_SEL13_SHIFT (8U) 14117 /*! SEL13 14118 * 0b000000..Logic 1 (VDD) 14119 * 0b000001..Logic 0 (VSS) 14120 * 0b000010..AFE modulator clock output 14121 * 0b000011..AFE modulator data output 14122 * 0b000100..LPTimer Output 14123 * 0b000101..Clock Output 14124 * 0b000110..Quad Timer channel 0 output 14125 * 0b000111..Quad Timer channel 1 output 14126 * 0b001000..Quad Timer channel 2 output 14127 * 0b001001..Quad Timer channel 3 output 14128 * 0b001010..iRTC Clock Output 14129 * 0b001011..CMP0 Output 14130 * 0b001100..CMP1 Output 14131 * 0b001101..iRTC Alarm Output 14132 * 0b001110..UART TX Output (after modulation) 14133 * 0b001111..EWM Output (EWM_OUT) 14134 * 0b010000..PIT Output 14135 * 0b010001..XBAR Input pin 0 14136 * 0b010010..XBAR Input pin 1 14137 * 0b010011..XBAR Input pin 2 14138 * 0b010100..XBAR Input pin 3 14139 * 0b010101..XBAR Input pin 4 14140 * 0b010110..XBAR Input pin 5 14141 * 0b010111..XBAR Input pin 6 14142 * 0b011000..XBAR Input pin 7 14143 * 0b011001..XBAR Input pin 8 14144 * 0b011010..ORed conversion complete flag for all SAR ADC channels 14145 * 0b011011..ORed conversion complete flag for all AFE channels 14146 * 0b011100..AFE Channel 0 conversion complete 14147 * 0b011101..AFE Channel 1 conversion complete 14148 * 0b011110..AFE Channel 2 conversion complete 14149 * 0b011111..AFE Channel 3 conversion complete 14150 * 0b100000..DMA Done Signal 14151 */ 14152 #define XBAR_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL6_SEL13_SHIFT)) & XBAR_SEL6_SEL13_MASK) 14153 /*! @} */ 14154 14155 /*! @name SEL7 - Crossbar Select Register 7 */ 14156 /*! @{ */ 14157 14158 #define XBAR_SEL7_SEL14_MASK (0x3FU) 14159 #define XBAR_SEL7_SEL14_SHIFT (0U) 14160 /*! SEL14 14161 * 0b000000..Logic 1 (VDD) 14162 * 0b000001..Logic 0 (VSS) 14163 * 0b000010..AFE modulator clock output 14164 * 0b000011..AFE modulator data output 14165 * 0b000100..LPTimer Output 14166 * 0b000101..Clock Output 14167 * 0b000110..Quad Timer channel 0 output 14168 * 0b000111..Quad Timer channel 1 output 14169 * 0b001000..Quad Timer channel 2 output 14170 * 0b001001..Quad Timer channel 3 output 14171 * 0b001010..iRTC Clock Output 14172 * 0b001011..CMP0 Output 14173 * 0b001100..CMP1 Output 14174 * 0b001101..iRTC Alarm Output 14175 * 0b001110..UART TX Output (after modulation) 14176 * 0b001111..EWM Output (EWM_OUT) 14177 * 0b010000..PIT Output 14178 * 0b010001..XBAR Input pin 0 14179 * 0b010010..XBAR Input pin 1 14180 * 0b010011..XBAR Input pin 2 14181 * 0b010100..XBAR Input pin 3 14182 * 0b010101..XBAR Input pin 4 14183 * 0b010110..XBAR Input pin 5 14184 * 0b010111..XBAR Input pin 6 14185 * 0b011000..XBAR Input pin 7 14186 * 0b011001..XBAR Input pin 8 14187 * 0b011010..ORed conversion complete flag for all SAR ADC channels 14188 * 0b011011..ORed conversion complete flag for all AFE channels 14189 * 0b011100..AFE Channel 0 conversion complete 14190 * 0b011101..AFE Channel 1 conversion complete 14191 * 0b011110..AFE Channel 2 conversion complete 14192 * 0b011111..AFE Channel 3 conversion complete 14193 * 0b100000..DMA Done Signal 14194 */ 14195 #define XBAR_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL7_SEL14_SHIFT)) & XBAR_SEL7_SEL14_MASK) 14196 14197 #define XBAR_SEL7_SEL15_MASK (0x3F00U) 14198 #define XBAR_SEL7_SEL15_SHIFT (8U) 14199 /*! SEL15 14200 * 0b000000..Logic 1 (VDD) 14201 * 0b000001..Logic 0 (VSS) 14202 * 0b000010..AFE modulator clock output 14203 * 0b000011..AFE modulator data output 14204 * 0b000100..LPTimer Output 14205 * 0b000101..Clock Output 14206 * 0b000110..Quad Timer channel 0 output 14207 * 0b000111..Quad Timer channel 1 output 14208 * 0b001000..Quad Timer channel 2 output 14209 * 0b001001..Quad Timer channel 3 output 14210 * 0b001010..iRTC Clock Output 14211 * 0b001011..CMP0 Output 14212 * 0b001100..CMP1 Output 14213 * 0b001101..iRTC Alarm Output 14214 * 0b001110..UART TX Output (after modulation) 14215 * 0b001111..EWM Output (EWM_OUT) 14216 * 0b010000..PIT Output 14217 * 0b010001..XBAR Input pin 0 14218 * 0b010010..XBAR Input pin 1 14219 * 0b010011..XBAR Input pin 2 14220 * 0b010100..XBAR Input pin 3 14221 * 0b010101..XBAR Input pin 4 14222 * 0b010110..XBAR Input pin 5 14223 * 0b010111..XBAR Input pin 6 14224 * 0b011000..XBAR Input pin 7 14225 * 0b011001..XBAR Input pin 8 14226 * 0b011010..ORed conversion complete flag for all SAR ADC channels 14227 * 0b011011..ORed conversion complete flag for all AFE channels 14228 * 0b011100..AFE Channel 0 conversion complete 14229 * 0b011101..AFE Channel 1 conversion complete 14230 * 0b011110..AFE Channel 2 conversion complete 14231 * 0b011111..AFE Channel 3 conversion complete 14232 * 0b100000..DMA Done Signal 14233 */ 14234 #define XBAR_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL7_SEL15_SHIFT)) & XBAR_SEL7_SEL15_MASK) 14235 /*! @} */ 14236 14237 /*! @name SEL8 - Crossbar Select Register 8 */ 14238 /*! @{ */ 14239 14240 #define XBAR_SEL8_SEL16_MASK (0x3FU) 14241 #define XBAR_SEL8_SEL16_SHIFT (0U) 14242 /*! SEL16 14243 * 0b000000..Logic 1 (VDD) 14244 * 0b000001..Logic 0 (VSS) 14245 * 0b000010..AFE modulator clock output 14246 * 0b000011..AFE modulator data output 14247 * 0b000100..LPTimer Output 14248 * 0b000101..Clock Output 14249 * 0b000110..Quad Timer channel 0 output 14250 * 0b000111..Quad Timer channel 1 output 14251 * 0b001000..Quad Timer channel 2 output 14252 * 0b001001..Quad Timer channel 3 output 14253 * 0b001010..iRTC Clock Output 14254 * 0b001011..CMP0 Output 14255 * 0b001100..CMP1 Output 14256 * 0b001101..iRTC Alarm Output 14257 * 0b001110..UART TX Output (after modulation) 14258 * 0b001111..EWM Output (EWM_OUT) 14259 * 0b010000..PIT Output 14260 * 0b010001..XBAR Input pin 0 14261 * 0b010010..XBAR Input pin 1 14262 * 0b010011..XBAR Input pin 2 14263 * 0b010100..XBAR Input pin 3 14264 * 0b010101..XBAR Input pin 4 14265 * 0b010110..XBAR Input pin 5 14266 * 0b010111..XBAR Input pin 6 14267 * 0b011000..XBAR Input pin 7 14268 * 0b011001..XBAR Input pin 8 14269 * 0b011010..ORed conversion complete flag for all SAR ADC channels 14270 * 0b011011..ORed conversion complete flag for all AFE channels 14271 * 0b011100..AFE Channel 0 conversion complete 14272 * 0b011101..AFE Channel 1 conversion complete 14273 * 0b011110..AFE Channel 2 conversion complete 14274 * 0b011111..AFE Channel 3 conversion complete 14275 * 0b100000..DMA Done Signal 14276 */ 14277 #define XBAR_SEL8_SEL16(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL8_SEL16_SHIFT)) & XBAR_SEL8_SEL16_MASK) 14278 14279 #define XBAR_SEL8_SEL17_MASK (0x3F00U) 14280 #define XBAR_SEL8_SEL17_SHIFT (8U) 14281 /*! SEL17 14282 * 0b000000..Logic 1 (VDD) 14283 * 0b000001..Logic 0 (VSS) 14284 * 0b000010..AFE modulator clock output 14285 * 0b000011..AFE modulator data output 14286 * 0b000100..LPTimer Output 14287 * 0b000101..Clock Output 14288 * 0b000110..Quad Timer channel 0 output 14289 * 0b000111..Quad Timer channel 1 output 14290 * 0b001000..Quad Timer channel 2 output 14291 * 0b001001..Quad Timer channel 3 output 14292 * 0b001010..iRTC Clock Output 14293 * 0b001011..CMP0 Output 14294 * 0b001100..CMP1 Output 14295 * 0b001101..iRTC Alarm Output 14296 * 0b001110..UART TX Output (after modulation) 14297 * 0b001111..EWM Output (EWM_OUT) 14298 * 0b010000..PIT Output 14299 * 0b010001..XBAR Input pin 0 14300 * 0b010010..XBAR Input pin 1 14301 * 0b010011..XBAR Input pin 2 14302 * 0b010100..XBAR Input pin 3 14303 * 0b010101..XBAR Input pin 4 14304 * 0b010110..XBAR Input pin 5 14305 * 0b010111..XBAR Input pin 6 14306 * 0b011000..XBAR Input pin 7 14307 * 0b011001..XBAR Input pin 8 14308 * 0b011010..ORed conversion complete flag for all SAR ADC channels 14309 * 0b011011..ORed conversion complete flag for all AFE channels 14310 * 0b011100..AFE Channel 0 conversion complete 14311 * 0b011101..AFE Channel 1 conversion complete 14312 * 0b011110..AFE Channel 2 conversion complete 14313 * 0b011111..AFE Channel 3 conversion complete 14314 * 0b100000..DMA Done Signal 14315 */ 14316 #define XBAR_SEL8_SEL17(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL8_SEL17_SHIFT)) & XBAR_SEL8_SEL17_MASK) 14317 /*! @} */ 14318 14319 /*! @name SEL9 - Crossbar Select Register 9 */ 14320 /*! @{ */ 14321 14322 #define XBAR_SEL9_SEL18_MASK (0x3FU) 14323 #define XBAR_SEL9_SEL18_SHIFT (0U) 14324 /*! SEL18 14325 * 0b000000..Logic 1 (VDD) 14326 * 0b000001..Logic 0 (VSS) 14327 * 0b000010..AFE modulator clock output 14328 * 0b000011..AFE modulator data output 14329 * 0b000100..LPTimer Output 14330 * 0b000101..Clock Output 14331 * 0b000110..Quad Timer channel 0 output 14332 * 0b000111..Quad Timer channel 1 output 14333 * 0b001000..Quad Timer channel 2 output 14334 * 0b001001..Quad Timer channel 3 output 14335 * 0b001010..iRTC Clock Output 14336 * 0b001011..CMP0 Output 14337 * 0b001100..CMP1 Output 14338 * 0b001101..iRTC Alarm Output 14339 * 0b001110..UART TX Output (after modulation) 14340 * 0b001111..EWM Output (EWM_OUT) 14341 * 0b010000..PIT Output 14342 * 0b010001..XBAR Input pin 0 14343 * 0b010010..XBAR Input pin 1 14344 * 0b010011..XBAR Input pin 2 14345 * 0b010100..XBAR Input pin 3 14346 * 0b010101..XBAR Input pin 4 14347 * 0b010110..XBAR Input pin 5 14348 * 0b010111..XBAR Input pin 6 14349 * 0b011000..XBAR Input pin 7 14350 * 0b011001..XBAR Input pin 8 14351 * 0b011010..ORed conversion complete flag for all SAR ADC channels 14352 * 0b011011..ORed conversion complete flag for all AFE channels 14353 * 0b011100..AFE Channel 0 conversion complete 14354 * 0b011101..AFE Channel 1 conversion complete 14355 * 0b011110..AFE Channel 2 conversion complete 14356 * 0b011111..AFE Channel 3 conversion complete 14357 * 0b100000..DMA Done Signal 14358 */ 14359 #define XBAR_SEL9_SEL18(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL9_SEL18_SHIFT)) & XBAR_SEL9_SEL18_MASK) 14360 14361 #define XBAR_SEL9_SEL19_MASK (0x3F00U) 14362 #define XBAR_SEL9_SEL19_SHIFT (8U) 14363 /*! SEL19 14364 * 0b000000..Logic 1 (VDD) 14365 * 0b000001..Logic 0 (VSS) 14366 * 0b000010..AFE modulator clock output 14367 * 0b000011..AFE modulator data output 14368 * 0b000100..LPTimer Output 14369 * 0b000101..Clock Output 14370 * 0b000110..Quad Timer channel 0 output 14371 * 0b000111..Quad Timer channel 1 output 14372 * 0b001000..Quad Timer channel 2 output 14373 * 0b001001..Quad Timer channel 3 output 14374 * 0b001010..iRTC Clock Output 14375 * 0b001011..CMP0 Output 14376 * 0b001100..CMP1 Output 14377 * 0b001101..iRTC Alarm Output 14378 * 0b001110..UART TX Output (after modulation) 14379 * 0b001111..EWM Output (EWM_OUT) 14380 * 0b010000..PIT Output 14381 * 0b010001..XBAR Input pin 0 14382 * 0b010010..XBAR Input pin 1 14383 * 0b010011..XBAR Input pin 2 14384 * 0b010100..XBAR Input pin 3 14385 * 0b010101..XBAR Input pin 4 14386 * 0b010110..XBAR Input pin 5 14387 * 0b010111..XBAR Input pin 6 14388 * 0b011000..XBAR Input pin 7 14389 * 0b011001..XBAR Input pin 8 14390 * 0b011010..ORed conversion complete flag for all SAR ADC channels 14391 * 0b011011..ORed conversion complete flag for all AFE channels 14392 * 0b011100..AFE Channel 0 conversion complete 14393 * 0b011101..AFE Channel 1 conversion complete 14394 * 0b011110..AFE Channel 2 conversion complete 14395 * 0b011111..AFE Channel 3 conversion complete 14396 * 0b100000..DMA Done Signal 14397 */ 14398 #define XBAR_SEL9_SEL19(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL9_SEL19_SHIFT)) & XBAR_SEL9_SEL19_MASK) 14399 /*! @} */ 14400 14401 /*! @name SEL10 - Crossbar Select Register 10 */ 14402 /*! @{ */ 14403 14404 #define XBAR_SEL10_SEL20_MASK (0x3FU) 14405 #define XBAR_SEL10_SEL20_SHIFT (0U) 14406 /*! SEL20 14407 * 0b000000..Logic 1 (VDD) 14408 * 0b000001..Logic 0 (VSS) 14409 * 0b000010..AFE modulator clock output 14410 * 0b000011..AFE modulator data output 14411 * 0b000100..LPTimer Output 14412 * 0b000101..Clock Output 14413 * 0b000110..Quad Timer channel 0 output 14414 * 0b000111..Quad Timer channel 1 output 14415 * 0b001000..Quad Timer channel 2 output 14416 * 0b001001..Quad Timer channel 3 output 14417 * 0b001010..iRTC Clock Output 14418 * 0b001011..CMP0 Output 14419 * 0b001100..CMP1 Output 14420 * 0b001101..iRTC Alarm Output 14421 * 0b001110..UART TX Output (after modulation) 14422 * 0b001111..EWM Output (EWM_OUT) 14423 * 0b010000..PIT Output 14424 * 0b010001..XBAR Input pin 0 14425 * 0b010010..XBAR Input pin 1 14426 * 0b010011..XBAR Input pin 2 14427 * 0b010100..XBAR Input pin 3 14428 * 0b010101..XBAR Input pin 4 14429 * 0b010110..XBAR Input pin 5 14430 * 0b010111..XBAR Input pin 6 14431 * 0b011000..XBAR Input pin 7 14432 * 0b011001..XBAR Input pin 8 14433 * 0b011010..ORed conversion complete flag for all SAR ADC channels 14434 * 0b011011..ORed conversion complete flag for all AFE channels 14435 * 0b011100..AFE Channel 0 conversion complete 14436 * 0b011101..AFE Channel 1 conversion complete 14437 * 0b011110..AFE Channel 2 conversion complete 14438 * 0b011111..AFE Channel 3 conversion complete 14439 * 0b100000..DMA Done Signal 14440 */ 14441 #define XBAR_SEL10_SEL20(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL10_SEL20_SHIFT)) & XBAR_SEL10_SEL20_MASK) 14442 14443 #define XBAR_SEL10_SEL21_MASK (0x3F00U) 14444 #define XBAR_SEL10_SEL21_SHIFT (8U) 14445 /*! SEL21 14446 * 0b000000..Logic 1 (VDD) 14447 * 0b000001..Logic 0 (VSS) 14448 * 0b000010..AFE modulator clock output 14449 * 0b000011..AFE modulator data output 14450 * 0b000100..LPTimer Output 14451 * 0b000101..Clock Output 14452 * 0b000110..Quad Timer channel 0 output 14453 * 0b000111..Quad Timer channel 1 output 14454 * 0b001000..Quad Timer channel 2 output 14455 * 0b001001..Quad Timer channel 3 output 14456 * 0b001010..iRTC Clock Output 14457 * 0b001011..CMP0 Output 14458 * 0b001100..CMP1 Output 14459 * 0b001101..iRTC Alarm Output 14460 * 0b001110..UART TX Output (after modulation) 14461 * 0b001111..EWM Output (EWM_OUT) 14462 * 0b010000..PIT Output 14463 * 0b010001..XBAR Input pin 0 14464 * 0b010010..XBAR Input pin 1 14465 * 0b010011..XBAR Input pin 2 14466 * 0b010100..XBAR Input pin 3 14467 * 0b010101..XBAR Input pin 4 14468 * 0b010110..XBAR Input pin 5 14469 * 0b010111..XBAR Input pin 6 14470 * 0b011000..XBAR Input pin 7 14471 * 0b011001..XBAR Input pin 8 14472 * 0b011010..ORed conversion complete flag for all SAR ADC channels 14473 * 0b011011..ORed conversion complete flag for all AFE channels 14474 * 0b011100..AFE Channel 0 conversion complete 14475 * 0b011101..AFE Channel 1 conversion complete 14476 * 0b011110..AFE Channel 2 conversion complete 14477 * 0b011111..AFE Channel 3 conversion complete 14478 * 0b100000..DMA Done Signal 14479 */ 14480 #define XBAR_SEL10_SEL21(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL10_SEL21_SHIFT)) & XBAR_SEL10_SEL21_MASK) 14481 /*! @} */ 14482 14483 /*! @name SEL11 - Crossbar Select Register 11 */ 14484 /*! @{ */ 14485 14486 #define XBAR_SEL11_SEL22_MASK (0x3FU) 14487 #define XBAR_SEL11_SEL22_SHIFT (0U) 14488 /*! SEL22 14489 * 0b000000..Logic 1 (VDD) 14490 * 0b000001..Logic 0 (VSS) 14491 * 0b000010..AFE modulator clock output 14492 * 0b000011..AFE modulator data output 14493 * 0b000100..LPTimer Output 14494 * 0b000101..Clock Output 14495 * 0b000110..Quad Timer channel 0 output 14496 * 0b000111..Quad Timer channel 1 output 14497 * 0b001000..Quad Timer channel 2 output 14498 * 0b001001..Quad Timer channel 3 output 14499 * 0b001010..iRTC Clock Output 14500 * 0b001011..CMP0 Output 14501 * 0b001100..CMP1 Output 14502 * 0b001101..iRTC Alarm Output 14503 * 0b001110..UART TX Output (after modulation) 14504 * 0b001111..EWM Output (EWM_OUT) 14505 * 0b010000..PIT Output 14506 * 0b010001..XBAR Input pin 0 14507 * 0b010010..XBAR Input pin 1 14508 * 0b010011..XBAR Input pin 2 14509 * 0b010100..XBAR Input pin 3 14510 * 0b010101..XBAR Input pin 4 14511 * 0b010110..XBAR Input pin 5 14512 * 0b010111..XBAR Input pin 6 14513 * 0b011000..XBAR Input pin 7 14514 * 0b011001..XBAR Input pin 8 14515 * 0b011010..ORed conversion complete flag for all SAR ADC channels 14516 * 0b011011..ORed conversion complete flag for all AFE channels 14517 * 0b011100..AFE Channel 0 conversion complete 14518 * 0b011101..AFE Channel 1 conversion complete 14519 * 0b011110..AFE Channel 2 conversion complete 14520 * 0b011111..AFE Channel 3 conversion complete 14521 * 0b100000..DMA Done Signal 14522 */ 14523 #define XBAR_SEL11_SEL22(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL11_SEL22_SHIFT)) & XBAR_SEL11_SEL22_MASK) 14524 14525 #define XBAR_SEL11_SEL23_MASK (0x3F00U) 14526 #define XBAR_SEL11_SEL23_SHIFT (8U) 14527 /*! SEL23 14528 * 0b000000..Logic 1 (VDD) 14529 * 0b000001..Logic 0 (VSS) 14530 * 0b000010..AFE modulator clock output 14531 * 0b000011..AFE modulator data output 14532 * 0b000100..LPTimer Output 14533 * 0b000101..Clock Output 14534 * 0b000110..Quad Timer channel 0 output 14535 * 0b000111..Quad Timer channel 1 output 14536 * 0b001000..Quad Timer channel 2 output 14537 * 0b001001..Quad Timer channel 3 output 14538 * 0b001010..iRTC Clock Output 14539 * 0b001011..CMP0 Output 14540 * 0b001100..CMP1 Output 14541 * 0b001101..iRTC Alarm Output 14542 * 0b001110..UART TX Output (after modulation) 14543 * 0b001111..EWM Output (EWM_OUT) 14544 * 0b010000..PIT Output 14545 * 0b010001..XBAR Input pin 0 14546 * 0b010010..XBAR Input pin 1 14547 * 0b010011..XBAR Input pin 2 14548 * 0b010100..XBAR Input pin 3 14549 * 0b010101..XBAR Input pin 4 14550 * 0b010110..XBAR Input pin 5 14551 * 0b010111..XBAR Input pin 6 14552 * 0b011000..XBAR Input pin 7 14553 * 0b011001..XBAR Input pin 8 14554 * 0b011010..ORed conversion complete flag for all SAR ADC channels 14555 * 0b011011..ORed conversion complete flag for all AFE channels 14556 * 0b011100..AFE Channel 0 conversion complete 14557 * 0b011101..AFE Channel 1 conversion complete 14558 * 0b011110..AFE Channel 2 conversion complete 14559 * 0b011111..AFE Channel 3 conversion complete 14560 * 0b100000..DMA Done Signal 14561 */ 14562 #define XBAR_SEL11_SEL23(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL11_SEL23_SHIFT)) & XBAR_SEL11_SEL23_MASK) 14563 /*! @} */ 14564 14565 /*! @name SEL12 - Crossbar Select Register 12 */ 14566 /*! @{ */ 14567 14568 #define XBAR_SEL12_SEL24_MASK (0x3FU) 14569 #define XBAR_SEL12_SEL24_SHIFT (0U) 14570 /*! SEL24 14571 * 0b000000..Logic 1 (VDD) 14572 * 0b000001..Logic 0 (VSS) 14573 * 0b000010..AFE modulator clock output 14574 * 0b000011..AFE modulator data output 14575 * 0b000100..LPTimer Output 14576 * 0b000101..Clock Output 14577 * 0b000110..Quad Timer channel 0 output 14578 * 0b000111..Quad Timer channel 1 output 14579 * 0b001000..Quad Timer channel 2 output 14580 * 0b001001..Quad Timer channel 3 output 14581 * 0b001010..iRTC Clock Output 14582 * 0b001011..CMP0 Output 14583 * 0b001100..CMP1 Output 14584 * 0b001101..iRTC Alarm Output 14585 * 0b001110..UART TX Output (after modulation) 14586 * 0b001111..EWM Output (EWM_OUT) 14587 * 0b010000..PIT Output 14588 * 0b010001..XBAR Input pin 0 14589 * 0b010010..XBAR Input pin 1 14590 * 0b010011..XBAR Input pin 2 14591 * 0b010100..XBAR Input pin 3 14592 * 0b010101..XBAR Input pin 4 14593 * 0b010110..XBAR Input pin 5 14594 * 0b010111..XBAR Input pin 6 14595 * 0b011000..XBAR Input pin 7 14596 * 0b011001..XBAR Input pin 8 14597 * 0b011010..ORed conversion complete flag for all SAR ADC channels 14598 * 0b011011..ORed conversion complete flag for all AFE channels 14599 * 0b011100..AFE Channel 0 conversion complete 14600 * 0b011101..AFE Channel 1 conversion complete 14601 * 0b011110..AFE Channel 2 conversion complete 14602 * 0b011111..AFE Channel 3 conversion complete 14603 * 0b100000..DMA Done Signal 14604 */ 14605 #define XBAR_SEL12_SEL24(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL12_SEL24_SHIFT)) & XBAR_SEL12_SEL24_MASK) 14606 14607 #define XBAR_SEL12_SEL25_MASK (0x3F00U) 14608 #define XBAR_SEL12_SEL25_SHIFT (8U) 14609 /*! SEL25 14610 * 0b000000..Logic 1 (VDD) 14611 * 0b000001..Logic 0 (VSS) 14612 * 0b000010..AFE modulator clock output 14613 * 0b000011..AFE modulator data output 14614 * 0b000100..LPTimer Output 14615 * 0b000101..Clock Output 14616 * 0b000110..Quad Timer channel 0 output 14617 * 0b000111..Quad Timer channel 1 output 14618 * 0b001000..Quad Timer channel 2 output 14619 * 0b001001..Quad Timer channel 3 output 14620 * 0b001010..iRTC Clock Output 14621 * 0b001011..CMP0 Output 14622 * 0b001100..CMP1 Output 14623 * 0b001101..iRTC Alarm Output 14624 * 0b001110..UART TX Output (after modulation) 14625 * 0b001111..EWM Output (EWM_OUT) 14626 * 0b010000..PIT Output 14627 * 0b010001..XBAR Input pin 0 14628 * 0b010010..XBAR Input pin 1 14629 * 0b010011..XBAR Input pin 2 14630 * 0b010100..XBAR Input pin 3 14631 * 0b010101..XBAR Input pin 4 14632 * 0b010110..XBAR Input pin 5 14633 * 0b010111..XBAR Input pin 6 14634 * 0b011000..XBAR Input pin 7 14635 * 0b011001..XBAR Input pin 8 14636 * 0b011010..ORed conversion complete flag for all SAR ADC channels 14637 * 0b011011..ORed conversion complete flag for all AFE channels 14638 * 0b011100..AFE Channel 0 conversion complete 14639 * 0b011101..AFE Channel 1 conversion complete 14640 * 0b011110..AFE Channel 2 conversion complete 14641 * 0b011111..AFE Channel 3 conversion complete 14642 * 0b100000..DMA Done Signal 14643 */ 14644 #define XBAR_SEL12_SEL25(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL12_SEL25_SHIFT)) & XBAR_SEL12_SEL25_MASK) 14645 /*! @} */ 14646 14647 /*! @name SEL13 - Crossbar Select Register 13 */ 14648 /*! @{ */ 14649 14650 #define XBAR_SEL13_SEL26_MASK (0x3FU) 14651 #define XBAR_SEL13_SEL26_SHIFT (0U) 14652 /*! SEL26 14653 * 0b000000..Logic 1 (VDD) 14654 * 0b000001..Logic 0 (VSS) 14655 * 0b000010..AFE modulator clock output 14656 * 0b000011..AFE modulator data output 14657 * 0b000100..LPTimer Output 14658 * 0b000101..Clock Output 14659 * 0b000110..Quad Timer channel 0 output 14660 * 0b000111..Quad Timer channel 1 output 14661 * 0b001000..Quad Timer channel 2 output 14662 * 0b001001..Quad Timer channel 3 output 14663 * 0b001010..iRTC Clock Output 14664 * 0b001011..CMP0 Output 14665 * 0b001100..CMP1 Output 14666 * 0b001101..iRTC Alarm Output 14667 * 0b001110..UART TX Output (after modulation) 14668 * 0b001111..EWM Output (EWM_OUT) 14669 * 0b010000..PIT Output 14670 * 0b010001..XBAR Input pin 0 14671 * 0b010010..XBAR Input pin 1 14672 * 0b010011..XBAR Input pin 2 14673 * 0b010100..XBAR Input pin 3 14674 * 0b010101..XBAR Input pin 4 14675 * 0b010110..XBAR Input pin 5 14676 * 0b010111..XBAR Input pin 6 14677 * 0b011000..XBAR Input pin 7 14678 * 0b011001..XBAR Input pin 8 14679 * 0b011010..ORed conversion complete flag for all SAR ADC channels 14680 * 0b011011..ORed conversion complete flag for all AFE channels 14681 * 0b011100..AFE Channel 0 conversion complete 14682 * 0b011101..AFE Channel 1 conversion complete 14683 * 0b011110..AFE Channel 2 conversion complete 14684 * 0b011111..AFE Channel 3 conversion complete 14685 * 0b100000..DMA Done Signal 14686 */ 14687 #define XBAR_SEL13_SEL26(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL13_SEL26_SHIFT)) & XBAR_SEL13_SEL26_MASK) 14688 14689 #define XBAR_SEL13_SEL27_MASK (0x3F00U) 14690 #define XBAR_SEL13_SEL27_SHIFT (8U) 14691 /*! SEL27 14692 * 0b000000..Logic 1 (VDD) 14693 * 0b000001..Logic 0 (VSS) 14694 * 0b000010..AFE modulator clock output 14695 * 0b000011..AFE modulator data output 14696 * 0b000100..LPTimer Output 14697 * 0b000101..Clock Output 14698 * 0b000110..Quad Timer channel 0 output 14699 * 0b000111..Quad Timer channel 1 output 14700 * 0b001000..Quad Timer channel 2 output 14701 * 0b001001..Quad Timer channel 3 output 14702 * 0b001010..iRTC Clock Output 14703 * 0b001011..CMP0 Output 14704 * 0b001100..CMP1 Output 14705 * 0b001101..iRTC Alarm Output 14706 * 0b001110..UART TX Output (after modulation) 14707 * 0b001111..EWM Output (EWM_OUT) 14708 * 0b010000..PIT Output 14709 * 0b010001..XBAR Input pin 0 14710 * 0b010010..XBAR Input pin 1 14711 * 0b010011..XBAR Input pin 2 14712 * 0b010100..XBAR Input pin 3 14713 * 0b010101..XBAR Input pin 4 14714 * 0b010110..XBAR Input pin 5 14715 * 0b010111..XBAR Input pin 6 14716 * 0b011000..XBAR Input pin 7 14717 * 0b011001..XBAR Input pin 8 14718 * 0b011010..ORed conversion complete flag for all SAR ADC channels 14719 * 0b011011..ORed conversion complete flag for all AFE channels 14720 * 0b011100..AFE Channel 0 conversion complete 14721 * 0b011101..AFE Channel 1 conversion complete 14722 * 0b011110..AFE Channel 2 conversion complete 14723 * 0b011111..AFE Channel 3 conversion complete 14724 * 0b100000..DMA Done Signal 14725 */ 14726 #define XBAR_SEL13_SEL27(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL13_SEL27_SHIFT)) & XBAR_SEL13_SEL27_MASK) 14727 /*! @} */ 14728 14729 /*! @name SEL14 - Crossbar Select Register 14 */ 14730 /*! @{ */ 14731 14732 #define XBAR_SEL14_SEL28_MASK (0x3FU) 14733 #define XBAR_SEL14_SEL28_SHIFT (0U) 14734 /*! SEL28 14735 * 0b000000..Logic 1 (VDD) 14736 * 0b000001..Logic 0 (VSS) 14737 * 0b000010..AFE modulator clock output 14738 * 0b000011..AFE modulator data output 14739 * 0b000100..LPTimer Output 14740 * 0b000101..Clock Output 14741 * 0b000110..Quad Timer channel 0 output 14742 * 0b000111..Quad Timer channel 1 output 14743 * 0b001000..Quad Timer channel 2 output 14744 * 0b001001..Quad Timer channel 3 output 14745 * 0b001010..iRTC Clock Output 14746 * 0b001011..CMP0 Output 14747 * 0b001100..CMP1 Output 14748 * 0b001101..iRTC Alarm Output 14749 * 0b001110..UART TX Output (after modulation) 14750 * 0b001111..EWM Output (EWM_OUT) 14751 * 0b010000..PIT Output 14752 * 0b010001..XBAR Input pin 0 14753 * 0b010010..XBAR Input pin 1 14754 * 0b010011..XBAR Input pin 2 14755 * 0b010100..XBAR Input pin 3 14756 * 0b010101..XBAR Input pin 4 14757 * 0b010110..XBAR Input pin 5 14758 * 0b010111..XBAR Input pin 6 14759 * 0b011000..XBAR Input pin 7 14760 * 0b011001..XBAR Input pin 8 14761 * 0b011010..ORed conversion complete flag for all SAR ADC channels 14762 * 0b011011..ORed conversion complete flag for all AFE channels 14763 * 0b011100..AFE Channel 0 conversion complete 14764 * 0b011101..AFE Channel 1 conversion complete 14765 * 0b011110..AFE Channel 2 conversion complete 14766 * 0b011111..AFE Channel 3 conversion complete 14767 * 0b100000..DMA Done Signal 14768 */ 14769 #define XBAR_SEL14_SEL28(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL14_SEL28_SHIFT)) & XBAR_SEL14_SEL28_MASK) 14770 14771 #define XBAR_SEL14_SEL29_MASK (0x3F00U) 14772 #define XBAR_SEL14_SEL29_SHIFT (8U) 14773 /*! SEL29 14774 * 0b000000..Logic 1 (VDD) 14775 * 0b000001..Logic 0 (VSS) 14776 * 0b000010..AFE modulator clock output 14777 * 0b000011..AFE modulator data output 14778 * 0b000100..LPTimer Output 14779 * 0b000101..Clock Output 14780 * 0b000110..Quad Timer channel 0 output 14781 * 0b000111..Quad Timer channel 1 output 14782 * 0b001000..Quad Timer channel 2 output 14783 * 0b001001..Quad Timer channel 3 output 14784 * 0b001010..iRTC Clock Output 14785 * 0b001011..CMP0 Output 14786 * 0b001100..CMP1 Output 14787 * 0b001101..iRTC Alarm Output 14788 * 0b001110..UART TX Output (after modulation) 14789 * 0b001111..EWM Output (EWM_OUT) 14790 * 0b010000..PIT Output 14791 * 0b010001..XBAR Input pin 0 14792 * 0b010010..XBAR Input pin 1 14793 * 0b010011..XBAR Input pin 2 14794 * 0b010100..XBAR Input pin 3 14795 * 0b010101..XBAR Input pin 4 14796 * 0b010110..XBAR Input pin 5 14797 * 0b010111..XBAR Input pin 6 14798 * 0b011000..XBAR Input pin 7 14799 * 0b011001..XBAR Input pin 8 14800 * 0b011010..ORed conversion complete flag for all SAR ADC channels 14801 * 0b011011..ORed conversion complete flag for all AFE channels 14802 * 0b011100..AFE Channel 0 conversion complete 14803 * 0b011101..AFE Channel 1 conversion complete 14804 * 0b011110..AFE Channel 2 conversion complete 14805 * 0b011111..AFE Channel 3 conversion complete 14806 * 0b100000..DMA Done Signal 14807 */ 14808 #define XBAR_SEL14_SEL29(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL14_SEL29_SHIFT)) & XBAR_SEL14_SEL29_MASK) 14809 /*! @} */ 14810 14811 /*! @name SEL15 - Crossbar Select Register 15 */ 14812 /*! @{ */ 14813 14814 #define XBAR_SEL15_SEL30_MASK (0x3FU) 14815 #define XBAR_SEL15_SEL30_SHIFT (0U) 14816 /*! SEL30 14817 * 0b000000..Logic 1 (VDD) 14818 * 0b000001..Logic 0 (VSS) 14819 * 0b000010..AFE modulator clock output 14820 * 0b000011..AFE modulator data output 14821 * 0b000100..LPTimer Output 14822 * 0b000101..Clock Output 14823 * 0b000110..Quad Timer channel 0 output 14824 * 0b000111..Quad Timer channel 1 output 14825 * 0b001000..Quad Timer channel 2 output 14826 * 0b001001..Quad Timer channel 3 output 14827 * 0b001010..iRTC Clock Output 14828 * 0b001011..CMP0 Output 14829 * 0b001100..CMP1 Output 14830 * 0b001101..iRTC Alarm Output 14831 * 0b001110..UART TX Output (after modulation) 14832 * 0b001111..EWM Output (EWM_OUT) 14833 * 0b010000..PIT Output 14834 * 0b010001..XBAR Input pin 0 14835 * 0b010010..XBAR Input pin 1 14836 * 0b010011..XBAR Input pin 2 14837 * 0b010100..XBAR Input pin 3 14838 * 0b010101..XBAR Input pin 4 14839 * 0b010110..XBAR Input pin 5 14840 * 0b010111..XBAR Input pin 6 14841 * 0b011000..XBAR Input pin 7 14842 * 0b011001..XBAR Input pin 8 14843 * 0b011010..ORed conversion complete flag for all SAR ADC channels 14844 * 0b011011..ORed conversion complete flag for all AFE channels 14845 * 0b011100..AFE Channel 0 conversion complete 14846 * 0b011101..AFE Channel 1 conversion complete 14847 * 0b011110..AFE Channel 2 conversion complete 14848 * 0b011111..AFE Channel 3 conversion complete 14849 * 0b100000..DMA Done Signal 14850 */ 14851 #define XBAR_SEL15_SEL30(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL15_SEL30_SHIFT)) & XBAR_SEL15_SEL30_MASK) 14852 14853 #define XBAR_SEL15_SEL31_MASK (0x3F00U) 14854 #define XBAR_SEL15_SEL31_SHIFT (8U) 14855 /*! SEL31 14856 * 0b000000..Logic 1 (VDD) 14857 * 0b000001..Logic 0 (VSS) 14858 * 0b000010..AFE modulator clock output 14859 * 0b000011..AFE modulator data output 14860 * 0b000100..LPTimer Output 14861 * 0b000101..Clock Output 14862 * 0b000110..Quad Timer channel 0 output 14863 * 0b000111..Quad Timer channel 1 output 14864 * 0b001000..Quad Timer channel 2 output 14865 * 0b001001..Quad Timer channel 3 output 14866 * 0b001010..iRTC Clock Output 14867 * 0b001011..CMP0 Output 14868 * 0b001100..CMP1 Output 14869 * 0b001101..iRTC Alarm Output 14870 * 0b001110..UART TX Output (after modulation) 14871 * 0b001111..EWM Output (EWM_OUT) 14872 * 0b010000..PIT Output 14873 * 0b010001..XBAR Input pin 0 14874 * 0b010010..XBAR Input pin 1 14875 * 0b010011..XBAR Input pin 2 14876 * 0b010100..XBAR Input pin 3 14877 * 0b010101..XBAR Input pin 4 14878 * 0b010110..XBAR Input pin 5 14879 * 0b010111..XBAR Input pin 6 14880 * 0b011000..XBAR Input pin 7 14881 * 0b011001..XBAR Input pin 8 14882 * 0b011010..ORed conversion complete flag for all SAR ADC channels 14883 * 0b011011..ORed conversion complete flag for all AFE channels 14884 * 0b011100..AFE Channel 0 conversion complete 14885 * 0b011101..AFE Channel 1 conversion complete 14886 * 0b011110..AFE Channel 2 conversion complete 14887 * 0b011111..AFE Channel 3 conversion complete 14888 * 0b100000..DMA Done Signal 14889 */ 14890 #define XBAR_SEL15_SEL31(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL15_SEL31_SHIFT)) & XBAR_SEL15_SEL31_MASK) 14891 /*! @} */ 14892 14893 /*! @name SEL16 - Crossbar Select Register 16 */ 14894 /*! @{ */ 14895 14896 #define XBAR_SEL16_SEL32_MASK (0x3FU) 14897 #define XBAR_SEL16_SEL32_SHIFT (0U) 14898 /*! SEL32 14899 * 0b000000..Logic 1 (VDD) 14900 * 0b000001..Logic 0 (VSS) 14901 * 0b000010..AFE modulator clock output 14902 * 0b000011..AFE modulator data output 14903 * 0b000100..LPTimer Output 14904 * 0b000101..Clock Output 14905 * 0b000110..Quad Timer channel 0 output 14906 * 0b000111..Quad Timer channel 1 output 14907 * 0b001000..Quad Timer channel 2 output 14908 * 0b001001..Quad Timer channel 3 output 14909 * 0b001010..iRTC Clock Output 14910 * 0b001011..CMP0 Output 14911 * 0b001100..CMP1 Output 14912 * 0b001101..iRTC Alarm Output 14913 * 0b001110..UART TX Output (after modulation) 14914 * 0b001111..EWM Output (EWM_OUT) 14915 * 0b010000..PIT Output 14916 * 0b010001..XBAR Input pin 0 14917 * 0b010010..XBAR Input pin 1 14918 * 0b010011..XBAR Input pin 2 14919 * 0b010100..XBAR Input pin 3 14920 * 0b010101..XBAR Input pin 4 14921 * 0b010110..XBAR Input pin 5 14922 * 0b010111..XBAR Input pin 6 14923 * 0b011000..XBAR Input pin 7 14924 * 0b011001..XBAR Input pin 8 14925 * 0b011010..ORed conversion complete flag for all SAR ADC channels 14926 * 0b011011..ORed conversion complete flag for all AFE channels 14927 * 0b011100..AFE Channel 0 conversion complete 14928 * 0b011101..AFE Channel 1 conversion complete 14929 * 0b011110..AFE Channel 2 conversion complete 14930 * 0b011111..AFE Channel 3 conversion complete 14931 * 0b100000..DMA Done Signal 14932 */ 14933 #define XBAR_SEL16_SEL32(x) (((uint16_t)(((uint16_t)(x)) << XBAR_SEL16_SEL32_SHIFT)) & XBAR_SEL16_SEL32_MASK) 14934 /*! @} */ 14935 14936 /*! @name CTRL0 - Crossbar Control Register 0 */ 14937 /*! @{ */ 14938 14939 #define XBAR_CTRL0_DEN0_MASK (0x1U) 14940 #define XBAR_CTRL0_DEN0_SHIFT (0U) 14941 /*! DEN0 - DMA Enable for XBAR_OUT0 14942 * 0b0..DMA disabled 14943 * 0b1..DMA enabled 14944 */ 14945 #define XBAR_CTRL0_DEN0(x) (((uint16_t)(((uint16_t)(x)) << XBAR_CTRL0_DEN0_SHIFT)) & XBAR_CTRL0_DEN0_MASK) 14946 14947 #define XBAR_CTRL0_IEN0_MASK (0x2U) 14948 #define XBAR_CTRL0_IEN0_SHIFT (1U) 14949 /*! IEN0 - Interrupt Enable for XBAR_OUT0 14950 * 0b0..Interrupt disabled 14951 * 0b1..Interrupt enabled 14952 */ 14953 #define XBAR_CTRL0_IEN0(x) (((uint16_t)(((uint16_t)(x)) << XBAR_CTRL0_IEN0_SHIFT)) & XBAR_CTRL0_IEN0_MASK) 14954 14955 #define XBAR_CTRL0_EDGE0_MASK (0xCU) 14956 #define XBAR_CTRL0_EDGE0_SHIFT (2U) 14957 /*! EDGE0 - Active edge for edge detection on XBAR_OUT0 14958 * 0b00..STS0 never asserts 14959 * 0b01..STS0 asserts on rising edges of XBAR_OUT0 14960 * 0b10..STS0 asserts on falling edges of XBAR_OUT0 14961 * 0b11..STS0 asserts on rising and falling edges of XBAR_OUT0 14962 */ 14963 #define XBAR_CTRL0_EDGE0(x) (((uint16_t)(((uint16_t)(x)) << XBAR_CTRL0_EDGE0_SHIFT)) & XBAR_CTRL0_EDGE0_MASK) 14964 14965 #define XBAR_CTRL0_STS0_MASK (0x10U) 14966 #define XBAR_CTRL0_STS0_SHIFT (4U) 14967 /*! STS0 - Edge detection status for XBAR_OUT0 14968 * 0b0..Active edge not yet detected on XBAR_OUT0 14969 * 0b1..Active edge detected on XBAR_OUT0 14970 */ 14971 #define XBAR_CTRL0_STS0(x) (((uint16_t)(((uint16_t)(x)) << XBAR_CTRL0_STS0_SHIFT)) & XBAR_CTRL0_STS0_MASK) 14972 /*! @} */ 14973 14974 14975 /*! 14976 * @} 14977 */ /* end of group XBAR_Register_Masks */ 14978 14979 14980 /* XBAR - Peripheral instance base addresses */ 14981 /** Peripheral XBAR base address */ 14982 #define XBAR_BASE (0x40055000u) 14983 /** Peripheral XBAR base pointer */ 14984 #define XBAR ((XBAR_Type *)XBAR_BASE) 14985 /** Array initializer of XBAR peripheral base addresses */ 14986 #define XBAR_BASE_ADDRS { XBAR_BASE } 14987 /** Array initializer of XBAR peripheral base pointers */ 14988 #define XBAR_BASE_PTRS { XBAR } 14989 /** Interrupt vectors for the XBAR peripheral type */ 14990 #define XBAR_IRQS { XBAR_IRQn } 14991 14992 /*! 14993 * @} 14994 */ /* end of group XBAR_Peripheral_Access_Layer */ 14995 14996 14997 /* 14998 ** End of section using anonymous unions 14999 */ 15000 15001 #if defined(__ARMCC_VERSION) 15002 #if (__ARMCC_VERSION >= 6010050) 15003 #pragma clang diagnostic pop 15004 #else 15005 #pragma pop 15006 #endif 15007 #elif defined(__CWCC__) 15008 #pragma pop 15009 #elif defined(__GNUC__) 15010 /* leave anonymous unions enabled */ 15011 #elif defined(__IAR_SYSTEMS_ICC__) 15012 #pragma language=default 15013 #else 15014 #error Not supported compiler type 15015 #endif 15016 15017 /*! 15018 * @} 15019 */ /* end of group Peripheral_access_layer */ 15020 15021 15022 /* ---------------------------------------------------------------------------- 15023 -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). 15024 ---------------------------------------------------------------------------- */ 15025 15026 /*! 15027 * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK). 15028 * @{ 15029 */ 15030 15031 #if defined(__ARMCC_VERSION) 15032 #if (__ARMCC_VERSION >= 6010050) 15033 #pragma clang system_header 15034 #endif 15035 #elif defined(__IAR_SYSTEMS_ICC__) 15036 #pragma system_include 15037 #endif 15038 15039 /** 15040 * @brief Mask and left-shift a bit field value for use in a register bit range. 15041 * @param field Name of the register bit field. 15042 * @param value Value of the bit field. 15043 * @return Masked and shifted value. 15044 */ 15045 #define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK)) 15046 /** 15047 * @brief Mask and right-shift a register value to extract a bit field value. 15048 * @param field Name of the register bit field. 15049 * @param value Value of the register. 15050 * @return Masked and shifted bit field value. 15051 */ 15052 #define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT)) 15053 15054 /*! 15055 * @} 15056 */ /* end of group Bit_Field_Generic_Macros */ 15057 15058 15059 /* ---------------------------------------------------------------------------- 15060 -- SDK Compatibility 15061 ---------------------------------------------------------------------------- */ 15062 15063 /*! 15064 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility 15065 * @{ 15066 */ 15067 15068 /* No SDK compatibility issues. */ 15069 15070 /*! 15071 * @} 15072 */ /* end of group SDK_Compatibility_Symbols */ 15073 15074 15075 #endif /* _MKM14ZA5_H_ */ 15076 15077
