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Searched refs:CH_MBSTAT (Results 1 – 6 of 6) sorted by relevance

/hal_nxp-3.6.0/s32/drivers/s32ze/Platform/src/
DMru_Ip_Irq.c386 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
410 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
437 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
461 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
488 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
512 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
539 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
563 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
590 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
614 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
[all …]
/hal_nxp-3.6.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_CANXL_MRU.h80 …__IO uint32_t CH_MBSTAT; /**< Channel (x) Mailbox Status, array offset: 0x… member
DS32Z2_SMU_MRU.h80 …__IO uint32_t CH_MBSTAT; /**< Channel (x) Mailbox Status, array offset: 0x… member
DS32Z2_RTU_MRU.h80 …__IO uint32_t CH_MBSTAT; /**< Channel (x) Mailbox Status, array offset: 0x… member
DS32Z2_CE_MRU.h80 …__IO uint32_t CH_MBSTAT; /**< Channel (x) Mailbox Status, array offset: 0x… member
/hal_nxp-3.6.0/s32/drivers/s32ze/Can_CANEXCEL/src/
DCanEXCEL_Ip.c62 if ((base->CHXCONFIG[0u].CH_MBSTAT & CANXL_MRU_CH_MBSTAT_MBS0_MASK) != 0U) in Canexcel_GetControllerMRU()
71 base->CHXCONFIG[0u].CH_MBSTAT |= CANXL_MRU_CH_MBSTAT_MBS3_MASK; in Canexcel_GetControllerMRU()
999 if ((base->CHXCONFIG[0u].CH_MBSTAT & mask) == mask) in Canexcel_Ip_MruIRQHandler()
1003 base->CHXCONFIG[0u].CH_MBSTAT |= mask; in Canexcel_Ip_MruIRQHandler()