1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2023 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_CE_MRU.h 10 * @version 2.1 11 * @date 2023-07-20 12 * @brief Peripheral Access Layer for S32Z2_CE_MRU 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_CE_MRU_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_CE_MRU_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- CE_MRU Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup CE_MRU_Peripheral_Access_Layer CE_MRU Peripheral Access Layer 68 * @{ 69 */ 70 71 /** CE_MRU - Size of Registers Arrays */ 72 #define CE_MRU_CHXCONFIG_COUNT 4u 73 #define CE_MRU_NOTIFY_COUNT 2u 74 75 /** CE_MRU - Register Layout Typedef */ 76 typedef struct { 77 struct { /* offset: 0x0, array step: 0x10 */ 78 __IO uint32_t CH_CFG0; /**< Channel (x) Configuration 0, array offset: 0x0, array step: 0x10, irregular array, not all indices are valid */ 79 __IO uint32_t CH_CFG1; /**< Channel (x) Configuration 1, array offset: 0x4, array step: 0x10, irregular array, not all indices are valid */ 80 __IO uint32_t CH_MBSTAT; /**< Channel (x) Mailbox Status, array offset: 0x8, array step: 0x10, irregular array, not all indices are valid */ 81 uint8_t RESERVED_0[4]; 82 } CHXCONFIG[CE_MRU_CHXCONFIG_COUNT]; 83 uint8_t RESERVED_0[448]; 84 __I uint32_t NOTIFY[CE_MRU_NOTIFY_COUNT]; /**< Notification 0 Status..Notification 1 Status, array offset: 0x200, array step: 0x4 */ 85 uint8_t RESERVED_1[15864]; 86 __IO uint32_t CH1_MB0; /**< Channel (x) Mailbox (n), offset: 0x4000 */ 87 __IO uint32_t CH1_MB1; /**< Channel (x) Mailbox (n), offset: 0x4004 */ 88 __IO uint32_t CH1_MB2; /**< Channel (x) Mailbox (n), offset: 0x4008 */ 89 __IO uint32_t CH1_MB3; /**< Channel (x) Mailbox (n), offset: 0x400C */ 90 __IO uint32_t CH1_MB4; /**< Channel (x) Mailbox (n), offset: 0x4010, not available in all instances (available on 12 out of 20) */ 91 __IO uint32_t CH1_MB5; /**< Channel (x) Mailbox (n), offset: 0x4014, not available in all instances (available on 12 out of 20) */ 92 __IO uint32_t CH1_MB6; /**< Channel (x) Mailbox (n), offset: 0x4018, not available in all instances (available on 12 out of 20) */ 93 __IO uint32_t CH1_MB7; /**< Channel (x) Mailbox (n), offset: 0x401C, not available in all instances (available on 12 out of 20) */ 94 __IO uint32_t CH1_MB8; /**< Channel (x) Mailbox (n), offset: 0x4020, not available in all instances (available on 12 out of 20) */ 95 __IO uint32_t CH1_MB9; /**< Channel (x) Mailbox (n), offset: 0x4024, not available in all instances (available on 12 out of 20) */ 96 __IO uint32_t CH1_MB10; /**< Channel (x) Mailbox (n), offset: 0x4028, not available in all instances (available on 12 out of 20) */ 97 __IO uint32_t CH1_MB11; /**< Channel (x) Mailbox (n), offset: 0x402C, not available in all instances (available on 12 out of 20) */ 98 __IO uint32_t CH1_MB12; /**< Channel (x) Mailbox (n), offset: 0x4030, not available in all instances (available on 12 out of 20) */ 99 __IO uint32_t CH1_MB13; /**< Channel (x) Mailbox (n), offset: 0x4034, not available in all instances (available on 12 out of 20) */ 100 __IO uint32_t CH1_MB14; /**< Channel (x) Mailbox (n), offset: 0x4038, not available in all instances (available on 12 out of 20) */ 101 __IO uint32_t CH1_MB15; /**< Channel (x) Mailbox (n), offset: 0x403C, not available in all instances (available on 12 out of 20) */ 102 uint8_t RESERVED_2[16320]; 103 __IO uint32_t CH2_MB0; /**< Channel (x) Mailbox (n), offset: 0x8000, not available in all instances (available on 12 out of 20) */ 104 __IO uint32_t CH2_MB1; /**< Channel (x) Mailbox (n), offset: 0x8004, not available in all instances (available on 12 out of 20) */ 105 __IO uint32_t CH2_MB2; /**< Channel (x) Mailbox (n), offset: 0x8008, not available in all instances (available on 12 out of 20) */ 106 __IO uint32_t CH2_MB3; /**< Channel (x) Mailbox (n), offset: 0x800C, not available in all instances (available on 12 out of 20) */ 107 __IO uint32_t CH2_MB4; /**< Channel (x) Mailbox (n), offset: 0x8010, not available in all instances (available on 12 out of 20) */ 108 __IO uint32_t CH2_MB5; /**< Channel (x) Mailbox (n), offset: 0x8014, not available in all instances (available on 12 out of 20) */ 109 __IO uint32_t CH2_MB6; /**< Channel (x) Mailbox (n), offset: 0x8018, not available in all instances (available on 12 out of 20) */ 110 __IO uint32_t CH2_MB7; /**< Channel (x) Mailbox (n), offset: 0x801C, not available in all instances (available on 12 out of 20) */ 111 __IO uint32_t CH2_MB8; /**< Channel (x) Mailbox (n), offset: 0x8020, not available in all instances (available on 12 out of 20) */ 112 __IO uint32_t CH2_MB9; /**< Channel (x) Mailbox (n), offset: 0x8024, not available in all instances (available on 12 out of 20) */ 113 __IO uint32_t CH2_MB10; /**< Channel (x) Mailbox (n), offset: 0x8028, not available in all instances (available on 12 out of 20) */ 114 __IO uint32_t CH2_MB11; /**< Channel (x) Mailbox (n), offset: 0x802C, not available in all instances (available on 12 out of 20) */ 115 __IO uint32_t CH2_MB12; /**< Channel (x) Mailbox (n), offset: 0x8030, not available in all instances (available on 12 out of 20) */ 116 __IO uint32_t CH2_MB13; /**< Channel (x) Mailbox (n), offset: 0x8034, not available in all instances (available on 12 out of 20) */ 117 __IO uint32_t CH2_MB14; /**< Channel (x) Mailbox (n), offset: 0x8038, not available in all instances (available on 12 out of 20) */ 118 __IO uint32_t CH2_MB15; /**< Channel (x) Mailbox (n), offset: 0x803C, not available in all instances (available on 12 out of 20) */ 119 uint8_t RESERVED_3[16320]; 120 __IO uint32_t CH3_MB0; /**< Channel (x) Mailbox (n), offset: 0xC000, not available in all instances (available on 12 out of 20) */ 121 __IO uint32_t CH3_MB1; /**< Channel (x) Mailbox (n), offset: 0xC004, not available in all instances (available on 12 out of 20) */ 122 __IO uint32_t CH3_MB2; /**< Channel (x) Mailbox (n), offset: 0xC008, not available in all instances (available on 12 out of 20) */ 123 __IO uint32_t CH3_MB3; /**< Channel (x) Mailbox (n), offset: 0xC00C, not available in all instances (available on 12 out of 20) */ 124 __IO uint32_t CH3_MB4; /**< Channel (x) Mailbox (n), offset: 0xC010, not available in all instances (available on 12 out of 20) */ 125 __IO uint32_t CH3_MB5; /**< Channel (x) Mailbox (n), offset: 0xC014, not available in all instances (available on 12 out of 20) */ 126 __IO uint32_t CH3_MB6; /**< Channel (x) Mailbox (n), offset: 0xC018, not available in all instances (available on 12 out of 20) */ 127 __IO uint32_t CH3_MB7; /**< Channel (x) Mailbox (n), offset: 0xC01C, not available in all instances (available on 12 out of 20) */ 128 __IO uint32_t CH3_MB8; /**< Channel (x) Mailbox (n), offset: 0xC020, not available in all instances (available on 12 out of 20) */ 129 __IO uint32_t CH3_MB9; /**< Channel (x) Mailbox (n), offset: 0xC024, not available in all instances (available on 12 out of 20) */ 130 __IO uint32_t CH3_MB10; /**< Channel (x) Mailbox (n), offset: 0xC028, not available in all instances (available on 12 out of 20) */ 131 __IO uint32_t CH3_MB11; /**< Channel (x) Mailbox (n), offset: 0xC02C, not available in all instances (available on 12 out of 20) */ 132 __IO uint32_t CH3_MB12; /**< Channel (x) Mailbox (n), offset: 0xC030, not available in all instances (available on 12 out of 20) */ 133 __IO uint32_t CH3_MB13; /**< Channel (x) Mailbox (n), offset: 0xC034, not available in all instances (available on 12 out of 20) */ 134 __IO uint32_t CH3_MB14; /**< Channel (x) Mailbox (n), offset: 0xC038, not available in all instances (available on 12 out of 20) */ 135 __IO uint32_t CH3_MB15; /**< Channel (x) Mailbox (n), offset: 0xC03C, not available in all instances (available on 12 out of 20) */ 136 uint8_t RESERVED_4[16320]; 137 __IO uint32_t CH4_MB0; /**< Channel (x) Mailbox (n), offset: 0x10000, not available in all instances (available on 12 out of 20) */ 138 __IO uint32_t CH4_MB1; /**< Channel (x) Mailbox (n), offset: 0x10004, not available in all instances (available on 12 out of 20) */ 139 __IO uint32_t CH4_MB2; /**< Channel (x) Mailbox (n), offset: 0x10008, not available in all instances (available on 12 out of 20) */ 140 __IO uint32_t CH4_MB3; /**< Channel (x) Mailbox (n), offset: 0x1000C, not available in all instances (available on 12 out of 20) */ 141 __IO uint32_t CH4_MB4; /**< Channel (x) Mailbox (n), offset: 0x10010, not available in all instances (available on 12 out of 20) */ 142 __IO uint32_t CH4_MB5; /**< Channel (x) Mailbox (n), offset: 0x10014, not available in all instances (available on 12 out of 20) */ 143 __IO uint32_t CH4_MB6; /**< Channel (x) Mailbox (n), offset: 0x10018, not available in all instances (available on 12 out of 20) */ 144 __IO uint32_t CH4_MB7; /**< Channel (x) Mailbox (n), offset: 0x1001C, not available in all instances (available on 12 out of 20) */ 145 __IO uint32_t CH4_MB8; /**< Channel (x) Mailbox (n), offset: 0x10020, not available in all instances (available on 12 out of 20) */ 146 __IO uint32_t CH4_MB9; /**< Channel (x) Mailbox (n), offset: 0x10024, not available in all instances (available on 12 out of 20) */ 147 __IO uint32_t CH4_MB10; /**< Channel (x) Mailbox (n), offset: 0x10028, not available in all instances (available on 12 out of 20) */ 148 __IO uint32_t CH4_MB11; /**< Channel (x) Mailbox (n), offset: 0x1002C, not available in all instances (available on 12 out of 20) */ 149 __IO uint32_t CH4_MB12; /**< Channel (x) Mailbox (n), offset: 0x10030, not available in all instances (available on 12 out of 20) */ 150 __IO uint32_t CH4_MB13; /**< Channel (x) Mailbox (n), offset: 0x10034, not available in all instances (available on 12 out of 20) */ 151 __IO uint32_t CH4_MB14; /**< Channel (x) Mailbox (n), offset: 0x10038, not available in all instances (available on 12 out of 20) */ 152 __IO uint32_t CH4_MB15; /**< Channel (x) Mailbox (n), offset: 0x1003C, not available in all instances (available on 12 out of 20) */ 153 } CE_MRU_Type, *CE_MRU_MemMapPtr; 154 155 /** Number of instances of the CE_MRU module. */ 156 #define CE_MRU_INSTANCE_COUNT (20u) 157 158 /* CE_MRU - Peripheral instance base addresses */ 159 /** Peripheral CE_MRU_0 base address */ 160 #define IP_CE_MRU_0_BASE (0x44AEC000u) 161 /** Peripheral CE_MRU_0 base pointer */ 162 #define IP_CE_MRU_0 ((CE_MRU_Type *)IP_CE_MRU_0_BASE) 163 /** Peripheral CE_MRU_1 base address */ 164 #define IP_CE_MRU_1_BASE (0x44B0C000u) 165 /** Peripheral CE_MRU_1 base pointer */ 166 #define IP_CE_MRU_1 ((CE_MRU_Type *)IP_CE_MRU_1_BASE) 167 /** Peripheral CE_MRU_2 base address */ 168 #define IP_CE_MRU_2_BASE (0x44B2C000u) 169 /** Peripheral CE_MRU_2 base pointer */ 170 #define IP_CE_MRU_2 ((CE_MRU_Type *)IP_CE_MRU_2_BASE) 171 /** Peripheral CE_MRU_3 base address */ 172 #define IP_CE_MRU_3_BASE (0x44B4C000u) 173 /** Peripheral CE_MRU_3 base pointer */ 174 #define IP_CE_MRU_3 ((CE_MRU_Type *)IP_CE_MRU_3_BASE) 175 /** Peripheral CE_MRU_4 base address */ 176 #define IP_CE_MRU_4_BASE (0x44B6C000u) 177 /** Peripheral CE_MRU_4 base pointer */ 178 #define IP_CE_MRU_4 ((CE_MRU_Type *)IP_CE_MRU_4_BASE) 179 /** Peripheral CE_MRU_5 base address */ 180 #define IP_CE_MRU_5_BASE (0x44B8C000u) 181 /** Peripheral CE_MRU_5 base pointer */ 182 #define IP_CE_MRU_5 ((CE_MRU_Type *)IP_CE_MRU_5_BASE) 183 /** Peripheral CE_MRU_6 base address */ 184 #define IP_CE_MRU_6_BASE (0x44C0C000u) 185 /** Peripheral CE_MRU_6 base pointer */ 186 #define IP_CE_MRU_6 ((CE_MRU_Type *)IP_CE_MRU_6_BASE) 187 /** Peripheral CE_MRU_7 base address */ 188 #define IP_CE_MRU_7_BASE (0x44C3C000u) 189 /** Peripheral CE_MRU_7 base pointer */ 190 #define IP_CE_MRU_7 ((CE_MRU_Type *)IP_CE_MRU_7_BASE) 191 /** Peripheral CE_MRU_8 base address */ 192 #define IP_CE_MRU_8_BASE (0x44C6C000u) 193 /** Peripheral CE_MRU_8 base pointer */ 194 #define IP_CE_MRU_8 ((CE_MRU_Type *)IP_CE_MRU_8_BASE) 195 /** Peripheral CE_MRU_9 base address */ 196 #define IP_CE_MRU_9_BASE (0x44C9C000u) 197 /** Peripheral CE_MRU_9 base pointer */ 198 #define IP_CE_MRU_9 ((CE_MRU_Type *)IP_CE_MRU_9_BASE) 199 /** Peripheral CE_MRU_10 base address */ 200 #define IP_CE_MRU_10_BASE (0x44CCC000u) 201 /** Peripheral CE_MRU_10 base pointer */ 202 #define IP_CE_MRU_10 ((CE_MRU_Type *)IP_CE_MRU_10_BASE) 203 /** Peripheral CE_MRU_11 base address */ 204 #define IP_CE_MRU_11_BASE (0x44CFC000u) 205 /** Peripheral CE_MRU_11 base pointer */ 206 #define IP_CE_MRU_11 ((CE_MRU_Type *)IP_CE_MRU_11_BASE) 207 /** Peripheral CE_MRU_12 base address */ 208 #define IP_CE_MRU_12_BASE (0x448EC000u) 209 /** Peripheral CE_MRU_12 base pointer */ 210 #define IP_CE_MRU_12 ((CE_MRU_Type *)IP_CE_MRU_12_BASE) 211 /** Peripheral CE_MRU_13 base address */ 212 #define IP_CE_MRU_13_BASE (0x4490C000u) 213 /** Peripheral CE_MRU_13 base pointer */ 214 #define IP_CE_MRU_13 ((CE_MRU_Type *)IP_CE_MRU_13_BASE) 215 /** Peripheral CE_MRU_14 base address */ 216 #define IP_CE_MRU_14_BASE (0x4492C000u) 217 /** Peripheral CE_MRU_14 base pointer */ 218 #define IP_CE_MRU_14 ((CE_MRU_Type *)IP_CE_MRU_14_BASE) 219 /** Peripheral CE_MRU_15 base address */ 220 #define IP_CE_MRU_15_BASE (0x4494C000u) 221 /** Peripheral CE_MRU_15 base pointer */ 222 #define IP_CE_MRU_15 ((CE_MRU_Type *)IP_CE_MRU_15_BASE) 223 /** Peripheral CE_MRU_16 base address */ 224 #define IP_CE_MRU_16_BASE (0x4496C000u) 225 /** Peripheral CE_MRU_16 base pointer */ 226 #define IP_CE_MRU_16 ((CE_MRU_Type *)IP_CE_MRU_16_BASE) 227 /** Peripheral CE_MRU_17 base address */ 228 #define IP_CE_MRU_17_BASE (0x4498C000u) 229 /** Peripheral CE_MRU_17 base pointer */ 230 #define IP_CE_MRU_17 ((CE_MRU_Type *)IP_CE_MRU_17_BASE) 231 /** Peripheral CE_MRU_18 base address */ 232 #define IP_CE_MRU_18_BASE (0x44D2C000u) 233 /** Peripheral CE_MRU_18 base pointer */ 234 #define IP_CE_MRU_18 ((CE_MRU_Type *)IP_CE_MRU_18_BASE) 235 /** Peripheral CE_MRU_19 base address */ 236 #define IP_CE_MRU_19_BASE (0x44D4C000u) 237 /** Peripheral CE_MRU_19 base pointer */ 238 #define IP_CE_MRU_19 ((CE_MRU_Type *)IP_CE_MRU_19_BASE) 239 /** Array initializer of CE_MRU peripheral base addresses */ 240 #define IP_CE_MRU_BASE_ADDRS { IP_CE_MRU_0_BASE, IP_CE_MRU_1_BASE, IP_CE_MRU_2_BASE, IP_CE_MRU_3_BASE, IP_CE_MRU_4_BASE, IP_CE_MRU_5_BASE, IP_CE_MRU_6_BASE, IP_CE_MRU_7_BASE, IP_CE_MRU_8_BASE, IP_CE_MRU_9_BASE, IP_CE_MRU_10_BASE, IP_CE_MRU_11_BASE, IP_CE_MRU_12_BASE, IP_CE_MRU_13_BASE, IP_CE_MRU_14_BASE, IP_CE_MRU_15_BASE, IP_CE_MRU_16_BASE, IP_CE_MRU_17_BASE, IP_CE_MRU_18_BASE, IP_CE_MRU_19_BASE } 241 /** Array initializer of CE_MRU peripheral base pointers */ 242 #define IP_CE_MRU_BASE_PTRS { IP_CE_MRU_0, IP_CE_MRU_1, IP_CE_MRU_2, IP_CE_MRU_3, IP_CE_MRU_4, IP_CE_MRU_5, IP_CE_MRU_6, IP_CE_MRU_7, IP_CE_MRU_8, IP_CE_MRU_9, IP_CE_MRU_10, IP_CE_MRU_11, IP_CE_MRU_12, IP_CE_MRU_13, IP_CE_MRU_14, IP_CE_MRU_15, IP_CE_MRU_16, IP_CE_MRU_17, IP_CE_MRU_18, IP_CE_MRU_19 } 243 244 /* ---------------------------------------------------------------------------- 245 -- CE_MRU Register Masks 246 ---------------------------------------------------------------------------- */ 247 248 /*! 249 * @addtogroup CE_MRU_Register_Masks CE_MRU Register Masks 250 * @{ 251 */ 252 253 /*! @name CH_CFG0 - Channel (x) Configuration 0 */ 254 /*! @{ */ 255 256 #define CE_MRU_CH_CFG0_CHE_MASK (0x1U) 257 #define CE_MRU_CH_CFG0_CHE_SHIFT (0U) 258 #define CE_MRU_CH_CFG0_CHE_WIDTH (1U) 259 #define CE_MRU_CH_CFG0_CHE(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG0_CHE_SHIFT)) & CE_MRU_CH_CFG0_CHE_MASK) 260 261 #define CE_MRU_CH_CFG0_CHR_MASK (0x2U) 262 #define CE_MRU_CH_CFG0_CHR_SHIFT (1U) 263 #define CE_MRU_CH_CFG0_CHR_WIDTH (1U) 264 #define CE_MRU_CH_CFG0_CHR(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG0_CHR_SHIFT)) & CE_MRU_CH_CFG0_CHR_MASK) 265 266 #define CE_MRU_CH_CFG0_IE_MASK (0x4U) 267 #define CE_MRU_CH_CFG0_IE_SHIFT (2U) 268 #define CE_MRU_CH_CFG0_IE_WIDTH (1U) 269 #define CE_MRU_CH_CFG0_IE(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG0_IE_SHIFT)) & CE_MRU_CH_CFG0_IE_MASK) 270 271 #define CE_MRU_CH_CFG0_MBE0_MASK (0x10000U) 272 #define CE_MRU_CH_CFG0_MBE0_SHIFT (16U) 273 #define CE_MRU_CH_CFG0_MBE0_WIDTH (1U) 274 #define CE_MRU_CH_CFG0_MBE0(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG0_MBE0_SHIFT)) & CE_MRU_CH_CFG0_MBE0_MASK) 275 276 #define CE_MRU_CH_CFG0_MBE1_MASK (0x20000U) 277 #define CE_MRU_CH_CFG0_MBE1_SHIFT (17U) 278 #define CE_MRU_CH_CFG0_MBE1_WIDTH (1U) 279 #define CE_MRU_CH_CFG0_MBE1(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG0_MBE1_SHIFT)) & CE_MRU_CH_CFG0_MBE1_MASK) 280 281 #define CE_MRU_CH_CFG0_MBE2_MASK (0x40000U) 282 #define CE_MRU_CH_CFG0_MBE2_SHIFT (18U) 283 #define CE_MRU_CH_CFG0_MBE2_WIDTH (1U) 284 #define CE_MRU_CH_CFG0_MBE2(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG0_MBE2_SHIFT)) & CE_MRU_CH_CFG0_MBE2_MASK) 285 286 #define CE_MRU_CH_CFG0_MBE3_MASK (0x80000U) 287 #define CE_MRU_CH_CFG0_MBE3_SHIFT (19U) 288 #define CE_MRU_CH_CFG0_MBE3_WIDTH (1U) 289 #define CE_MRU_CH_CFG0_MBE3(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG0_MBE3_SHIFT)) & CE_MRU_CH_CFG0_MBE3_MASK) 290 291 #define CE_MRU_CH_CFG0_MBE4_MASK (0x100000U) 292 #define CE_MRU_CH_CFG0_MBE4_SHIFT (20U) 293 #define CE_MRU_CH_CFG0_MBE4_WIDTH (1U) 294 #define CE_MRU_CH_CFG0_MBE4(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG0_MBE4_SHIFT)) & CE_MRU_CH_CFG0_MBE4_MASK) 295 296 #define CE_MRU_CH_CFG0_MBE5_MASK (0x200000U) 297 #define CE_MRU_CH_CFG0_MBE5_SHIFT (21U) 298 #define CE_MRU_CH_CFG0_MBE5_WIDTH (1U) 299 #define CE_MRU_CH_CFG0_MBE5(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG0_MBE5_SHIFT)) & CE_MRU_CH_CFG0_MBE5_MASK) 300 301 #define CE_MRU_CH_CFG0_MBE6_MASK (0x400000U) 302 #define CE_MRU_CH_CFG0_MBE6_SHIFT (22U) 303 #define CE_MRU_CH_CFG0_MBE6_WIDTH (1U) 304 #define CE_MRU_CH_CFG0_MBE6(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG0_MBE6_SHIFT)) & CE_MRU_CH_CFG0_MBE6_MASK) 305 306 #define CE_MRU_CH_CFG0_MBE7_MASK (0x800000U) 307 #define CE_MRU_CH_CFG0_MBE7_SHIFT (23U) 308 #define CE_MRU_CH_CFG0_MBE7_WIDTH (1U) 309 #define CE_MRU_CH_CFG0_MBE7(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG0_MBE7_SHIFT)) & CE_MRU_CH_CFG0_MBE7_MASK) 310 311 #define CE_MRU_CH_CFG0_MBE8_MASK (0x1000000U) 312 #define CE_MRU_CH_CFG0_MBE8_SHIFT (24U) 313 #define CE_MRU_CH_CFG0_MBE8_WIDTH (1U) 314 #define CE_MRU_CH_CFG0_MBE8(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG0_MBE8_SHIFT)) & CE_MRU_CH_CFG0_MBE8_MASK) 315 316 #define CE_MRU_CH_CFG0_MBE9_MASK (0x2000000U) 317 #define CE_MRU_CH_CFG0_MBE9_SHIFT (25U) 318 #define CE_MRU_CH_CFG0_MBE9_WIDTH (1U) 319 #define CE_MRU_CH_CFG0_MBE9(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG0_MBE9_SHIFT)) & CE_MRU_CH_CFG0_MBE9_MASK) 320 321 #define CE_MRU_CH_CFG0_MBE10_MASK (0x4000000U) 322 #define CE_MRU_CH_CFG0_MBE10_SHIFT (26U) 323 #define CE_MRU_CH_CFG0_MBE10_WIDTH (1U) 324 #define CE_MRU_CH_CFG0_MBE10(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG0_MBE10_SHIFT)) & CE_MRU_CH_CFG0_MBE10_MASK) 325 326 #define CE_MRU_CH_CFG0_MBE11_MASK (0x8000000U) 327 #define CE_MRU_CH_CFG0_MBE11_SHIFT (27U) 328 #define CE_MRU_CH_CFG0_MBE11_WIDTH (1U) 329 #define CE_MRU_CH_CFG0_MBE11(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG0_MBE11_SHIFT)) & CE_MRU_CH_CFG0_MBE11_MASK) 330 331 #define CE_MRU_CH_CFG0_MBE12_MASK (0x10000000U) 332 #define CE_MRU_CH_CFG0_MBE12_SHIFT (28U) 333 #define CE_MRU_CH_CFG0_MBE12_WIDTH (1U) 334 #define CE_MRU_CH_CFG0_MBE12(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG0_MBE12_SHIFT)) & CE_MRU_CH_CFG0_MBE12_MASK) 335 336 #define CE_MRU_CH_CFG0_MBE13_MASK (0x20000000U) 337 #define CE_MRU_CH_CFG0_MBE13_SHIFT (29U) 338 #define CE_MRU_CH_CFG0_MBE13_WIDTH (1U) 339 #define CE_MRU_CH_CFG0_MBE13(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG0_MBE13_SHIFT)) & CE_MRU_CH_CFG0_MBE13_MASK) 340 341 #define CE_MRU_CH_CFG0_MBE14_MASK (0x40000000U) 342 #define CE_MRU_CH_CFG0_MBE14_SHIFT (30U) 343 #define CE_MRU_CH_CFG0_MBE14_WIDTH (1U) 344 #define CE_MRU_CH_CFG0_MBE14(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG0_MBE14_SHIFT)) & CE_MRU_CH_CFG0_MBE14_MASK) 345 346 #define CE_MRU_CH_CFG0_MBE15_MASK (0x80000000U) 347 #define CE_MRU_CH_CFG0_MBE15_SHIFT (31U) 348 #define CE_MRU_CH_CFG0_MBE15_WIDTH (1U) 349 #define CE_MRU_CH_CFG0_MBE15(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG0_MBE15_SHIFT)) & CE_MRU_CH_CFG0_MBE15_MASK) 350 /*! @} */ 351 352 /*! @name CH_CFG1 - Channel (x) Configuration 1 */ 353 /*! @{ */ 354 355 #define CE_MRU_CH_CFG1_MBIC0_MASK (0x10000U) 356 #define CE_MRU_CH_CFG1_MBIC0_SHIFT (16U) 357 #define CE_MRU_CH_CFG1_MBIC0_WIDTH (1U) 358 #define CE_MRU_CH_CFG1_MBIC0(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG1_MBIC0_SHIFT)) & CE_MRU_CH_CFG1_MBIC0_MASK) 359 360 #define CE_MRU_CH_CFG1_MBIC1_MASK (0x20000U) 361 #define CE_MRU_CH_CFG1_MBIC1_SHIFT (17U) 362 #define CE_MRU_CH_CFG1_MBIC1_WIDTH (1U) 363 #define CE_MRU_CH_CFG1_MBIC1(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG1_MBIC1_SHIFT)) & CE_MRU_CH_CFG1_MBIC1_MASK) 364 365 #define CE_MRU_CH_CFG1_MBIC2_MASK (0x40000U) 366 #define CE_MRU_CH_CFG1_MBIC2_SHIFT (18U) 367 #define CE_MRU_CH_CFG1_MBIC2_WIDTH (1U) 368 #define CE_MRU_CH_CFG1_MBIC2(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG1_MBIC2_SHIFT)) & CE_MRU_CH_CFG1_MBIC2_MASK) 369 370 #define CE_MRU_CH_CFG1_MBIC3_MASK (0x80000U) 371 #define CE_MRU_CH_CFG1_MBIC3_SHIFT (19U) 372 #define CE_MRU_CH_CFG1_MBIC3_WIDTH (1U) 373 #define CE_MRU_CH_CFG1_MBIC3(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG1_MBIC3_SHIFT)) & CE_MRU_CH_CFG1_MBIC3_MASK) 374 375 #define CE_MRU_CH_CFG1_MBIC4_MASK (0x100000U) 376 #define CE_MRU_CH_CFG1_MBIC4_SHIFT (20U) 377 #define CE_MRU_CH_CFG1_MBIC4_WIDTH (1U) 378 #define CE_MRU_CH_CFG1_MBIC4(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG1_MBIC4_SHIFT)) & CE_MRU_CH_CFG1_MBIC4_MASK) 379 380 #define CE_MRU_CH_CFG1_MBIC5_MASK (0x200000U) 381 #define CE_MRU_CH_CFG1_MBIC5_SHIFT (21U) 382 #define CE_MRU_CH_CFG1_MBIC5_WIDTH (1U) 383 #define CE_MRU_CH_CFG1_MBIC5(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG1_MBIC5_SHIFT)) & CE_MRU_CH_CFG1_MBIC5_MASK) 384 385 #define CE_MRU_CH_CFG1_MBIC6_MASK (0x400000U) 386 #define CE_MRU_CH_CFG1_MBIC6_SHIFT (22U) 387 #define CE_MRU_CH_CFG1_MBIC6_WIDTH (1U) 388 #define CE_MRU_CH_CFG1_MBIC6(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG1_MBIC6_SHIFT)) & CE_MRU_CH_CFG1_MBIC6_MASK) 389 390 #define CE_MRU_CH_CFG1_MBIC7_MASK (0x800000U) 391 #define CE_MRU_CH_CFG1_MBIC7_SHIFT (23U) 392 #define CE_MRU_CH_CFG1_MBIC7_WIDTH (1U) 393 #define CE_MRU_CH_CFG1_MBIC7(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG1_MBIC7_SHIFT)) & CE_MRU_CH_CFG1_MBIC7_MASK) 394 395 #define CE_MRU_CH_CFG1_MBIC8_MASK (0x1000000U) 396 #define CE_MRU_CH_CFG1_MBIC8_SHIFT (24U) 397 #define CE_MRU_CH_CFG1_MBIC8_WIDTH (1U) 398 #define CE_MRU_CH_CFG1_MBIC8(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG1_MBIC8_SHIFT)) & CE_MRU_CH_CFG1_MBIC8_MASK) 399 400 #define CE_MRU_CH_CFG1_MBIC9_MASK (0x2000000U) 401 #define CE_MRU_CH_CFG1_MBIC9_SHIFT (25U) 402 #define CE_MRU_CH_CFG1_MBIC9_WIDTH (1U) 403 #define CE_MRU_CH_CFG1_MBIC9(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG1_MBIC9_SHIFT)) & CE_MRU_CH_CFG1_MBIC9_MASK) 404 405 #define CE_MRU_CH_CFG1_MBIC10_MASK (0x4000000U) 406 #define CE_MRU_CH_CFG1_MBIC10_SHIFT (26U) 407 #define CE_MRU_CH_CFG1_MBIC10_WIDTH (1U) 408 #define CE_MRU_CH_CFG1_MBIC10(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG1_MBIC10_SHIFT)) & CE_MRU_CH_CFG1_MBIC10_MASK) 409 410 #define CE_MRU_CH_CFG1_MBIC11_MASK (0x8000000U) 411 #define CE_MRU_CH_CFG1_MBIC11_SHIFT (27U) 412 #define CE_MRU_CH_CFG1_MBIC11_WIDTH (1U) 413 #define CE_MRU_CH_CFG1_MBIC11(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG1_MBIC11_SHIFT)) & CE_MRU_CH_CFG1_MBIC11_MASK) 414 415 #define CE_MRU_CH_CFG1_MBIC12_MASK (0x10000000U) 416 #define CE_MRU_CH_CFG1_MBIC12_SHIFT (28U) 417 #define CE_MRU_CH_CFG1_MBIC12_WIDTH (1U) 418 #define CE_MRU_CH_CFG1_MBIC12(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG1_MBIC12_SHIFT)) & CE_MRU_CH_CFG1_MBIC12_MASK) 419 420 #define CE_MRU_CH_CFG1_MBIC13_MASK (0x20000000U) 421 #define CE_MRU_CH_CFG1_MBIC13_SHIFT (29U) 422 #define CE_MRU_CH_CFG1_MBIC13_WIDTH (1U) 423 #define CE_MRU_CH_CFG1_MBIC13(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG1_MBIC13_SHIFT)) & CE_MRU_CH_CFG1_MBIC13_MASK) 424 425 #define CE_MRU_CH_CFG1_MBIC14_MASK (0x40000000U) 426 #define CE_MRU_CH_CFG1_MBIC14_SHIFT (30U) 427 #define CE_MRU_CH_CFG1_MBIC14_WIDTH (1U) 428 #define CE_MRU_CH_CFG1_MBIC14(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG1_MBIC14_SHIFT)) & CE_MRU_CH_CFG1_MBIC14_MASK) 429 430 #define CE_MRU_CH_CFG1_MBIC15_MASK (0x80000000U) 431 #define CE_MRU_CH_CFG1_MBIC15_SHIFT (31U) 432 #define CE_MRU_CH_CFG1_MBIC15_WIDTH (1U) 433 #define CE_MRU_CH_CFG1_MBIC15(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_CFG1_MBIC15_SHIFT)) & CE_MRU_CH_CFG1_MBIC15_MASK) 434 /*! @} */ 435 436 /*! @name CH_MBSTAT - Channel (x) Mailbox Status */ 437 /*! @{ */ 438 439 #define CE_MRU_CH_MBSTAT_MBS0_MASK (0x10000U) 440 #define CE_MRU_CH_MBSTAT_MBS0_SHIFT (16U) 441 #define CE_MRU_CH_MBSTAT_MBS0_WIDTH (1U) 442 #define CE_MRU_CH_MBSTAT_MBS0(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_MBSTAT_MBS0_SHIFT)) & CE_MRU_CH_MBSTAT_MBS0_MASK) 443 444 #define CE_MRU_CH_MBSTAT_MBS1_MASK (0x20000U) 445 #define CE_MRU_CH_MBSTAT_MBS1_SHIFT (17U) 446 #define CE_MRU_CH_MBSTAT_MBS1_WIDTH (1U) 447 #define CE_MRU_CH_MBSTAT_MBS1(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_MBSTAT_MBS1_SHIFT)) & CE_MRU_CH_MBSTAT_MBS1_MASK) 448 449 #define CE_MRU_CH_MBSTAT_MBS2_MASK (0x40000U) 450 #define CE_MRU_CH_MBSTAT_MBS2_SHIFT (18U) 451 #define CE_MRU_CH_MBSTAT_MBS2_WIDTH (1U) 452 #define CE_MRU_CH_MBSTAT_MBS2(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_MBSTAT_MBS2_SHIFT)) & CE_MRU_CH_MBSTAT_MBS2_MASK) 453 454 #define CE_MRU_CH_MBSTAT_MBS3_MASK (0x80000U) 455 #define CE_MRU_CH_MBSTAT_MBS3_SHIFT (19U) 456 #define CE_MRU_CH_MBSTAT_MBS3_WIDTH (1U) 457 #define CE_MRU_CH_MBSTAT_MBS3(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_MBSTAT_MBS3_SHIFT)) & CE_MRU_CH_MBSTAT_MBS3_MASK) 458 459 #define CE_MRU_CH_MBSTAT_MBS4_MASK (0x100000U) 460 #define CE_MRU_CH_MBSTAT_MBS4_SHIFT (20U) 461 #define CE_MRU_CH_MBSTAT_MBS4_WIDTH (1U) 462 #define CE_MRU_CH_MBSTAT_MBS4(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_MBSTAT_MBS4_SHIFT)) & CE_MRU_CH_MBSTAT_MBS4_MASK) 463 464 #define CE_MRU_CH_MBSTAT_MBS5_MASK (0x200000U) 465 #define CE_MRU_CH_MBSTAT_MBS5_SHIFT (21U) 466 #define CE_MRU_CH_MBSTAT_MBS5_WIDTH (1U) 467 #define CE_MRU_CH_MBSTAT_MBS5(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_MBSTAT_MBS5_SHIFT)) & CE_MRU_CH_MBSTAT_MBS5_MASK) 468 469 #define CE_MRU_CH_MBSTAT_MBS6_MASK (0x400000U) 470 #define CE_MRU_CH_MBSTAT_MBS6_SHIFT (22U) 471 #define CE_MRU_CH_MBSTAT_MBS6_WIDTH (1U) 472 #define CE_MRU_CH_MBSTAT_MBS6(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_MBSTAT_MBS6_SHIFT)) & CE_MRU_CH_MBSTAT_MBS6_MASK) 473 474 #define CE_MRU_CH_MBSTAT_MBS7_MASK (0x800000U) 475 #define CE_MRU_CH_MBSTAT_MBS7_SHIFT (23U) 476 #define CE_MRU_CH_MBSTAT_MBS7_WIDTH (1U) 477 #define CE_MRU_CH_MBSTAT_MBS7(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_MBSTAT_MBS7_SHIFT)) & CE_MRU_CH_MBSTAT_MBS7_MASK) 478 479 #define CE_MRU_CH_MBSTAT_MBS8_MASK (0x1000000U) 480 #define CE_MRU_CH_MBSTAT_MBS8_SHIFT (24U) 481 #define CE_MRU_CH_MBSTAT_MBS8_WIDTH (1U) 482 #define CE_MRU_CH_MBSTAT_MBS8(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_MBSTAT_MBS8_SHIFT)) & CE_MRU_CH_MBSTAT_MBS8_MASK) 483 484 #define CE_MRU_CH_MBSTAT_MBS9_MASK (0x2000000U) 485 #define CE_MRU_CH_MBSTAT_MBS9_SHIFT (25U) 486 #define CE_MRU_CH_MBSTAT_MBS9_WIDTH (1U) 487 #define CE_MRU_CH_MBSTAT_MBS9(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_MBSTAT_MBS9_SHIFT)) & CE_MRU_CH_MBSTAT_MBS9_MASK) 488 489 #define CE_MRU_CH_MBSTAT_MBS10_MASK (0x4000000U) 490 #define CE_MRU_CH_MBSTAT_MBS10_SHIFT (26U) 491 #define CE_MRU_CH_MBSTAT_MBS10_WIDTH (1U) 492 #define CE_MRU_CH_MBSTAT_MBS10(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_MBSTAT_MBS10_SHIFT)) & CE_MRU_CH_MBSTAT_MBS10_MASK) 493 494 #define CE_MRU_CH_MBSTAT_MBS11_MASK (0x8000000U) 495 #define CE_MRU_CH_MBSTAT_MBS11_SHIFT (27U) 496 #define CE_MRU_CH_MBSTAT_MBS11_WIDTH (1U) 497 #define CE_MRU_CH_MBSTAT_MBS11(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_MBSTAT_MBS11_SHIFT)) & CE_MRU_CH_MBSTAT_MBS11_MASK) 498 499 #define CE_MRU_CH_MBSTAT_MBS12_MASK (0x10000000U) 500 #define CE_MRU_CH_MBSTAT_MBS12_SHIFT (28U) 501 #define CE_MRU_CH_MBSTAT_MBS12_WIDTH (1U) 502 #define CE_MRU_CH_MBSTAT_MBS12(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_MBSTAT_MBS12_SHIFT)) & CE_MRU_CH_MBSTAT_MBS12_MASK) 503 504 #define CE_MRU_CH_MBSTAT_MBS13_MASK (0x20000000U) 505 #define CE_MRU_CH_MBSTAT_MBS13_SHIFT (29U) 506 #define CE_MRU_CH_MBSTAT_MBS13_WIDTH (1U) 507 #define CE_MRU_CH_MBSTAT_MBS13(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_MBSTAT_MBS13_SHIFT)) & CE_MRU_CH_MBSTAT_MBS13_MASK) 508 509 #define CE_MRU_CH_MBSTAT_MBS14_MASK (0x40000000U) 510 #define CE_MRU_CH_MBSTAT_MBS14_SHIFT (30U) 511 #define CE_MRU_CH_MBSTAT_MBS14_WIDTH (1U) 512 #define CE_MRU_CH_MBSTAT_MBS14(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_MBSTAT_MBS14_SHIFT)) & CE_MRU_CH_MBSTAT_MBS14_MASK) 513 514 #define CE_MRU_CH_MBSTAT_MBS15_MASK (0x80000000U) 515 #define CE_MRU_CH_MBSTAT_MBS15_SHIFT (31U) 516 #define CE_MRU_CH_MBSTAT_MBS15_WIDTH (1U) 517 #define CE_MRU_CH_MBSTAT_MBS15(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH_MBSTAT_MBS15_SHIFT)) & CE_MRU_CH_MBSTAT_MBS15_MASK) 518 /*! @} */ 519 520 /*! @name NOTIFY - Notification 0 Status..Notification 1 Status */ 521 /*! @{ */ 522 523 #define CE_MRU_NOTIFY_CH1_IS0_MASK (0x1U) 524 #define CE_MRU_NOTIFY_CH1_IS0_SHIFT (0U) 525 #define CE_MRU_NOTIFY_CH1_IS0_WIDTH (1U) 526 #define CE_MRU_NOTIFY_CH1_IS0(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_NOTIFY_CH1_IS0_SHIFT)) & CE_MRU_NOTIFY_CH1_IS0_MASK) 527 528 #define CE_MRU_NOTIFY_CH1_IS1_MASK (0x1U) 529 #define CE_MRU_NOTIFY_CH1_IS1_SHIFT (0U) 530 #define CE_MRU_NOTIFY_CH1_IS1_WIDTH (1U) 531 #define CE_MRU_NOTIFY_CH1_IS1(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_NOTIFY_CH1_IS1_SHIFT)) & CE_MRU_NOTIFY_CH1_IS1_MASK) 532 533 #define CE_MRU_NOTIFY_CH2_IS0_MASK (0x2U) 534 #define CE_MRU_NOTIFY_CH2_IS0_SHIFT (1U) 535 #define CE_MRU_NOTIFY_CH2_IS0_WIDTH (1U) 536 #define CE_MRU_NOTIFY_CH2_IS0(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_NOTIFY_CH2_IS0_SHIFT)) & CE_MRU_NOTIFY_CH2_IS0_MASK) 537 538 #define CE_MRU_NOTIFY_CH2_IS1_MASK (0x2U) 539 #define CE_MRU_NOTIFY_CH2_IS1_SHIFT (1U) 540 #define CE_MRU_NOTIFY_CH2_IS1_WIDTH (1U) 541 #define CE_MRU_NOTIFY_CH2_IS1(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_NOTIFY_CH2_IS1_SHIFT)) & CE_MRU_NOTIFY_CH2_IS1_MASK) 542 543 #define CE_MRU_NOTIFY_CH3_IS0_MASK (0x4U) 544 #define CE_MRU_NOTIFY_CH3_IS0_SHIFT (2U) 545 #define CE_MRU_NOTIFY_CH3_IS0_WIDTH (1U) 546 #define CE_MRU_NOTIFY_CH3_IS0(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_NOTIFY_CH3_IS0_SHIFT)) & CE_MRU_NOTIFY_CH3_IS0_MASK) 547 548 #define CE_MRU_NOTIFY_CH3_IS1_MASK (0x4U) 549 #define CE_MRU_NOTIFY_CH3_IS1_SHIFT (2U) 550 #define CE_MRU_NOTIFY_CH3_IS1_WIDTH (1U) 551 #define CE_MRU_NOTIFY_CH3_IS1(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_NOTIFY_CH3_IS1_SHIFT)) & CE_MRU_NOTIFY_CH3_IS1_MASK) 552 553 #define CE_MRU_NOTIFY_CH4_IS0_MASK (0x8U) 554 #define CE_MRU_NOTIFY_CH4_IS0_SHIFT (3U) 555 #define CE_MRU_NOTIFY_CH4_IS0_WIDTH (1U) 556 #define CE_MRU_NOTIFY_CH4_IS0(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_NOTIFY_CH4_IS0_SHIFT)) & CE_MRU_NOTIFY_CH4_IS0_MASK) 557 558 #define CE_MRU_NOTIFY_CH4_IS1_MASK (0x8U) 559 #define CE_MRU_NOTIFY_CH4_IS1_SHIFT (3U) 560 #define CE_MRU_NOTIFY_CH4_IS1_WIDTH (1U) 561 #define CE_MRU_NOTIFY_CH4_IS1(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_NOTIFY_CH4_IS1_SHIFT)) & CE_MRU_NOTIFY_CH4_IS1_MASK) 562 /*! @} */ 563 564 /*! @name CH1_MB0 - Channel (x) Mailbox (n) */ 565 /*! @{ */ 566 567 #define CE_MRU_CH1_MB0_MBD_MASK (0xFFFFFFFFU) 568 #define CE_MRU_CH1_MB0_MBD_SHIFT (0U) 569 #define CE_MRU_CH1_MB0_MBD_WIDTH (32U) 570 #define CE_MRU_CH1_MB0_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH1_MB0_MBD_SHIFT)) & CE_MRU_CH1_MB0_MBD_MASK) 571 /*! @} */ 572 573 /*! @name CH1_MB1 - Channel (x) Mailbox (n) */ 574 /*! @{ */ 575 576 #define CE_MRU_CH1_MB1_MBD_MASK (0xFFFFFFFFU) 577 #define CE_MRU_CH1_MB1_MBD_SHIFT (0U) 578 #define CE_MRU_CH1_MB1_MBD_WIDTH (32U) 579 #define CE_MRU_CH1_MB1_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH1_MB1_MBD_SHIFT)) & CE_MRU_CH1_MB1_MBD_MASK) 580 /*! @} */ 581 582 /*! @name CH1_MB2 - Channel (x) Mailbox (n) */ 583 /*! @{ */ 584 585 #define CE_MRU_CH1_MB2_MBD_MASK (0xFFFFFFFFU) 586 #define CE_MRU_CH1_MB2_MBD_SHIFT (0U) 587 #define CE_MRU_CH1_MB2_MBD_WIDTH (32U) 588 #define CE_MRU_CH1_MB2_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH1_MB2_MBD_SHIFT)) & CE_MRU_CH1_MB2_MBD_MASK) 589 /*! @} */ 590 591 /*! @name CH1_MB3 - Channel (x) Mailbox (n) */ 592 /*! @{ */ 593 594 #define CE_MRU_CH1_MB3_MBD_MASK (0xFFFFFFFFU) 595 #define CE_MRU_CH1_MB3_MBD_SHIFT (0U) 596 #define CE_MRU_CH1_MB3_MBD_WIDTH (32U) 597 #define CE_MRU_CH1_MB3_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH1_MB3_MBD_SHIFT)) & CE_MRU_CH1_MB3_MBD_MASK) 598 /*! @} */ 599 600 /*! @name CH1_MB4 - Channel (x) Mailbox (n) */ 601 /*! @{ */ 602 603 #define CE_MRU_CH1_MB4_MBD_MASK (0xFFFFFFFFU) 604 #define CE_MRU_CH1_MB4_MBD_SHIFT (0U) 605 #define CE_MRU_CH1_MB4_MBD_WIDTH (32U) 606 #define CE_MRU_CH1_MB4_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH1_MB4_MBD_SHIFT)) & CE_MRU_CH1_MB4_MBD_MASK) 607 /*! @} */ 608 609 /*! @name CH1_MB5 - Channel (x) Mailbox (n) */ 610 /*! @{ */ 611 612 #define CE_MRU_CH1_MB5_MBD_MASK (0xFFFFFFFFU) 613 #define CE_MRU_CH1_MB5_MBD_SHIFT (0U) 614 #define CE_MRU_CH1_MB5_MBD_WIDTH (32U) 615 #define CE_MRU_CH1_MB5_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH1_MB5_MBD_SHIFT)) & CE_MRU_CH1_MB5_MBD_MASK) 616 /*! @} */ 617 618 /*! @name CH1_MB6 - Channel (x) Mailbox (n) */ 619 /*! @{ */ 620 621 #define CE_MRU_CH1_MB6_MBD_MASK (0xFFFFFFFFU) 622 #define CE_MRU_CH1_MB6_MBD_SHIFT (0U) 623 #define CE_MRU_CH1_MB6_MBD_WIDTH (32U) 624 #define CE_MRU_CH1_MB6_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH1_MB6_MBD_SHIFT)) & CE_MRU_CH1_MB6_MBD_MASK) 625 /*! @} */ 626 627 /*! @name CH1_MB7 - Channel (x) Mailbox (n) */ 628 /*! @{ */ 629 630 #define CE_MRU_CH1_MB7_MBD_MASK (0xFFFFFFFFU) 631 #define CE_MRU_CH1_MB7_MBD_SHIFT (0U) 632 #define CE_MRU_CH1_MB7_MBD_WIDTH (32U) 633 #define CE_MRU_CH1_MB7_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH1_MB7_MBD_SHIFT)) & CE_MRU_CH1_MB7_MBD_MASK) 634 /*! @} */ 635 636 /*! @name CH1_MB8 - Channel (x) Mailbox (n) */ 637 /*! @{ */ 638 639 #define CE_MRU_CH1_MB8_MBD_MASK (0xFFFFFFFFU) 640 #define CE_MRU_CH1_MB8_MBD_SHIFT (0U) 641 #define CE_MRU_CH1_MB8_MBD_WIDTH (32U) 642 #define CE_MRU_CH1_MB8_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH1_MB8_MBD_SHIFT)) & CE_MRU_CH1_MB8_MBD_MASK) 643 /*! @} */ 644 645 /*! @name CH1_MB9 - Channel (x) Mailbox (n) */ 646 /*! @{ */ 647 648 #define CE_MRU_CH1_MB9_MBD_MASK (0xFFFFFFFFU) 649 #define CE_MRU_CH1_MB9_MBD_SHIFT (0U) 650 #define CE_MRU_CH1_MB9_MBD_WIDTH (32U) 651 #define CE_MRU_CH1_MB9_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH1_MB9_MBD_SHIFT)) & CE_MRU_CH1_MB9_MBD_MASK) 652 /*! @} */ 653 654 /*! @name CH1_MB10 - Channel (x) Mailbox (n) */ 655 /*! @{ */ 656 657 #define CE_MRU_CH1_MB10_MBD_MASK (0xFFFFFFFFU) 658 #define CE_MRU_CH1_MB10_MBD_SHIFT (0U) 659 #define CE_MRU_CH1_MB10_MBD_WIDTH (32U) 660 #define CE_MRU_CH1_MB10_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH1_MB10_MBD_SHIFT)) & CE_MRU_CH1_MB10_MBD_MASK) 661 /*! @} */ 662 663 /*! @name CH1_MB11 - Channel (x) Mailbox (n) */ 664 /*! @{ */ 665 666 #define CE_MRU_CH1_MB11_MBD_MASK (0xFFFFFFFFU) 667 #define CE_MRU_CH1_MB11_MBD_SHIFT (0U) 668 #define CE_MRU_CH1_MB11_MBD_WIDTH (32U) 669 #define CE_MRU_CH1_MB11_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH1_MB11_MBD_SHIFT)) & CE_MRU_CH1_MB11_MBD_MASK) 670 /*! @} */ 671 672 /*! @name CH1_MB12 - Channel (x) Mailbox (n) */ 673 /*! @{ */ 674 675 #define CE_MRU_CH1_MB12_MBD_MASK (0xFFFFFFFFU) 676 #define CE_MRU_CH1_MB12_MBD_SHIFT (0U) 677 #define CE_MRU_CH1_MB12_MBD_WIDTH (32U) 678 #define CE_MRU_CH1_MB12_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH1_MB12_MBD_SHIFT)) & CE_MRU_CH1_MB12_MBD_MASK) 679 /*! @} */ 680 681 /*! @name CH1_MB13 - Channel (x) Mailbox (n) */ 682 /*! @{ */ 683 684 #define CE_MRU_CH1_MB13_MBD_MASK (0xFFFFFFFFU) 685 #define CE_MRU_CH1_MB13_MBD_SHIFT (0U) 686 #define CE_MRU_CH1_MB13_MBD_WIDTH (32U) 687 #define CE_MRU_CH1_MB13_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH1_MB13_MBD_SHIFT)) & CE_MRU_CH1_MB13_MBD_MASK) 688 /*! @} */ 689 690 /*! @name CH1_MB14 - Channel (x) Mailbox (n) */ 691 /*! @{ */ 692 693 #define CE_MRU_CH1_MB14_MBD_MASK (0xFFFFFFFFU) 694 #define CE_MRU_CH1_MB14_MBD_SHIFT (0U) 695 #define CE_MRU_CH1_MB14_MBD_WIDTH (32U) 696 #define CE_MRU_CH1_MB14_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH1_MB14_MBD_SHIFT)) & CE_MRU_CH1_MB14_MBD_MASK) 697 /*! @} */ 698 699 /*! @name CH1_MB15 - Channel (x) Mailbox (n) */ 700 /*! @{ */ 701 702 #define CE_MRU_CH1_MB15_MBD_MASK (0xFFFFFFFFU) 703 #define CE_MRU_CH1_MB15_MBD_SHIFT (0U) 704 #define CE_MRU_CH1_MB15_MBD_WIDTH (32U) 705 #define CE_MRU_CH1_MB15_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH1_MB15_MBD_SHIFT)) & CE_MRU_CH1_MB15_MBD_MASK) 706 /*! @} */ 707 708 /*! @name CH2_MB0 - Channel (x) Mailbox (n) */ 709 /*! @{ */ 710 711 #define CE_MRU_CH2_MB0_MBD_MASK (0xFFFFFFFFU) 712 #define CE_MRU_CH2_MB0_MBD_SHIFT (0U) 713 #define CE_MRU_CH2_MB0_MBD_WIDTH (32U) 714 #define CE_MRU_CH2_MB0_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH2_MB0_MBD_SHIFT)) & CE_MRU_CH2_MB0_MBD_MASK) 715 /*! @} */ 716 717 /*! @name CH2_MB1 - Channel (x) Mailbox (n) */ 718 /*! @{ */ 719 720 #define CE_MRU_CH2_MB1_MBD_MASK (0xFFFFFFFFU) 721 #define CE_MRU_CH2_MB1_MBD_SHIFT (0U) 722 #define CE_MRU_CH2_MB1_MBD_WIDTH (32U) 723 #define CE_MRU_CH2_MB1_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH2_MB1_MBD_SHIFT)) & CE_MRU_CH2_MB1_MBD_MASK) 724 /*! @} */ 725 726 /*! @name CH2_MB2 - Channel (x) Mailbox (n) */ 727 /*! @{ */ 728 729 #define CE_MRU_CH2_MB2_MBD_MASK (0xFFFFFFFFU) 730 #define CE_MRU_CH2_MB2_MBD_SHIFT (0U) 731 #define CE_MRU_CH2_MB2_MBD_WIDTH (32U) 732 #define CE_MRU_CH2_MB2_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH2_MB2_MBD_SHIFT)) & CE_MRU_CH2_MB2_MBD_MASK) 733 /*! @} */ 734 735 /*! @name CH2_MB3 - Channel (x) Mailbox (n) */ 736 /*! @{ */ 737 738 #define CE_MRU_CH2_MB3_MBD_MASK (0xFFFFFFFFU) 739 #define CE_MRU_CH2_MB3_MBD_SHIFT (0U) 740 #define CE_MRU_CH2_MB3_MBD_WIDTH (32U) 741 #define CE_MRU_CH2_MB3_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH2_MB3_MBD_SHIFT)) & CE_MRU_CH2_MB3_MBD_MASK) 742 /*! @} */ 743 744 /*! @name CH2_MB4 - Channel (x) Mailbox (n) */ 745 /*! @{ */ 746 747 #define CE_MRU_CH2_MB4_MBD_MASK (0xFFFFFFFFU) 748 #define CE_MRU_CH2_MB4_MBD_SHIFT (0U) 749 #define CE_MRU_CH2_MB4_MBD_WIDTH (32U) 750 #define CE_MRU_CH2_MB4_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH2_MB4_MBD_SHIFT)) & CE_MRU_CH2_MB4_MBD_MASK) 751 /*! @} */ 752 753 /*! @name CH2_MB5 - Channel (x) Mailbox (n) */ 754 /*! @{ */ 755 756 #define CE_MRU_CH2_MB5_MBD_MASK (0xFFFFFFFFU) 757 #define CE_MRU_CH2_MB5_MBD_SHIFT (0U) 758 #define CE_MRU_CH2_MB5_MBD_WIDTH (32U) 759 #define CE_MRU_CH2_MB5_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH2_MB5_MBD_SHIFT)) & CE_MRU_CH2_MB5_MBD_MASK) 760 /*! @} */ 761 762 /*! @name CH2_MB6 - Channel (x) Mailbox (n) */ 763 /*! @{ */ 764 765 #define CE_MRU_CH2_MB6_MBD_MASK (0xFFFFFFFFU) 766 #define CE_MRU_CH2_MB6_MBD_SHIFT (0U) 767 #define CE_MRU_CH2_MB6_MBD_WIDTH (32U) 768 #define CE_MRU_CH2_MB6_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH2_MB6_MBD_SHIFT)) & CE_MRU_CH2_MB6_MBD_MASK) 769 /*! @} */ 770 771 /*! @name CH2_MB7 - Channel (x) Mailbox (n) */ 772 /*! @{ */ 773 774 #define CE_MRU_CH2_MB7_MBD_MASK (0xFFFFFFFFU) 775 #define CE_MRU_CH2_MB7_MBD_SHIFT (0U) 776 #define CE_MRU_CH2_MB7_MBD_WIDTH (32U) 777 #define CE_MRU_CH2_MB7_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH2_MB7_MBD_SHIFT)) & CE_MRU_CH2_MB7_MBD_MASK) 778 /*! @} */ 779 780 /*! @name CH2_MB8 - Channel (x) Mailbox (n) */ 781 /*! @{ */ 782 783 #define CE_MRU_CH2_MB8_MBD_MASK (0xFFFFFFFFU) 784 #define CE_MRU_CH2_MB8_MBD_SHIFT (0U) 785 #define CE_MRU_CH2_MB8_MBD_WIDTH (32U) 786 #define CE_MRU_CH2_MB8_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH2_MB8_MBD_SHIFT)) & CE_MRU_CH2_MB8_MBD_MASK) 787 /*! @} */ 788 789 /*! @name CH2_MB9 - Channel (x) Mailbox (n) */ 790 /*! @{ */ 791 792 #define CE_MRU_CH2_MB9_MBD_MASK (0xFFFFFFFFU) 793 #define CE_MRU_CH2_MB9_MBD_SHIFT (0U) 794 #define CE_MRU_CH2_MB9_MBD_WIDTH (32U) 795 #define CE_MRU_CH2_MB9_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH2_MB9_MBD_SHIFT)) & CE_MRU_CH2_MB9_MBD_MASK) 796 /*! @} */ 797 798 /*! @name CH2_MB10 - Channel (x) Mailbox (n) */ 799 /*! @{ */ 800 801 #define CE_MRU_CH2_MB10_MBD_MASK (0xFFFFFFFFU) 802 #define CE_MRU_CH2_MB10_MBD_SHIFT (0U) 803 #define CE_MRU_CH2_MB10_MBD_WIDTH (32U) 804 #define CE_MRU_CH2_MB10_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH2_MB10_MBD_SHIFT)) & CE_MRU_CH2_MB10_MBD_MASK) 805 /*! @} */ 806 807 /*! @name CH2_MB11 - Channel (x) Mailbox (n) */ 808 /*! @{ */ 809 810 #define CE_MRU_CH2_MB11_MBD_MASK (0xFFFFFFFFU) 811 #define CE_MRU_CH2_MB11_MBD_SHIFT (0U) 812 #define CE_MRU_CH2_MB11_MBD_WIDTH (32U) 813 #define CE_MRU_CH2_MB11_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH2_MB11_MBD_SHIFT)) & CE_MRU_CH2_MB11_MBD_MASK) 814 /*! @} */ 815 816 /*! @name CH2_MB12 - Channel (x) Mailbox (n) */ 817 /*! @{ */ 818 819 #define CE_MRU_CH2_MB12_MBD_MASK (0xFFFFFFFFU) 820 #define CE_MRU_CH2_MB12_MBD_SHIFT (0U) 821 #define CE_MRU_CH2_MB12_MBD_WIDTH (32U) 822 #define CE_MRU_CH2_MB12_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH2_MB12_MBD_SHIFT)) & CE_MRU_CH2_MB12_MBD_MASK) 823 /*! @} */ 824 825 /*! @name CH2_MB13 - Channel (x) Mailbox (n) */ 826 /*! @{ */ 827 828 #define CE_MRU_CH2_MB13_MBD_MASK (0xFFFFFFFFU) 829 #define CE_MRU_CH2_MB13_MBD_SHIFT (0U) 830 #define CE_MRU_CH2_MB13_MBD_WIDTH (32U) 831 #define CE_MRU_CH2_MB13_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH2_MB13_MBD_SHIFT)) & CE_MRU_CH2_MB13_MBD_MASK) 832 /*! @} */ 833 834 /*! @name CH2_MB14 - Channel (x) Mailbox (n) */ 835 /*! @{ */ 836 837 #define CE_MRU_CH2_MB14_MBD_MASK (0xFFFFFFFFU) 838 #define CE_MRU_CH2_MB14_MBD_SHIFT (0U) 839 #define CE_MRU_CH2_MB14_MBD_WIDTH (32U) 840 #define CE_MRU_CH2_MB14_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH2_MB14_MBD_SHIFT)) & CE_MRU_CH2_MB14_MBD_MASK) 841 /*! @} */ 842 843 /*! @name CH2_MB15 - Channel (x) Mailbox (n) */ 844 /*! @{ */ 845 846 #define CE_MRU_CH2_MB15_MBD_MASK (0xFFFFFFFFU) 847 #define CE_MRU_CH2_MB15_MBD_SHIFT (0U) 848 #define CE_MRU_CH2_MB15_MBD_WIDTH (32U) 849 #define CE_MRU_CH2_MB15_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH2_MB15_MBD_SHIFT)) & CE_MRU_CH2_MB15_MBD_MASK) 850 /*! @} */ 851 852 /*! @name CH3_MB0 - Channel (x) Mailbox (n) */ 853 /*! @{ */ 854 855 #define CE_MRU_CH3_MB0_MBD_MASK (0xFFFFFFFFU) 856 #define CE_MRU_CH3_MB0_MBD_SHIFT (0U) 857 #define CE_MRU_CH3_MB0_MBD_WIDTH (32U) 858 #define CE_MRU_CH3_MB0_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH3_MB0_MBD_SHIFT)) & CE_MRU_CH3_MB0_MBD_MASK) 859 /*! @} */ 860 861 /*! @name CH3_MB1 - Channel (x) Mailbox (n) */ 862 /*! @{ */ 863 864 #define CE_MRU_CH3_MB1_MBD_MASK (0xFFFFFFFFU) 865 #define CE_MRU_CH3_MB1_MBD_SHIFT (0U) 866 #define CE_MRU_CH3_MB1_MBD_WIDTH (32U) 867 #define CE_MRU_CH3_MB1_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH3_MB1_MBD_SHIFT)) & CE_MRU_CH3_MB1_MBD_MASK) 868 /*! @} */ 869 870 /*! @name CH3_MB2 - Channel (x) Mailbox (n) */ 871 /*! @{ */ 872 873 #define CE_MRU_CH3_MB2_MBD_MASK (0xFFFFFFFFU) 874 #define CE_MRU_CH3_MB2_MBD_SHIFT (0U) 875 #define CE_MRU_CH3_MB2_MBD_WIDTH (32U) 876 #define CE_MRU_CH3_MB2_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH3_MB2_MBD_SHIFT)) & CE_MRU_CH3_MB2_MBD_MASK) 877 /*! @} */ 878 879 /*! @name CH3_MB3 - Channel (x) Mailbox (n) */ 880 /*! @{ */ 881 882 #define CE_MRU_CH3_MB3_MBD_MASK (0xFFFFFFFFU) 883 #define CE_MRU_CH3_MB3_MBD_SHIFT (0U) 884 #define CE_MRU_CH3_MB3_MBD_WIDTH (32U) 885 #define CE_MRU_CH3_MB3_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH3_MB3_MBD_SHIFT)) & CE_MRU_CH3_MB3_MBD_MASK) 886 /*! @} */ 887 888 /*! @name CH3_MB4 - Channel (x) Mailbox (n) */ 889 /*! @{ */ 890 891 #define CE_MRU_CH3_MB4_MBD_MASK (0xFFFFFFFFU) 892 #define CE_MRU_CH3_MB4_MBD_SHIFT (0U) 893 #define CE_MRU_CH3_MB4_MBD_WIDTH (32U) 894 #define CE_MRU_CH3_MB4_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH3_MB4_MBD_SHIFT)) & CE_MRU_CH3_MB4_MBD_MASK) 895 /*! @} */ 896 897 /*! @name CH3_MB5 - Channel (x) Mailbox (n) */ 898 /*! @{ */ 899 900 #define CE_MRU_CH3_MB5_MBD_MASK (0xFFFFFFFFU) 901 #define CE_MRU_CH3_MB5_MBD_SHIFT (0U) 902 #define CE_MRU_CH3_MB5_MBD_WIDTH (32U) 903 #define CE_MRU_CH3_MB5_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH3_MB5_MBD_SHIFT)) & CE_MRU_CH3_MB5_MBD_MASK) 904 /*! @} */ 905 906 /*! @name CH3_MB6 - Channel (x) Mailbox (n) */ 907 /*! @{ */ 908 909 #define CE_MRU_CH3_MB6_MBD_MASK (0xFFFFFFFFU) 910 #define CE_MRU_CH3_MB6_MBD_SHIFT (0U) 911 #define CE_MRU_CH3_MB6_MBD_WIDTH (32U) 912 #define CE_MRU_CH3_MB6_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH3_MB6_MBD_SHIFT)) & CE_MRU_CH3_MB6_MBD_MASK) 913 /*! @} */ 914 915 /*! @name CH3_MB7 - Channel (x) Mailbox (n) */ 916 /*! @{ */ 917 918 #define CE_MRU_CH3_MB7_MBD_MASK (0xFFFFFFFFU) 919 #define CE_MRU_CH3_MB7_MBD_SHIFT (0U) 920 #define CE_MRU_CH3_MB7_MBD_WIDTH (32U) 921 #define CE_MRU_CH3_MB7_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH3_MB7_MBD_SHIFT)) & CE_MRU_CH3_MB7_MBD_MASK) 922 /*! @} */ 923 924 /*! @name CH3_MB8 - Channel (x) Mailbox (n) */ 925 /*! @{ */ 926 927 #define CE_MRU_CH3_MB8_MBD_MASK (0xFFFFFFFFU) 928 #define CE_MRU_CH3_MB8_MBD_SHIFT (0U) 929 #define CE_MRU_CH3_MB8_MBD_WIDTH (32U) 930 #define CE_MRU_CH3_MB8_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH3_MB8_MBD_SHIFT)) & CE_MRU_CH3_MB8_MBD_MASK) 931 /*! @} */ 932 933 /*! @name CH3_MB9 - Channel (x) Mailbox (n) */ 934 /*! @{ */ 935 936 #define CE_MRU_CH3_MB9_MBD_MASK (0xFFFFFFFFU) 937 #define CE_MRU_CH3_MB9_MBD_SHIFT (0U) 938 #define CE_MRU_CH3_MB9_MBD_WIDTH (32U) 939 #define CE_MRU_CH3_MB9_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH3_MB9_MBD_SHIFT)) & CE_MRU_CH3_MB9_MBD_MASK) 940 /*! @} */ 941 942 /*! @name CH3_MB10 - Channel (x) Mailbox (n) */ 943 /*! @{ */ 944 945 #define CE_MRU_CH3_MB10_MBD_MASK (0xFFFFFFFFU) 946 #define CE_MRU_CH3_MB10_MBD_SHIFT (0U) 947 #define CE_MRU_CH3_MB10_MBD_WIDTH (32U) 948 #define CE_MRU_CH3_MB10_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH3_MB10_MBD_SHIFT)) & CE_MRU_CH3_MB10_MBD_MASK) 949 /*! @} */ 950 951 /*! @name CH3_MB11 - Channel (x) Mailbox (n) */ 952 /*! @{ */ 953 954 #define CE_MRU_CH3_MB11_MBD_MASK (0xFFFFFFFFU) 955 #define CE_MRU_CH3_MB11_MBD_SHIFT (0U) 956 #define CE_MRU_CH3_MB11_MBD_WIDTH (32U) 957 #define CE_MRU_CH3_MB11_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH3_MB11_MBD_SHIFT)) & CE_MRU_CH3_MB11_MBD_MASK) 958 /*! @} */ 959 960 /*! @name CH3_MB12 - Channel (x) Mailbox (n) */ 961 /*! @{ */ 962 963 #define CE_MRU_CH3_MB12_MBD_MASK (0xFFFFFFFFU) 964 #define CE_MRU_CH3_MB12_MBD_SHIFT (0U) 965 #define CE_MRU_CH3_MB12_MBD_WIDTH (32U) 966 #define CE_MRU_CH3_MB12_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH3_MB12_MBD_SHIFT)) & CE_MRU_CH3_MB12_MBD_MASK) 967 /*! @} */ 968 969 /*! @name CH3_MB13 - Channel (x) Mailbox (n) */ 970 /*! @{ */ 971 972 #define CE_MRU_CH3_MB13_MBD_MASK (0xFFFFFFFFU) 973 #define CE_MRU_CH3_MB13_MBD_SHIFT (0U) 974 #define CE_MRU_CH3_MB13_MBD_WIDTH (32U) 975 #define CE_MRU_CH3_MB13_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH3_MB13_MBD_SHIFT)) & CE_MRU_CH3_MB13_MBD_MASK) 976 /*! @} */ 977 978 /*! @name CH3_MB14 - Channel (x) Mailbox (n) */ 979 /*! @{ */ 980 981 #define CE_MRU_CH3_MB14_MBD_MASK (0xFFFFFFFFU) 982 #define CE_MRU_CH3_MB14_MBD_SHIFT (0U) 983 #define CE_MRU_CH3_MB14_MBD_WIDTH (32U) 984 #define CE_MRU_CH3_MB14_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH3_MB14_MBD_SHIFT)) & CE_MRU_CH3_MB14_MBD_MASK) 985 /*! @} */ 986 987 /*! @name CH3_MB15 - Channel (x) Mailbox (n) */ 988 /*! @{ */ 989 990 #define CE_MRU_CH3_MB15_MBD_MASK (0xFFFFFFFFU) 991 #define CE_MRU_CH3_MB15_MBD_SHIFT (0U) 992 #define CE_MRU_CH3_MB15_MBD_WIDTH (32U) 993 #define CE_MRU_CH3_MB15_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH3_MB15_MBD_SHIFT)) & CE_MRU_CH3_MB15_MBD_MASK) 994 /*! @} */ 995 996 /*! @name CH4_MB0 - Channel (x) Mailbox (n) */ 997 /*! @{ */ 998 999 #define CE_MRU_CH4_MB0_MBD_MASK (0xFFFFFFFFU) 1000 #define CE_MRU_CH4_MB0_MBD_SHIFT (0U) 1001 #define CE_MRU_CH4_MB0_MBD_WIDTH (32U) 1002 #define CE_MRU_CH4_MB0_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH4_MB0_MBD_SHIFT)) & CE_MRU_CH4_MB0_MBD_MASK) 1003 /*! @} */ 1004 1005 /*! @name CH4_MB1 - Channel (x) Mailbox (n) */ 1006 /*! @{ */ 1007 1008 #define CE_MRU_CH4_MB1_MBD_MASK (0xFFFFFFFFU) 1009 #define CE_MRU_CH4_MB1_MBD_SHIFT (0U) 1010 #define CE_MRU_CH4_MB1_MBD_WIDTH (32U) 1011 #define CE_MRU_CH4_MB1_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH4_MB1_MBD_SHIFT)) & CE_MRU_CH4_MB1_MBD_MASK) 1012 /*! @} */ 1013 1014 /*! @name CH4_MB2 - Channel (x) Mailbox (n) */ 1015 /*! @{ */ 1016 1017 #define CE_MRU_CH4_MB2_MBD_MASK (0xFFFFFFFFU) 1018 #define CE_MRU_CH4_MB2_MBD_SHIFT (0U) 1019 #define CE_MRU_CH4_MB2_MBD_WIDTH (32U) 1020 #define CE_MRU_CH4_MB2_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH4_MB2_MBD_SHIFT)) & CE_MRU_CH4_MB2_MBD_MASK) 1021 /*! @} */ 1022 1023 /*! @name CH4_MB3 - Channel (x) Mailbox (n) */ 1024 /*! @{ */ 1025 1026 #define CE_MRU_CH4_MB3_MBD_MASK (0xFFFFFFFFU) 1027 #define CE_MRU_CH4_MB3_MBD_SHIFT (0U) 1028 #define CE_MRU_CH4_MB3_MBD_WIDTH (32U) 1029 #define CE_MRU_CH4_MB3_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH4_MB3_MBD_SHIFT)) & CE_MRU_CH4_MB3_MBD_MASK) 1030 /*! @} */ 1031 1032 /*! @name CH4_MB4 - Channel (x) Mailbox (n) */ 1033 /*! @{ */ 1034 1035 #define CE_MRU_CH4_MB4_MBD_MASK (0xFFFFFFFFU) 1036 #define CE_MRU_CH4_MB4_MBD_SHIFT (0U) 1037 #define CE_MRU_CH4_MB4_MBD_WIDTH (32U) 1038 #define CE_MRU_CH4_MB4_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH4_MB4_MBD_SHIFT)) & CE_MRU_CH4_MB4_MBD_MASK) 1039 /*! @} */ 1040 1041 /*! @name CH4_MB5 - Channel (x) Mailbox (n) */ 1042 /*! @{ */ 1043 1044 #define CE_MRU_CH4_MB5_MBD_MASK (0xFFFFFFFFU) 1045 #define CE_MRU_CH4_MB5_MBD_SHIFT (0U) 1046 #define CE_MRU_CH4_MB5_MBD_WIDTH (32U) 1047 #define CE_MRU_CH4_MB5_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH4_MB5_MBD_SHIFT)) & CE_MRU_CH4_MB5_MBD_MASK) 1048 /*! @} */ 1049 1050 /*! @name CH4_MB6 - Channel (x) Mailbox (n) */ 1051 /*! @{ */ 1052 1053 #define CE_MRU_CH4_MB6_MBD_MASK (0xFFFFFFFFU) 1054 #define CE_MRU_CH4_MB6_MBD_SHIFT (0U) 1055 #define CE_MRU_CH4_MB6_MBD_WIDTH (32U) 1056 #define CE_MRU_CH4_MB6_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH4_MB6_MBD_SHIFT)) & CE_MRU_CH4_MB6_MBD_MASK) 1057 /*! @} */ 1058 1059 /*! @name CH4_MB7 - Channel (x) Mailbox (n) */ 1060 /*! @{ */ 1061 1062 #define CE_MRU_CH4_MB7_MBD_MASK (0xFFFFFFFFU) 1063 #define CE_MRU_CH4_MB7_MBD_SHIFT (0U) 1064 #define CE_MRU_CH4_MB7_MBD_WIDTH (32U) 1065 #define CE_MRU_CH4_MB7_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH4_MB7_MBD_SHIFT)) & CE_MRU_CH4_MB7_MBD_MASK) 1066 /*! @} */ 1067 1068 /*! @name CH4_MB8 - Channel (x) Mailbox (n) */ 1069 /*! @{ */ 1070 1071 #define CE_MRU_CH4_MB8_MBD_MASK (0xFFFFFFFFU) 1072 #define CE_MRU_CH4_MB8_MBD_SHIFT (0U) 1073 #define CE_MRU_CH4_MB8_MBD_WIDTH (32U) 1074 #define CE_MRU_CH4_MB8_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH4_MB8_MBD_SHIFT)) & CE_MRU_CH4_MB8_MBD_MASK) 1075 /*! @} */ 1076 1077 /*! @name CH4_MB9 - Channel (x) Mailbox (n) */ 1078 /*! @{ */ 1079 1080 #define CE_MRU_CH4_MB9_MBD_MASK (0xFFFFFFFFU) 1081 #define CE_MRU_CH4_MB9_MBD_SHIFT (0U) 1082 #define CE_MRU_CH4_MB9_MBD_WIDTH (32U) 1083 #define CE_MRU_CH4_MB9_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH4_MB9_MBD_SHIFT)) & CE_MRU_CH4_MB9_MBD_MASK) 1084 /*! @} */ 1085 1086 /*! @name CH4_MB10 - Channel (x) Mailbox (n) */ 1087 /*! @{ */ 1088 1089 #define CE_MRU_CH4_MB10_MBD_MASK (0xFFFFFFFFU) 1090 #define CE_MRU_CH4_MB10_MBD_SHIFT (0U) 1091 #define CE_MRU_CH4_MB10_MBD_WIDTH (32U) 1092 #define CE_MRU_CH4_MB10_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH4_MB10_MBD_SHIFT)) & CE_MRU_CH4_MB10_MBD_MASK) 1093 /*! @} */ 1094 1095 /*! @name CH4_MB11 - Channel (x) Mailbox (n) */ 1096 /*! @{ */ 1097 1098 #define CE_MRU_CH4_MB11_MBD_MASK (0xFFFFFFFFU) 1099 #define CE_MRU_CH4_MB11_MBD_SHIFT (0U) 1100 #define CE_MRU_CH4_MB11_MBD_WIDTH (32U) 1101 #define CE_MRU_CH4_MB11_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH4_MB11_MBD_SHIFT)) & CE_MRU_CH4_MB11_MBD_MASK) 1102 /*! @} */ 1103 1104 /*! @name CH4_MB12 - Channel (x) Mailbox (n) */ 1105 /*! @{ */ 1106 1107 #define CE_MRU_CH4_MB12_MBD_MASK (0xFFFFFFFFU) 1108 #define CE_MRU_CH4_MB12_MBD_SHIFT (0U) 1109 #define CE_MRU_CH4_MB12_MBD_WIDTH (32U) 1110 #define CE_MRU_CH4_MB12_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH4_MB12_MBD_SHIFT)) & CE_MRU_CH4_MB12_MBD_MASK) 1111 /*! @} */ 1112 1113 /*! @name CH4_MB13 - Channel (x) Mailbox (n) */ 1114 /*! @{ */ 1115 1116 #define CE_MRU_CH4_MB13_MBD_MASK (0xFFFFFFFFU) 1117 #define CE_MRU_CH4_MB13_MBD_SHIFT (0U) 1118 #define CE_MRU_CH4_MB13_MBD_WIDTH (32U) 1119 #define CE_MRU_CH4_MB13_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH4_MB13_MBD_SHIFT)) & CE_MRU_CH4_MB13_MBD_MASK) 1120 /*! @} */ 1121 1122 /*! @name CH4_MB14 - Channel (x) Mailbox (n) */ 1123 /*! @{ */ 1124 1125 #define CE_MRU_CH4_MB14_MBD_MASK (0xFFFFFFFFU) 1126 #define CE_MRU_CH4_MB14_MBD_SHIFT (0U) 1127 #define CE_MRU_CH4_MB14_MBD_WIDTH (32U) 1128 #define CE_MRU_CH4_MB14_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH4_MB14_MBD_SHIFT)) & CE_MRU_CH4_MB14_MBD_MASK) 1129 /*! @} */ 1130 1131 /*! @name CH4_MB15 - Channel (x) Mailbox (n) */ 1132 /*! @{ */ 1133 1134 #define CE_MRU_CH4_MB15_MBD_MASK (0xFFFFFFFFU) 1135 #define CE_MRU_CH4_MB15_MBD_SHIFT (0U) 1136 #define CE_MRU_CH4_MB15_MBD_WIDTH (32U) 1137 #define CE_MRU_CH4_MB15_MBD(x) (((uint32_t)(((uint32_t)(x)) << CE_MRU_CH4_MB15_MBD_SHIFT)) & CE_MRU_CH4_MB15_MBD_MASK) 1138 /*! @} */ 1139 1140 /*! 1141 * @} 1142 */ /* end of group CE_MRU_Register_Masks */ 1143 1144 /*! 1145 * @} 1146 */ /* end of group CE_MRU_Peripheral_Access_Layer */ 1147 1148 #endif /* #if !defined(S32Z2_CE_MRU_H_) */ 1149
