1 /*
2 * Copyright 2021-2023 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file Mru_Ip_Irq.c
9 *
10 * @version 1.0.0
11 *
12 * @brief ISR handler file.
13 * @details Declaration APIs for Mru ISR.
14 *
15 * @addtogroup MRU_IP_DRIVER Mru Ip Driver
16 * @{
17 */
18
19 #ifdef __cplusplus
20 extern "C"
21 {
22 #endif
23
24 /*==================================================================================================
25 * INCLUDE FILES
26 * 1) system and project includes
27 * 2) needed interfaces from external units
28 * 3) internal and external interfaces from this unit
29 ==================================================================================================*/
30 #include "Mru_Ip.h"
31
32 /*==================================================================================================
33 * SOURCE FILE VERSION INFORMATION
34 ==================================================================================================*/
35 #define CDD_PLATFORM_MRU_IP_VENDOR_ID_IRQ_C 43
36 #define CDD_PLATFORM_MRU_IP_AR_RELEASE_MAJOR_VERSION_IRQ_C 4
37 #define CDD_PLATFORM_MRU_IP_AR_RELEASE_MINOR_VERSION_IRQ_C 7
38 #define CDD_PLATFORM_MRU_IP_AR_RELEASE_REVISION_VERSION_IRQ_C 0
39 #define CDD_PLATFORM_MRU_IP_SW_MAJOR_VERSION_IRQ_C 1
40 #define CDD_PLATFORM_MRU_IP_SW_MINOR_VERSION_IRQ_C 0
41 #define CDD_PLATFORM_MRU_IP_SW_PATCH_VERSION_IRQ_C 0
42 /*==================================================================================================
43 * FILE VERSION CHECKS
44 ==================================================================================================*/
45 /* Check if Mru_Ip.h and Mru_Ip_Irq.c are of the same vendor */
46 #if (CDD_PLATFORM_MRU_IP_VENDOR_ID != CDD_PLATFORM_MRU_IP_VENDOR_ID_IRQ_C)
47 #error "Mru_Ip.h and Mru_Ip_Irq.c have different vendor ids"
48 #endif
49 /* Check if Mru_Ip.h file and Mru_Ip_Irq.c file are of the same Autosar version */
50 #if ((CDD_PLATFORM_MRU_IP_AR_RELEASE_MAJOR_VERSION != CDD_PLATFORM_MRU_IP_AR_RELEASE_MAJOR_VERSION_IRQ_C) || \
51 (CDD_PLATFORM_MRU_IP_AR_RELEASE_MINOR_VERSION != CDD_PLATFORM_MRU_IP_AR_RELEASE_MINOR_VERSION_IRQ_C) || \
52 (CDD_PLATFORM_MRU_IP_AR_RELEASE_REVISION_VERSION != CDD_PLATFORM_MRU_IP_AR_RELEASE_REVISION_VERSION_IRQ_C))
53 #error "AutoSar Version Numbers of Mru_Ip.h and Mru_Ip_Irq.c are different"
54 #endif
55 #if ((CDD_PLATFORM_MRU_IP_SW_MAJOR_VERSION != CDD_PLATFORM_MRU_IP_SW_MAJOR_VERSION_IRQ_C) || \
56 (CDD_PLATFORM_MRU_IP_SW_MINOR_VERSION != CDD_PLATFORM_MRU_IP_SW_MINOR_VERSION_IRQ_C) || \
57 (CDD_PLATFORM_MRU_IP_SW_PATCH_VERSION != CDD_PLATFORM_MRU_IP_SW_PATCH_VERSION_IRQ_C))
58 #error "Software Version Numbers of Mru_Ip.h and Mru_Ip_Irq.c are different"
59 #endif
60 /*==================================================================================================
61 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
62 ==================================================================================================*/
63 /*==================================================================================================
64 * LOCAL MACROS
65 ==================================================================================================*/
66 /*==================================================================================================
67 * LOCAL CONSTANTS
68 ==================================================================================================*/
69 /*==================================================================================================
70 * LOCAL VARIABLES
71 ==================================================================================================*/
72 /*==================================================================================================
73 * GLOBAL CONSTANTS
74 ==================================================================================================*/
75 /*==================================================================================================
76 * GLOBAL VARIABLES
77 ==================================================================================================*/
78 #define PLATFORM_START_SEC_VAR_CLEARED_UNSPECIFIED
79 #include "Platform_MemMap.h"
80
81 extern Mru_Ip_StateStructureType* Mru_Ip_apxStateStructureArray[MRU_IP_NUMBER_OF_INSTANCES];
82
83 #define PLATFORM_STOP_SEC_VAR_CLEARED_UNSPECIFIED
84 #include "Platform_MemMap.h"
85 /*==================================================================================================
86 * LOCAL FUNCTION PROTOTYPES
87 ==================================================================================================*/
88 #define PLATFORM_START_SEC_CODE
89 #include "Platform_MemMap.h"
90
91 #ifdef SMU_MRU_ENABLED
92 #if (!defined MRU_IP_SKIP_SMU_MRU_INT0_HANDLER)
93 ISR(Mru_Ip_SMU_MRU_Int0_IRQHandler);
94 #endif
95 #if (!defined MRU_IP_SKIP_SMU_MRU_INT1_HANDLER)
96 ISR(Mru_Ip_SMU_MRU_Int1_IRQHandler);
97 #endif
98 #endif
99
100 #ifdef RTU0_MRU0_ENABLED
101 #if (!defined MRU_IP_SKIP_RTU0_MRU0_INT0_HANDLER)
102 ISR(Mru_Ip_RTU0_MRU0_Int0_IRQHandler);
103 #endif
104 #if (!defined MRU_IP_SKIP_RTU0_MRU0_INT1_HANDLER)
105 ISR(Mru_Ip_RTU0_MRU0_Int1_IRQHandler);
106 #endif
107 #endif
108
109 #ifdef RTU0_MRU1_ENABLED
110 #if (!defined MRU_IP_SKIP_RTU0_MRU1_INT0_HANDLER)
111 ISR(Mru_Ip_RTU0_MRU1_Int0_IRQHandler);
112 #endif
113 #if (!defined MRU_IP_SKIP_RTU0_MRU1_INT1_HANDLER)
114 ISR(Mru_Ip_RTU0_MRU1_Int1_IRQHandler);
115 #endif
116 #endif
117
118 #ifdef RTU0_MRU2_ENABLED
119 #if (!defined MRU_IP_SKIP_RTU0_MRU2_INT0_HANDLER)
120 ISR(Mru_Ip_RTU0_MRU2_Int0_IRQHandler);
121 #endif
122 #if (!defined MRU_IP_SKIP_RTU0_MRU2_INT1_HANDLER)
123 ISR(Mru_Ip_RTU0_MRU2_Int1_IRQHandler);
124 #endif
125 #endif
126
127 #ifdef RTU0_MRU3_ENABLED
128 #if (!defined MRU_IP_SKIP_RTU0_MRU3_INT0_HANDLER)
129 ISR(Mru_Ip_RTU0_MRU3_Int0_IRQHandler);
130 #endif
131 #if (!defined MRU_IP_SKIP_RTU0_MRU3_INT1_HANDLER)
132 ISR(Mru_Ip_RTU0_MRU3_Int1_IRQHandler);
133 #endif
134 #endif
135
136 #ifdef RTU1_MRU4_ENABLED
137 #if (!defined MRU_IP_SKIP_RTU1_MRU4_INT0_HANDLER)
138 ISR(Mru_Ip_RTU1_MRU4_Int0_IRQHandler);
139 #endif
140 #if (!defined MRU_IP_SKIP_RTU1_MRU4_INT1_HANDLER)
141 ISR(Mru_Ip_RTU1_MRU4_Int1_IRQHandler);
142 #endif
143 #endif
144
145 #ifdef RTU1_MRU5_ENABLED
146 #if (!defined MRU_IP_SKIP_RTU1_MRU5_INT0_HANDLER)
147 ISR(Mru_Ip_RTU1_MRU5_Int0_IRQHandler);
148 #endif
149 #if (!defined MRU_IP_SKIP_RTU1_MRU5_INT1_HANDLER)
150 ISR(Mru_Ip_RTU1_MRU5_Int1_IRQHandler);
151 #endif
152 #endif
153
154 #ifdef RTU1_MRU6_ENABLED
155 #if (!defined MRU_IP_SKIP_RTU1_MRU6_INT0_HANDLER)
156 ISR(Mru_Ip_RTU1_MRU6_Int0_IRQHandler);
157 #endif
158 #if (!defined MRU_IP_SKIP_RTU1_MRU6_INT1_HANDLER)
159 ISR(Mru_Ip_RTU1_MRU6_Int1_IRQHandler);
160 #endif
161 #endif
162
163 #ifdef RTU1_MRU7_ENABLED
164 #if (!defined MRU_IP_SKIP_RTU1_MRU7_INT0_HANDLER)
165 ISR(Mru_Ip_RTU1_MRU7_Int0_IRQHandler);
166 #endif
167 #if (!defined MRU_IP_SKIP_RTU1_MRU7_INT1_HANDLER)
168 ISR(Mru_Ip_RTU1_MRU7_Int1_IRQHandler);
169 #endif
170 #endif
171
172 #ifdef CE_MRU0_ENABLED
173 #if (!defined MRU_IP_SKIP_CE_MRU0_INT0_HANDLER)
174 ISR(Mru_Ip_CE_MRU0_Int0_IRQHandler);
175 #endif
176 #if (!defined MRU_IP_SKIP_CE_MRU0_INT1_HANDLER)
177 ISR(Mru_Ip_CE_MRU0_Int1_IRQHandler);
178 #endif
179 #endif
180
181 #ifdef CE_MRU1_ENABLED
182 #if (!defined MRU_IP_SKIP_CE_MRU1_INT0_HANDLER)
183 ISR(Mru_Ip_CE_MRU1_Int0_IRQHandler);
184 #endif
185 #if (!defined MRU_IP_SKIP_CE_MRU1_INT1_HANDLER)
186 ISR(Mru_Ip_CE_MRU1_Int1_IRQHandler);
187 #endif
188 #endif
189
190 #ifdef CE_MRU2_ENABLED
191 #if (!defined MRU_IP_SKIP_CE_MRU2_INT0_HANDLER)
192 ISR(Mru_Ip_CE_MRU2_Int0_IRQHandler);
193 #endif
194 #if (!defined MRU_IP_SKIP_CE_MRU2_INT1_HANDLER)
195 ISR(Mru_Ip_CE_MRU2_Int1_IRQHandler);
196 #endif
197 #endif
198
199 #ifdef CE_MRU3_ENABLED
200 #if (!defined MRU_IP_SKIP_CE_MRU3_INT0_HANDLER)
201 ISR(Mru_Ip_CE_MRU3_Int0_IRQHandler);
202 #endif
203 #if (!defined MRU_IP_SKIP_CE_MRU3_INT1_HANDLER)
204 ISR(Mru_Ip_CE_MRU3_Int1_IRQHandler);
205 #endif
206 #endif
207
208 #ifdef CE_MRU4_ENABLED
209 #if (!defined MRU_IP_SKIP_CE_MRU4_INT0_HANDLER)
210 ISR(Mru_Ip_CE_MRU4_Int0_IRQHandler);
211 #endif
212 #if (!defined MRU_IP_SKIP_CE_MRU4_INT1_HANDLER)
213 ISR(Mru_Ip_CE_MRU4_Int1_IRQHandler);
214 #endif
215 #endif
216
217 #ifdef CE_MRU5_ENABLED
218 #if (!defined MRU_IP_SKIP_CE_MRU5_INT0_HANDLER)
219 ISR(Mru_Ip_CE_MRU5_Int0_IRQHandler);
220 #endif
221 #if (!defined MRU_IP_SKIP_CE_MRU5_INT1_HANDLER)
222 ISR(Mru_Ip_CE_MRU5_Int1_IRQHandler);
223 #endif
224 #endif
225
226 #ifdef CE_MRU6_ENABLED
227 #if (!defined MRU_IP_SKIP_CE_MRU6_INT0_HANDLER)
228 ISR(Mru_Ip_CE_MRU6_Int0_IRQHandler);
229 #endif
230 #if (!defined MRU_IP_SKIP_CE_MRU6_INT1_HANDLER)
231 ISR(Mru_Ip_CE_MRU6_Int1_IRQHandler);
232 #endif
233 #endif
234
235 #ifdef CE_MRU7_ENABLED
236 #if (!defined MRU_IP_SKIP_CE_MRU7_INT0_HANDLER)
237 ISR(Mru_Ip_CE_MRU7_Int0_IRQHandler);
238 #endif
239 #if (!defined MRU_IP_SKIP_CE_MRU7_INT1_HANDLER)
240 ISR(Mru_Ip_CE_MRU7_Int1_IRQHandler);
241 #endif
242 #endif
243
244 #ifdef CE_MRU8_ENABLED
245 #if (!defined MRU_IP_SKIP_CE_MRU8_INT0_HANDLER)
246 ISR(Mru_Ip_CE_MRU8_Int0_IRQHandler);
247 #endif
248 #if (!defined MRU_IP_SKIP_CE_MRU8_INT1_HANDLER)
249 ISR(Mru_Ip_CE_MRU8_Int1_IRQHandler);
250 #endif
251 #endif
252
253 #ifdef CE_MRU9_ENABLED
254 #if (!defined MRU_IP_SKIP_CE_MRU9_INT0_HANDLER)
255 ISR(Mru_Ip_CE_MRU9_Int0_IRQHandler);
256 #endif
257 #if (!defined MRU_IP_SKIP_CE_MRU9_INT1_HANDLER)
258 ISR(Mru_Ip_CE_MRU9_Int1_IRQHandler);
259 #endif
260 #endif
261
262 #ifdef CE_MRU10_ENABLED
263 #if (!defined MRU_IP_SKIP_CE_MRU10_INT0_HANDLER)
264 ISR(Mru_Ip_CE_MRU10_Int0_IRQHandler);
265 #endif
266 #if (!defined MRU_IP_SKIP_CE_MRU10_INT1_HANDLER)
267 ISR(Mru_Ip_CE_MRU10_Int1_IRQHandler);
268 #endif
269 #endif
270
271 #ifdef CE_MRU11_ENABLED
272 #if (!defined MRU_IP_SKIP_CE_MRU11_INT0_HANDLER)
273 ISR(Mru_Ip_CE_MRU11_Int0_IRQHandler);
274 #endif
275 #if (!defined MRU_IP_SKIP_CE_MRU11_INT1_HANDLER)
276 ISR(Mru_Ip_CE_MRU11_Int1_IRQHandler);
277 #endif
278 #endif
279
280 #ifdef CE_MRU12_ENABLED
281 #if (!defined MRU_IP_SKIP_CE_MRU12_INT0_HANDLER)
282 ISR(Mru_Ip_CE_MRU12_Int0_IRQHandler);
283 #endif
284 #if (!defined MRU_IP_SKIP_CE_MRU12_INT1_HANDLER)
285 ISR(Mru_Ip_CE_MRU12_Int1_IRQHandler);
286 #endif
287 #endif
288
289 #ifdef CE_MRU13_ENABLED
290 #if (!defined MRU_IP_SKIP_CE_MRU13_INT0_HANDLER)
291 ISR(Mru_Ip_CE_MRU13_Int0_IRQHandler);
292 #endif
293 #if (!defined MRU_IP_SKIP_CE_MRU13_INT1_HANDLER)
294 ISR(Mru_Ip_CE_MRU13_Int1_IRQHandler);
295 #endif
296 #endif
297
298 #ifdef CE_MRU14_ENABLED
299 #if (!defined MRU_IP_SKIP_CE_MRU14_INT0_HANDLER)
300 ISR(Mru_Ip_CE_MRU14_Int0_IRQHandler);
301 #endif
302 #if (!defined MRU_IP_SKIP_CE_MRU14_INT1_HANDLER)
303 ISR(Mru_Ip_CE_MRU14_Int1_IRQHandler);
304 #endif
305 #endif
306
307 #ifdef CE_MRU15_ENABLED
308 #if (!defined MRU_IP_SKIP_CE_MRU15_INT0_HANDLER)
309 ISR(Mru_Ip_CE_MRU15_Int0_IRQHandler);
310 #endif
311 #if (!defined MRU_IP_SKIP_CE_MRU15_INT1_HANDLER)
312 ISR(Mru_Ip_CE_MRU15_Int1_IRQHandler);
313 #endif
314 #endif
315
316 #ifdef CE_MRU16_ENABLED
317 #if (!defined MRU_IP_SKIP_CE_MRU16_INT0_HANDLER)
318 ISR(Mru_Ip_CE_MRU16_Int0_IRQHandler);
319 #endif
320 #if (!defined MRU_IP_SKIP_CE_MRU16_INT1_HANDLER)
321 ISR(Mru_Ip_CE_MRU16_Int1_IRQHandler);
322 #endif
323 #endif
324
325 #ifdef CE_MRU17_ENABLED
326 #if (!defined MRU_IP_SKIP_CE_MRU17_INT0_HANDLER)
327 ISR(Mru_Ip_CE_MRU17_Int0_IRQHandler);
328 #endif
329 #if (!defined MRU_IP_SKIP_CE_MRU17_INT1_HANDLER)
330 ISR(Mru_Ip_CE_MRU17_Int1_IRQHandler);
331 #endif
332 #endif
333
334 #ifdef CE_MRU18_ENABLED
335 #if (!defined MRU_IP_SKIP_CE_MRU18_INT0_HANDLER)
336 ISR(Mru_Ip_CE_MRU18_Int0_IRQHandler);
337 #endif
338 #if (!defined MRU_IP_SKIP_CE_MRU18_INT1_HANDLER)
339 ISR(Mru_Ip_CE_MRU18_Int1_IRQHandler);
340 #endif
341 #endif
342
343 #ifdef CE_MRU19_ENABLED
344 #if (!defined MRU_IP_SKIP_CE_MRU19_INT0_HANDLER)
345 ISR(Mru_Ip_CE_MRU19_Int0_IRQHandler);
346 #endif
347 #if (!defined MRU_IP_SKIP_CE_MRU19_INT1_HANDLER)
348 ISR(Mru_Ip_CE_MRU19_Int1_IRQHandler);
349 #endif
350 #endif
351
352 #if ((defined CE_MRU6_ENABLED && (!defined MRU_IP_SKIP_CE_MRU6_INT0_HANDLER)) || (defined CE_MRU7_ENABLED && (!defined MRU_IP_SKIP_CE_MRU7_INT0_HANDLER)) || (defined CE_MRU8_ENABLED && (!defined MRU_IP_SKIP_CE_MRU8_INT0_HANDLER)) || \
353 (defined CE_MRU9_ENABLED && (!defined MRU_IP_SKIP_CE_MRU9_INT0_HANDLER)) || (defined CE_MRU10_ENABLED && (!defined MRU_IP_SKIP_CE_MRU10_INT0_HANDLER)) || (defined CE_MRU11_ENABLED && (!defined MRU_IP_SKIP_CE_MRU11_INT0_HANDLER)))
354 ISR(Mru_Ip_CE_MRU6_TO_MRU11_Int0_IRQHandler);
355 #endif
356 #if ((defined CE_MRU6_ENABLED && (!defined MRU_IP_SKIP_CE_MRU6_INT1_HANDLER)) || (defined CE_MRU7_ENABLED && (!defined MRU_IP_SKIP_CE_MRU7_INT1_HANDLER)) || (defined CE_MRU8_ENABLED && (!defined MRU_IP_SKIP_CE_MRU8_INT1_HANDLER)) || \
357 (defined CE_MRU9_ENABLED && (!defined MRU_IP_SKIP_CE_MRU9_INT1_HANDLER)) || (defined CE_MRU10_ENABLED && (!defined MRU_IP_SKIP_CE_MRU10_INT1_HANDLER)) || (defined CE_MRU11_ENABLED && (!defined MRU_IP_SKIP_CE_MRU11_INT1_HANDLER)))
358 ISR(Mru_Ip_CE_MRU6_TO_MRU11_Int1_IRQHandler);
359 #endif
360 /*==================================================================================================
361 * LOCAL FUNCTIONS
362 ==================================================================================================*/
363 /*==================================================================================================
364 * GLOBAL FUNCTIONS
365 ==================================================================================================*/
366 #ifdef SMU_MRU_ENABLED
367 #if (!defined MRU_IP_SKIP_SMU_MRU_INT0_HANDLER)
ISR(Mru_Ip_SMU_MRU_Int0_IRQHandler)368 ISR(Mru_Ip_SMU_MRU_Int0_IRQHandler)
369 {
370 SMU_MRU_Type* Base = Mru_Ip_apxSMU_Bases[MRU_IP_SMU_MRU_INSTANCE];
371 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_SMU_MRU_ID];
372 uint8 ChannelIdx;
373
374 if(NULL_PTR != State)
375 {
376 /* the driver has been initialized */
377 /* Processing IRQ */
378 Mru_Ip_IrqHandler(MRU_IP_SMU_MRU_ID, MRU_IP_INT_GROUP_0);
379 }
380 else
381 {
382 /* the driver has not been initialized */
383 /* clear all flags for all channels */
384 for(ChannelIdx = 0u; ChannelIdx < SMU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
385 {
386 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
387 }
388 }
389 }
390 #endif
391 #if (!defined MRU_IP_SKIP_SMU_MRU_INT1_HANDLER)
ISR(Mru_Ip_SMU_MRU_Int1_IRQHandler)392 ISR(Mru_Ip_SMU_MRU_Int1_IRQHandler)
393 {
394 SMU_MRU_Type* Base = Mru_Ip_apxSMU_Bases[MRU_IP_SMU_MRU_INSTANCE];
395 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_SMU_MRU_ID];
396 uint8 ChannelIdx;
397
398 if(NULL_PTR != State)
399 {
400 /* the driver has been initialized */
401 /* Processing IRQ */
402 Mru_Ip_IrqHandler(MRU_IP_SMU_MRU_ID, MRU_IP_INT_GROUP_1);
403 }
404 else
405 {
406 /* the driver has not been initialized */
407 /* clear all flags for all channels */
408 for(ChannelIdx = 0u; ChannelIdx < SMU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
409 {
410 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
411 }
412 }
413 }
414 #endif
415 #endif
416
417 #ifdef RTU0_MRU0_ENABLED
418 #if (!defined MRU_IP_SKIP_RTU0_MRU0_INT0_HANDLER)
ISR(Mru_Ip_RTU0_MRU0_Int0_IRQHandler)419 ISR(Mru_Ip_RTU0_MRU0_Int0_IRQHandler)
420 {
421 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU0_MRU0_INSTANCE];
422 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_RTU0_MRU0_ID];
423 uint8 ChannelIdx;
424
425 if(NULL_PTR != State)
426 {
427 /* the driver has been initialized */
428 /* Processing IRQ */
429 Mru_Ip_IrqHandler(MRU_IP_RTU0_MRU0_ID, MRU_IP_INT_GROUP_0);
430 }
431 else
432 {
433 /* the driver has not been initialized */
434 /* clear all flags for all channels */
435 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
436 {
437 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
438 }
439 }
440 }
441 #endif
442 #if (!defined MRU_IP_SKIP_RTU0_MRU0_INT1_HANDLER)
ISR(Mru_Ip_RTU0_MRU0_Int1_IRQHandler)443 ISR(Mru_Ip_RTU0_MRU0_Int1_IRQHandler)
444 {
445 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU0_MRU0_INSTANCE];
446 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_RTU0_MRU0_ID];
447 uint8 ChannelIdx;
448
449 if(NULL_PTR != State)
450 {
451 /* the driver has been initialized */
452 /* Processing IRQ */
453 Mru_Ip_IrqHandler(MRU_IP_RTU0_MRU0_ID, MRU_IP_INT_GROUP_1);
454 }
455 else
456 {
457 /* the driver has not been initialized */
458 /* clear all flags for all channels */
459 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
460 {
461 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
462 }
463 }
464 }
465 #endif
466 #endif
467
468 #ifdef RTU0_MRU1_ENABLED
469 #if (!defined MRU_IP_SKIP_RTU0_MRU1_INT0_HANDLER)
ISR(Mru_Ip_RTU0_MRU1_Int0_IRQHandler)470 ISR(Mru_Ip_RTU0_MRU1_Int0_IRQHandler)
471 {
472 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU0_MRU1_INSTANCE];
473 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_RTU0_MRU1_ID];
474 uint8 ChannelIdx;
475
476 if(NULL_PTR != State)
477 {
478 /* the driver has been initialized */
479 /* Processing IRQ */
480 Mru_Ip_IrqHandler(MRU_IP_RTU0_MRU1_ID, MRU_IP_INT_GROUP_0);
481 }
482 else
483 {
484 /* the driver has not been initialized */
485 /* clear all flags for all channels */
486 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
487 {
488 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
489 }
490 }
491 }
492 #endif
493 #if (!defined MRU_IP_SKIP_RTU0_MRU1_INT1_HANDLER)
ISR(Mru_Ip_RTU0_MRU1_Int1_IRQHandler)494 ISR(Mru_Ip_RTU0_MRU1_Int1_IRQHandler)
495 {
496 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU0_MRU1_INSTANCE];
497 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_RTU0_MRU1_ID];
498 uint8 ChannelIdx;
499
500 if(NULL_PTR != State)
501 {
502 /* the driver has been initialized */
503 /* Processing IRQ */
504 Mru_Ip_IrqHandler(MRU_IP_RTU0_MRU1_ID, MRU_IP_INT_GROUP_1);
505 }
506 else
507 {
508 /* the driver has not been initialized */
509 /* clear all flags for all channels */
510 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
511 {
512 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
513 }
514 }
515 }
516 #endif
517 #endif
518
519 #ifdef RTU0_MRU2_ENABLED
520 #if (!defined MRU_IP_SKIP_RTU0_MRU2_INT0_HANDLER)
ISR(Mru_Ip_RTU0_MRU2_Int0_IRQHandler)521 ISR(Mru_Ip_RTU0_MRU2_Int0_IRQHandler)
522 {
523 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU0_MRU2_INSTANCE];
524 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_RTU0_MRU2_ID];
525 uint8 ChannelIdx;
526
527 if(NULL_PTR != State)
528 {
529 /* the driver has been initialized */
530 /* Processing IRQ */
531 Mru_Ip_IrqHandler(MRU_IP_RTU0_MRU2_ID, MRU_IP_INT_GROUP_0);
532 }
533 else
534 {
535 /* the driver has not been initialized */
536 /* clear all flags for all channels */
537 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
538 {
539 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
540 }
541 }
542 }
543 #endif
544 #if (!defined MRU_IP_SKIP_RTU0_MRU2_INT1_HANDLER)
ISR(Mru_Ip_RTU0_MRU2_Int1_IRQHandler)545 ISR(Mru_Ip_RTU0_MRU2_Int1_IRQHandler)
546 {
547 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU0_MRU2_INSTANCE];
548 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_RTU0_MRU2_ID];
549 uint8 ChannelIdx;
550
551 if(NULL_PTR != State)
552 {
553 /* the driver has been initialized */
554 /* Processing IRQ */
555 Mru_Ip_IrqHandler(MRU_IP_RTU0_MRU2_ID, MRU_IP_INT_GROUP_1);
556 }
557 else
558 {
559 /* the driver has not been initialized */
560 /* clear all flags for all channels */
561 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
562 {
563 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
564 }
565 }
566 }
567 #endif
568 #endif
569
570 #ifdef RTU0_MRU3_ENABLED
571 #if (!defined MRU_IP_SKIP_RTU0_MRU3_INT0_HANDLER)
ISR(Mru_Ip_RTU0_MRU3_Int0_IRQHandler)572 ISR(Mru_Ip_RTU0_MRU3_Int0_IRQHandler)
573 {
574 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU0_MRU3_INSTANCE];
575 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_RTU0_MRU3_ID];
576 uint8 ChannelIdx;
577
578 if(NULL_PTR != State)
579 {
580 /* the driver has been initialized */
581 /* Processing IRQ */
582 Mru_Ip_IrqHandler(MRU_IP_RTU0_MRU3_ID, MRU_IP_INT_GROUP_0);
583 }
584 else
585 {
586 /* the driver has not been initialized */
587 /* clear all flags for all channels */
588 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
589 {
590 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
591 }
592 }
593 }
594 #endif
595 #if (!defined MRU_IP_SKIP_RTU0_MRU3_INT1_HANDLER)
ISR(Mru_Ip_RTU0_MRU3_Int1_IRQHandler)596 ISR(Mru_Ip_RTU0_MRU3_Int1_IRQHandler)
597 {
598 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU0_MRU3_INSTANCE];
599 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_RTU0_MRU3_ID];
600 uint8 ChannelIdx;
601
602 if(NULL_PTR != State)
603 {
604 /* the driver has been initialized */
605 /* Processing IRQ */
606 Mru_Ip_IrqHandler(MRU_IP_RTU0_MRU3_ID, MRU_IP_INT_GROUP_1);
607 }
608 else
609 {
610 /* the driver has not been initialized */
611 /* clear all flags for all channels */
612 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
613 {
614 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
615 }
616 }
617 }
618 #endif
619 #endif
620
621 #ifdef RTU1_MRU4_ENABLED
622 #if (!defined MRU_IP_SKIP_RTU1_MRU4_INT0_HANDLER)
ISR(Mru_Ip_RTU1_MRU4_Int0_IRQHandler)623 ISR(Mru_Ip_RTU1_MRU4_Int0_IRQHandler)
624 {
625 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU1_MRU4_INSTANCE];
626 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_RTU1_MRU4_ID];
627 uint8 ChannelIdx;
628
629 if(NULL_PTR != State)
630 {
631 /* the driver has been initialized */
632 /* Processing IRQ */
633 Mru_Ip_IrqHandler(MRU_IP_RTU1_MRU4_ID, MRU_IP_INT_GROUP_0);
634 }
635 else
636 {
637 /* the driver has not been initialized */
638 /* clear all flags for all channels */
639 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
640 {
641 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
642 }
643 }
644 }
645 #endif
646 #if (!defined MRU_IP_SKIP_RTU1_MRU4_INT1_HANDLER)
ISR(Mru_Ip_RTU1_MRU4_Int1_IRQHandler)647 ISR(Mru_Ip_RTU1_MRU4_Int1_IRQHandler)
648 {
649 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU1_MRU4_INSTANCE];
650 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_RTU1_MRU4_ID];
651 uint8 ChannelIdx;
652
653 if(NULL_PTR != State)
654 {
655 /* the driver has been initialized */
656 /* Processing IRQ */
657 Mru_Ip_IrqHandler(MRU_IP_RTU1_MRU4_ID, MRU_IP_INT_GROUP_1);
658 }
659 else
660 {
661 /* the driver has not been initialized */
662 /* clear all flags for all channels */
663 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
664 {
665 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
666 }
667 }
668 }
669 #endif
670 #endif
671
672 #ifdef RTU1_MRU5_ENABLED
673 #if (!defined MRU_IP_SKIP_RTU1_MRU5_INT0_HANDLER)
ISR(Mru_Ip_RTU1_MRU5_Int0_IRQHandler)674 ISR(Mru_Ip_RTU1_MRU5_Int0_IRQHandler)
675 {
676 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU1_MRU5_INSTANCE];
677 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_RTU1_MRU5_ID];
678 uint8 ChannelIdx;
679
680 if(NULL_PTR != State)
681 {
682 /* the driver has been initialized */
683 /* Processing IRQ */
684 Mru_Ip_IrqHandler(MRU_IP_RTU1_MRU5_ID, MRU_IP_INT_GROUP_0);
685 }
686 else
687 {
688 /* the driver has not been initialized */
689 /* clear all flags for all channels */
690 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
691 {
692 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
693 }
694 }
695 }
696 #endif
697 #if (!defined MRU_IP_SKIP_RTU1_MRU5_INT1_HANDLER)
ISR(Mru_Ip_RTU1_MRU5_Int1_IRQHandler)698 ISR(Mru_Ip_RTU1_MRU5_Int1_IRQHandler)
699 {
700 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU1_MRU5_INSTANCE];
701 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_RTU1_MRU5_ID];
702 uint8 ChannelIdx;
703
704 if(NULL_PTR != State)
705 {
706 /* the driver has been initialized */
707 /* Processing IRQ */
708 Mru_Ip_IrqHandler(MRU_IP_RTU1_MRU5_ID, MRU_IP_INT_GROUP_1);
709 }
710 else
711 {
712 /* the driver has not been initialized */
713 /* clear all flags for all channels */
714 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
715 {
716 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
717 }
718 }
719 }
720 #endif
721 #endif
722
723 #ifdef RTU1_MRU6_ENABLED
724 #if (!defined MRU_IP_SKIP_RTU1_MRU6_INT0_HANDLER)
ISR(Mru_Ip_RTU1_MRU6_Int0_IRQHandler)725 ISR(Mru_Ip_RTU1_MRU6_Int0_IRQHandler)
726 {
727 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU1_MRU6_INSTANCE];
728 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_RTU1_MRU6_ID];
729 uint8 ChannelIdx;
730
731 if(NULL_PTR != State)
732 {
733 /* the driver has been initialized */
734 /* Processing IRQ */
735 Mru_Ip_IrqHandler(MRU_IP_RTU1_MRU6_ID, MRU_IP_INT_GROUP_0);
736 }
737 else
738 {
739 /* the driver has not been initialized */
740 /* clear all flags for all channels */
741 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
742 {
743 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
744 }
745 }
746 }
747 #endif
748 #if (!defined MRU_IP_SKIP_RTU1_MRU6_INT1_HANDLER)
ISR(Mru_Ip_RTU1_MRU6_Int1_IRQHandler)749 ISR(Mru_Ip_RTU1_MRU6_Int1_IRQHandler)
750 {
751 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU1_MRU6_INSTANCE];
752 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_RTU1_MRU6_ID];
753 uint8 ChannelIdx;
754
755 if(NULL_PTR != State)
756 {
757 /* the driver has been initialized */
758 /* Processing IRQ */
759 Mru_Ip_IrqHandler(MRU_IP_RTU1_MRU6_ID, MRU_IP_INT_GROUP_1);
760 }
761 else
762 {
763 /* the driver has not been initialized */
764 /* clear all flags for all channels */
765 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
766 {
767 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
768 }
769 }
770 }
771 #endif
772 #endif
773
774 #ifdef RTU1_MRU7_ENABLED
775 #if (!defined MRU_IP_SKIP_RTU1_MRU7_INT0_HANDLER)
ISR(Mru_Ip_RTU1_MRU7_Int0_IRQHandler)776 ISR(Mru_Ip_RTU1_MRU7_Int0_IRQHandler)
777 {
778 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU1_MRU7_INSTANCE];
779 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_RTU1_MRU7_ID];
780 uint8 ChannelIdx;
781
782 if(NULL_PTR != State)
783 {
784 /* the driver has been initialized */
785 /* Processing IRQ */
786 Mru_Ip_IrqHandler(MRU_IP_RTU1_MRU7_ID, MRU_IP_INT_GROUP_0);
787 }
788 else
789 {
790 /* the driver has not been initialized */
791 /* clear all flags for all channels */
792 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
793 {
794 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
795 }
796 }
797 }
798 #endif
799 #if (!defined MRU_IP_SKIP_RTU1_MRU7_INT1_HANDLER)
ISR(Mru_Ip_RTU1_MRU7_Int1_IRQHandler)800 ISR(Mru_Ip_RTU1_MRU7_Int1_IRQHandler)
801 {
802 RTU_MRU_Type* Base = Mru_Ip_apxRTU_Bases[MRU_IP_RTU1_MRU7_INSTANCE];
803 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_RTU1_MRU7_ID];
804 uint8 ChannelIdx;
805
806 if(NULL_PTR != State)
807 {
808 /* the driver has been initialized */
809 /* Processing IRQ */
810 Mru_Ip_IrqHandler(MRU_IP_RTU1_MRU7_ID, MRU_IP_INT_GROUP_1);
811 }
812 else
813 {
814 /* the driver has not been initialized */
815 /* clear all flags for all channels */
816 for(ChannelIdx = 0u; ChannelIdx < RTU_MRU_CHXCONFIG_COUNT; ChannelIdx++)
817 {
818 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
819 }
820 }
821 }
822 #endif
823 #endif
824
825 #ifdef CE_MRU0_ENABLED
826 #if (!defined MRU_IP_SKIP_CE_MRU0_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU0_Int0_IRQHandler)827 ISR(Mru_Ip_CE_MRU0_Int0_IRQHandler)
828 {
829 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU0_INSTANCE];
830 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU0_ID];
831 uint8 ChannelIdx;
832
833 if(NULL_PTR != State)
834 {
835 /* the driver has been initialized */
836 /* Processing IRQ */
837 Mru_Ip_IrqHandler(MRU_IP_CE_MRU0_ID, MRU_IP_INT_GROUP_0);
838 }
839 else
840 {
841 /* the driver has not been initialized */
842 /* clear all flags for all channels */
843 for(ChannelIdx = 0u; ChannelIdx < CE_MRU0_CH_NUM; ChannelIdx++)
844 {
845 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
846 }
847 }
848 }
849 #endif
850 #if (!defined MRU_IP_SKIP_CE_MRU0_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU0_Int1_IRQHandler)851 ISR(Mru_Ip_CE_MRU0_Int1_IRQHandler)
852 {
853 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU0_INSTANCE];
854 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU0_ID];
855 uint8 ChannelIdx;
856
857 if(NULL_PTR != State)
858 {
859 /* the driver has been initialized */
860 /* Processing IRQ */
861 Mru_Ip_IrqHandler(MRU_IP_CE_MRU0_ID, MRU_IP_INT_GROUP_1);
862 }
863 else
864 {
865 /* the driver has not been initialized */
866 /* clear all flags for all channels */
867 for(ChannelIdx = 0u; ChannelIdx < CE_MRU0_CH_NUM; ChannelIdx++)
868 {
869 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
870 }
871 }
872 }
873 #endif
874 #endif
875
876 #ifdef CE_MRU1_ENABLED
877 #if (!defined MRU_IP_SKIP_CE_MRU1_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU1_Int0_IRQHandler)878 ISR(Mru_Ip_CE_MRU1_Int0_IRQHandler)
879 {
880 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU1_INSTANCE];
881 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU1_ID];
882 uint8 ChannelIdx;
883
884 if(NULL_PTR != State)
885 {
886 /* the driver has been initialized */
887 /* Processing IRQ */
888 Mru_Ip_IrqHandler(MRU_IP_CE_MRU1_ID, MRU_IP_INT_GROUP_0);
889 }
890 else
891 {
892 /* the driver has not been initialized */
893 /* clear all flags for all channels */
894 for(ChannelIdx = 0u; ChannelIdx < CE_MRU1_CH_NUM; ChannelIdx++)
895 {
896 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
897 }
898 }
899 }
900 #endif
901 #if (!defined MRU_IP_SKIP_CE_MRU1_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU1_Int1_IRQHandler)902 ISR(Mru_Ip_CE_MRU1_Int1_IRQHandler)
903 {
904 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU1_INSTANCE];
905 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU1_ID];
906 uint8 ChannelIdx;
907
908 if(NULL_PTR != State)
909 {
910 /* the driver has been initialized */
911 /* Processing IRQ */
912 Mru_Ip_IrqHandler(MRU_IP_CE_MRU1_ID, MRU_IP_INT_GROUP_1);
913 }
914 else
915 {
916 /* the driver has not been initialized */
917 /* clear all flags for all channels */
918 for(ChannelIdx = 0u; ChannelIdx < CE_MRU1_CH_NUM; ChannelIdx++)
919 {
920 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
921 }
922 }
923 }
924 #endif
925 #endif
926
927 #ifdef CE_MRU2_ENABLED
928 #if (!defined MRU_IP_SKIP_CE_MRU2_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU2_Int0_IRQHandler)929 ISR(Mru_Ip_CE_MRU2_Int0_IRQHandler)
930 {
931 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU2_INSTANCE];
932 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU2_ID];
933 uint8 ChannelIdx;
934
935 if(NULL_PTR != State)
936 {
937 /* the driver has been initialized */
938 /* Processing IRQ */
939 Mru_Ip_IrqHandler(MRU_IP_CE_MRU2_ID, MRU_IP_INT_GROUP_0);
940 }
941 else
942 {
943 /* the driver has not been initialized */
944 /* clear all flags for all channels */
945 for(ChannelIdx = 0u; ChannelIdx < CE_MRU2_CH_NUM; ChannelIdx++)
946 {
947 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
948 }
949 }
950 }
951 #endif
952 #if (!defined MRU_IP_SKIP_CE_MRU2_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU2_Int1_IRQHandler)953 ISR(Mru_Ip_CE_MRU2_Int1_IRQHandler)
954 {
955 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU2_INSTANCE];
956 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU2_ID];
957 uint8 ChannelIdx;
958
959 if(NULL_PTR != State)
960 {
961 /* the driver has been initialized */
962 /* Processing IRQ */
963 Mru_Ip_IrqHandler(MRU_IP_CE_MRU2_ID, MRU_IP_INT_GROUP_1);
964 }
965 else
966 {
967 /* the driver has not been initialized */
968 /* clear all flags for all channels */
969 for(ChannelIdx = 0u; ChannelIdx < CE_MRU2_CH_NUM; ChannelIdx++)
970 {
971 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
972 }
973 }
974 }
975 #endif
976 #endif
977
978 #ifdef CE_MRU3_ENABLED
979 #if (!defined MRU_IP_SKIP_CE_MRU3_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU3_Int0_IRQHandler)980 ISR(Mru_Ip_CE_MRU3_Int0_IRQHandler)
981 {
982 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU3_INSTANCE];
983 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU3_ID];
984 uint8 ChannelIdx;
985
986 if(NULL_PTR != State)
987 {
988 /* the driver has been initialized */
989 /* Processing IRQ */
990 Mru_Ip_IrqHandler(MRU_IP_CE_MRU3_ID, MRU_IP_INT_GROUP_0);
991 }
992 else
993 {
994 /* the driver has not been initialized */
995 /* clear all flags for all channels */
996 for(ChannelIdx = 0u; ChannelIdx < CE_MRU3_CH_NUM; ChannelIdx++)
997 {
998 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
999 }
1000 }
1001 }
1002 #endif
1003 #if (!defined MRU_IP_SKIP_CE_MRU3_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU3_Int1_IRQHandler)1004 ISR(Mru_Ip_CE_MRU3_Int1_IRQHandler)
1005 {
1006 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU3_INSTANCE];
1007 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU3_ID];
1008 uint8 ChannelIdx;
1009
1010 if(NULL_PTR != State)
1011 {
1012 /* the driver has been initialized */
1013 /* Processing IRQ */
1014 Mru_Ip_IrqHandler(MRU_IP_CE_MRU3_ID, MRU_IP_INT_GROUP_1);
1015 }
1016 else
1017 {
1018 /* the driver has not been initialized */
1019 /* clear all flags for all channels */
1020 for(ChannelIdx = 0u; ChannelIdx < CE_MRU3_CH_NUM; ChannelIdx++)
1021 {
1022 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1023 }
1024 }
1025 }
1026 #endif
1027 #endif
1028
1029 #ifdef CE_MRU4_ENABLED
1030 #if (!defined MRU_IP_SKIP_CE_MRU4_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU4_Int0_IRQHandler)1031 ISR(Mru_Ip_CE_MRU4_Int0_IRQHandler)
1032 {
1033 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU4_INSTANCE];
1034 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU4_ID];
1035 uint8 ChannelIdx;
1036
1037 if(NULL_PTR != State)
1038 {
1039 /* the driver has been initialized */
1040 /* Processing IRQ */
1041 Mru_Ip_IrqHandler(MRU_IP_CE_MRU4_ID, MRU_IP_INT_GROUP_0);
1042 }
1043 else
1044 {
1045 /* the driver has not been initialized */
1046 /* clear all flags for all channels */
1047 for(ChannelIdx = 0u; ChannelIdx < CE_MRU4_CH_NUM; ChannelIdx++)
1048 {
1049 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1050 }
1051 }
1052 }
1053 #endif
1054 #if (!defined MRU_IP_SKIP_CE_MRU4_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU4_Int1_IRQHandler)1055 ISR(Mru_Ip_CE_MRU4_Int1_IRQHandler)
1056 {
1057 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU4_INSTANCE];
1058 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU4_ID];
1059 uint8 ChannelIdx;
1060
1061 if(NULL_PTR != State)
1062 {
1063 /* the driver has been initialized */
1064 /* Processing IRQ */
1065 Mru_Ip_IrqHandler(MRU_IP_CE_MRU4_ID, MRU_IP_INT_GROUP_1);
1066 }
1067 else
1068 {
1069 /* the driver has not been initialized */
1070 /* clear all flags for all channels */
1071 for(ChannelIdx = 0u; ChannelIdx < CE_MRU4_CH_NUM; ChannelIdx++)
1072 {
1073 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1074 }
1075 }
1076 }
1077 #endif
1078 #endif
1079
1080 #ifdef CE_MRU5_ENABLED
1081 #if (!defined MRU_IP_SKIP_CE_MRU5_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU5_Int0_IRQHandler)1082 ISR(Mru_Ip_CE_MRU5_Int0_IRQHandler)
1083 {
1084 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU5_INSTANCE];
1085 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU5_ID];
1086 uint8 ChannelIdx;
1087
1088 if(NULL_PTR != State)
1089 {
1090 /* the driver has been initialized */
1091 /* Processing IRQ */
1092 Mru_Ip_IrqHandler(MRU_IP_CE_MRU5_ID, MRU_IP_INT_GROUP_0);
1093 }
1094 else
1095 {
1096 /* the driver has not been initialized */
1097 /* clear all flags for all channels */
1098 for(ChannelIdx = 0u; ChannelIdx < CE_MRU5_CH_NUM; ChannelIdx++)
1099 {
1100 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1101 }
1102 }
1103 }
1104 #endif
1105 #if (!defined MRU_IP_SKIP_CE_MRU5_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU5_Int1_IRQHandler)1106 ISR(Mru_Ip_CE_MRU5_Int1_IRQHandler)
1107 {
1108 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU5_INSTANCE];
1109 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU5_ID];
1110 uint8 ChannelIdx;
1111
1112 if(NULL_PTR != State)
1113 {
1114 /* the driver has been initialized */
1115 /* Processing IRQ */
1116 Mru_Ip_IrqHandler(MRU_IP_CE_MRU5_ID, MRU_IP_INT_GROUP_1);
1117 }
1118 else
1119 {
1120 /* the driver has not been initialized */
1121 /* clear all flags for all channels */
1122 for(ChannelIdx = 0u; ChannelIdx < CE_MRU5_CH_NUM; ChannelIdx++)
1123 {
1124 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1125 }
1126 }
1127 }
1128 #endif
1129 #endif
1130
1131 #ifdef CE_MRU6_ENABLED
1132 #if (!defined MRU_IP_SKIP_CE_MRU6_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU6_Int0_IRQHandler)1133 ISR(Mru_Ip_CE_MRU6_Int0_IRQHandler)
1134 {
1135 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU6_INSTANCE];
1136 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU6_ID];
1137 uint8 ChannelIdx;
1138
1139 if(NULL_PTR != State)
1140 {
1141 /* the driver has been initialized */
1142 /* Processing IRQ */
1143 Mru_Ip_IrqHandler(MRU_IP_CE_MRU6_ID, MRU_IP_INT_GROUP_0);
1144 }
1145 else
1146 {
1147 /* the driver has not been initialized */
1148 /* clear all flags for all channels */
1149 for(ChannelIdx = 0u; ChannelIdx < CE_MRU6_CH_NUM; ChannelIdx++)
1150 {
1151 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1152 }
1153 }
1154 }
1155 #endif
1156 #if (!defined MRU_IP_SKIP_CE_MRU6_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU6_Int1_IRQHandler)1157 ISR(Mru_Ip_CE_MRU6_Int1_IRQHandler)
1158 {
1159 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU6_INSTANCE];
1160 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU6_ID];
1161 uint8 ChannelIdx;
1162
1163 if(NULL_PTR != State)
1164 {
1165 /* the driver has been initialized */
1166 /* Processing IRQ */
1167 Mru_Ip_IrqHandler(MRU_IP_CE_MRU6_ID, MRU_IP_INT_GROUP_1);
1168 }
1169 else
1170 {
1171 /* the driver has not been initialized */
1172 /* clear all flags for all channels */
1173 for(ChannelIdx = 0u; ChannelIdx < CE_MRU6_CH_NUM; ChannelIdx++)
1174 {
1175 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1176 }
1177 }
1178 }
1179 #endif
1180 #endif
1181
1182 #ifdef CE_MRU7_ENABLED
1183 #if (!defined MRU_IP_SKIP_CE_MRU7_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU7_Int0_IRQHandler)1184 ISR(Mru_Ip_CE_MRU7_Int0_IRQHandler)
1185 {
1186 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU7_INSTANCE];
1187 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU7_ID];
1188 uint8 ChannelIdx;
1189
1190 if(NULL_PTR != State)
1191 {
1192 /* the driver has been initialized */
1193 /* Processing IRQ */
1194 Mru_Ip_IrqHandler(MRU_IP_CE_MRU7_ID, MRU_IP_INT_GROUP_0);
1195 }
1196 else
1197 {
1198 /* the driver has not been initialized */
1199 /* clear all flags for all channels */
1200 for(ChannelIdx = 0u; ChannelIdx < CE_MRU7_CH_NUM; ChannelIdx++)
1201 {
1202 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1203 }
1204 }
1205 }
1206 #endif
1207 #if (!defined MRU_IP_SKIP_CE_MRU7_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU7_Int1_IRQHandler)1208 ISR(Mru_Ip_CE_MRU7_Int1_IRQHandler)
1209 {
1210 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU7_INSTANCE];
1211 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU7_ID];
1212 uint8 ChannelIdx;
1213
1214 if(NULL_PTR != State)
1215 {
1216 /* the driver has been initialized */
1217 /* Processing IRQ */
1218 Mru_Ip_IrqHandler(MRU_IP_CE_MRU7_ID, MRU_IP_INT_GROUP_1);
1219 }
1220 else
1221 {
1222 /* the driver has not been initialized */
1223 /* clear all flags for all channels */
1224 for(ChannelIdx = 0u; ChannelIdx < CE_MRU7_CH_NUM; ChannelIdx++)
1225 {
1226 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1227 }
1228 }
1229 }
1230 #endif
1231 #endif
1232
1233 #ifdef CE_MRU8_ENABLED
1234 #if (!defined MRU_IP_SKIP_CE_MRU8_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU8_Int0_IRQHandler)1235 ISR(Mru_Ip_CE_MRU8_Int0_IRQHandler)
1236 {
1237 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU8_INSTANCE];
1238 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU8_ID];
1239 uint8 ChannelIdx;
1240
1241 if(NULL_PTR != State)
1242 {
1243 /* the driver has been initialized */
1244 /* Processing IRQ */
1245 Mru_Ip_IrqHandler(MRU_IP_CE_MRU8_ID, MRU_IP_INT_GROUP_0);
1246 }
1247 else
1248 {
1249 /* the driver has not been initialized */
1250 /* clear all flags for all channels */
1251 for(ChannelIdx = 0u; ChannelIdx < CE_MRU8_CH_NUM; ChannelIdx++)
1252 {
1253 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1254 }
1255 }
1256 }
1257 #endif
1258 #if (!defined MRU_IP_SKIP_CE_MRU8_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU8_Int1_IRQHandler)1259 ISR(Mru_Ip_CE_MRU8_Int1_IRQHandler)
1260 {
1261 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU8_INSTANCE];
1262 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU8_ID];
1263 uint8 ChannelIdx;
1264
1265 if(NULL_PTR != State)
1266 {
1267 /* the driver has been initialized */
1268 /* Processing IRQ */
1269 Mru_Ip_IrqHandler(MRU_IP_CE_MRU8_ID, MRU_IP_INT_GROUP_1);
1270 }
1271 else
1272 {
1273 /* the driver has not been initialized */
1274 /* clear all flags for all channels */
1275 for(ChannelIdx = 0u; ChannelIdx < CE_MRU8_CH_NUM; ChannelIdx++)
1276 {
1277 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1278 }
1279 }
1280 }
1281 #endif
1282 #endif
1283
1284 #ifdef CE_MRU9_ENABLED
1285 #if (!defined MRU_IP_SKIP_CE_MRU9_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU9_Int0_IRQHandler)1286 ISR(Mru_Ip_CE_MRU9_Int0_IRQHandler)
1287 {
1288 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU9_INSTANCE];
1289 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU9_ID];
1290 uint8 ChannelIdx;
1291
1292 if(NULL_PTR != State)
1293 {
1294 /* the driver has been initialized */
1295 /* Processing IRQ */
1296 Mru_Ip_IrqHandler(MRU_IP_CE_MRU9_ID, MRU_IP_INT_GROUP_0);
1297 }
1298 else
1299 {
1300 /* the driver has not been initialized */
1301 /* clear all flags for all channels */
1302 for(ChannelIdx = 0u; ChannelIdx < CE_MRU9_CH_NUM; ChannelIdx++)
1303 {
1304 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1305 }
1306 }
1307 }
1308 #endif
1309 #if (!defined MRU_IP_SKIP_CE_MRU9_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU9_Int1_IRQHandler)1310 ISR(Mru_Ip_CE_MRU9_Int1_IRQHandler)
1311 {
1312 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU9_INSTANCE];
1313 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU9_ID];
1314 uint8 ChannelIdx;
1315
1316 if(NULL_PTR != State)
1317 {
1318 /* the driver has been initialized */
1319 /* Processing IRQ */
1320 Mru_Ip_IrqHandler(MRU_IP_CE_MRU9_ID, MRU_IP_INT_GROUP_1);
1321 }
1322 else
1323 {
1324 /* the driver has not been initialized */
1325 /* clear all flags for all channels */
1326 for(ChannelIdx = 0u; ChannelIdx < CE_MRU9_CH_NUM; ChannelIdx++)
1327 {
1328 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1329 }
1330 }
1331 }
1332 #endif
1333 #endif
1334
1335 #ifdef CE_MRU10_ENABLED
1336 #if (!defined MRU_IP_SKIP_CE_MRU10_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU10_Int0_IRQHandler)1337 ISR(Mru_Ip_CE_MRU10_Int0_IRQHandler)
1338 {
1339 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU10_INSTANCE];
1340 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU10_ID];
1341 uint8 ChannelIdx;
1342
1343 if(NULL_PTR != State)
1344 {
1345 /* the driver has been initialized */
1346 /* Processing IRQ */
1347 Mru_Ip_IrqHandler(MRU_IP_CE_MRU10_ID, MRU_IP_INT_GROUP_0);
1348 }
1349 else
1350 {
1351 /* the driver has not been initialized */
1352 /* clear all flags for all channels */
1353 for(ChannelIdx = 0u; ChannelIdx < CE_MRU10_CH_NUM; ChannelIdx++)
1354 {
1355 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1356 }
1357 }
1358 }
1359 #endif
1360 #if (!defined MRU_IP_SKIP_CE_MRU10_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU10_Int1_IRQHandler)1361 ISR(Mru_Ip_CE_MRU10_Int1_IRQHandler)
1362 {
1363 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU10_INSTANCE];
1364 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU10_ID];
1365 uint8 ChannelIdx;
1366
1367 if(NULL_PTR != State)
1368 {
1369 /* the driver has been initialized */
1370 /* Processing IRQ */
1371 Mru_Ip_IrqHandler(MRU_IP_CE_MRU10_ID, MRU_IP_INT_GROUP_1);
1372 }
1373 else
1374 {
1375 /* the driver has not been initialized */
1376 /* clear all flags for all channels */
1377 for(ChannelIdx = 0u; ChannelIdx < CE_MRU10_CH_NUM; ChannelIdx++)
1378 {
1379 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1380 }
1381 }
1382 }
1383 #endif
1384 #endif
1385
1386 #ifdef CE_MRU11_ENABLED
1387 #if (!defined MRU_IP_SKIP_CE_MRU11_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU11_Int0_IRQHandler)1388 ISR(Mru_Ip_CE_MRU11_Int0_IRQHandler)
1389 {
1390 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU11_INSTANCE];
1391 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU11_ID];
1392 uint8 ChannelIdx;
1393
1394 if(NULL_PTR != State)
1395 {
1396 /* the driver has been initialized */
1397 /* Processing IRQ */
1398 Mru_Ip_IrqHandler(MRU_IP_CE_MRU11_ID, MRU_IP_INT_GROUP_0);
1399 }
1400 else
1401 {
1402 /* the driver has not been initialized */
1403 /* clear all flags for all channels */
1404 for(ChannelIdx = 0u; ChannelIdx < CE_MRU11_CH_NUM; ChannelIdx++)
1405 {
1406 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1407 }
1408 }
1409 }
1410 #endif
1411 #if (!defined MRU_IP_SKIP_CE_MRU11_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU11_Int1_IRQHandler)1412 ISR(Mru_Ip_CE_MRU11_Int1_IRQHandler)
1413 {
1414 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU11_INSTANCE];
1415 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU11_ID];
1416 uint8 ChannelIdx;
1417
1418 if(NULL_PTR != State)
1419 {
1420 /* the driver has been initialized */
1421 /* Processing IRQ */
1422 Mru_Ip_IrqHandler(MRU_IP_CE_MRU11_ID, MRU_IP_INT_GROUP_1);
1423 }
1424 else
1425 {
1426 /* the driver has not been initialized */
1427 /* clear all flags for all channels */
1428 for(ChannelIdx = 0u; ChannelIdx < CE_MRU11_CH_NUM; ChannelIdx++)
1429 {
1430 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1431 }
1432 }
1433 }
1434 #endif
1435 #endif
1436
1437 #ifdef CE_MRU12_ENABLED
1438 #if (!defined MRU_IP_SKIP_CE_MRU12_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU12_Int0_IRQHandler)1439 ISR(Mru_Ip_CE_MRU12_Int0_IRQHandler)
1440 {
1441 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU12_INSTANCE];
1442 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU12_ID];
1443 uint8 ChannelIdx;
1444
1445 if(NULL_PTR != State)
1446 {
1447 /* the driver has been initialized */
1448 /* Processing IRQ */
1449 Mru_Ip_IrqHandler(MRU_IP_CE_MRU12_ID, MRU_IP_INT_GROUP_0);
1450 }
1451 else
1452 {
1453 /* the driver has not been initialized */
1454 /* clear all flags for all channels */
1455 for(ChannelIdx = 0u; ChannelIdx < CE_MRU12_CH_NUM; ChannelIdx++)
1456 {
1457 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1458 }
1459 }
1460 }
1461 #endif
1462 #if (!defined MRU_IP_SKIP_CE_MRU12_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU12_Int1_IRQHandler)1463 ISR(Mru_Ip_CE_MRU12_Int1_IRQHandler)
1464 {
1465 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU12_INSTANCE];
1466 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU12_ID];
1467 uint8 ChannelIdx;
1468
1469 if(NULL_PTR != State)
1470 {
1471 /* the driver has been initialized */
1472 /* Processing IRQ */
1473 Mru_Ip_IrqHandler(MRU_IP_CE_MRU12_ID, MRU_IP_INT_GROUP_1);
1474 }
1475 else
1476 {
1477 /* the driver has not been initialized */
1478 /* clear all flags for all channels */
1479 for(ChannelIdx = 0u; ChannelIdx < CE_MRU12_CH_NUM; ChannelIdx++)
1480 {
1481 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1482 }
1483 }
1484 }
1485 #endif
1486 #endif
1487
1488 #ifdef CE_MRU13_ENABLED
1489 #if (!defined MRU_IP_SKIP_CE_MRU13_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU13_Int0_IRQHandler)1490 ISR(Mru_Ip_CE_MRU13_Int0_IRQHandler)
1491 {
1492 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU13_INSTANCE];
1493 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU13_ID];
1494 uint8 ChannelIdx;
1495
1496 if(NULL_PTR != State)
1497 {
1498 /* the driver has been initialized */
1499 /* Processing IRQ */
1500 Mru_Ip_IrqHandler(MRU_IP_CE_MRU13_ID, MRU_IP_INT_GROUP_0);
1501 }
1502 else
1503 {
1504 /* the driver has not been initialized */
1505 /* clear all flags for all channels */
1506 for(ChannelIdx = 0u; ChannelIdx < CE_MRU13_CH_NUM; ChannelIdx++)
1507 {
1508 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1509 }
1510 }
1511 }
1512 #endif
1513 #if (!defined MRU_IP_SKIP_CE_MRU13_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU13_Int1_IRQHandler)1514 ISR(Mru_Ip_CE_MRU13_Int1_IRQHandler)
1515 {
1516 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU13_INSTANCE];
1517 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU13_ID];
1518 uint8 ChannelIdx;
1519
1520 if(NULL_PTR != State)
1521 {
1522 /* the driver has been initialized */
1523 /* Processing IRQ */
1524 Mru_Ip_IrqHandler(MRU_IP_CE_MRU13_ID, MRU_IP_INT_GROUP_1);
1525 }
1526 else
1527 {
1528 /* the driver has not been initialized */
1529 /* clear all flags for all channels */
1530 for(ChannelIdx = 0u; ChannelIdx < CE_MRU13_CH_NUM; ChannelIdx++)
1531 {
1532 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1533 }
1534 }
1535 }
1536 #endif
1537 #endif
1538
1539 #ifdef CE_MRU14_ENABLED
1540 #if (!defined MRU_IP_SKIP_CE_MRU14_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU14_Int0_IRQHandler)1541 ISR(Mru_Ip_CE_MRU14_Int0_IRQHandler)
1542 {
1543 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU14_INSTANCE];
1544 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU14_ID];
1545 uint8 ChannelIdx;
1546
1547 if(NULL_PTR != State)
1548 {
1549 /* the driver has been initialized */
1550 /* Processing IRQ */
1551 Mru_Ip_IrqHandler(MRU_IP_CE_MRU14_ID, MRU_IP_INT_GROUP_0);
1552 }
1553 else
1554 {
1555 /* the driver has not been initialized */
1556 /* clear all flags for all channels */
1557 for(ChannelIdx = 0u; ChannelIdx < CE_MRU14_CH_NUM; ChannelIdx++)
1558 {
1559 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1560 }
1561 }
1562 }
1563 #endif
1564 #if (!defined MRU_IP_SKIP_CE_MRU14_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU14_Int1_IRQHandler)1565 ISR(Mru_Ip_CE_MRU14_Int1_IRQHandler)
1566 {
1567 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU14_INSTANCE];
1568 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU14_ID];
1569 uint8 ChannelIdx;
1570
1571 if(NULL_PTR != State)
1572 {
1573 /* the driver has been initialized */
1574 /* Processing IRQ */
1575 Mru_Ip_IrqHandler(MRU_IP_CE_MRU14_ID, MRU_IP_INT_GROUP_1);
1576 }
1577 else
1578 {
1579 /* the driver has not been initialized */
1580 /* clear all flags for all channels */
1581 for(ChannelIdx = 0u; ChannelIdx < CE_MRU14_CH_NUM; ChannelIdx++)
1582 {
1583 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1584 }
1585 }
1586 }
1587 #endif
1588 #endif
1589
1590 #ifdef CE_MRU15_ENABLED
1591 #if (!defined MRU_IP_SKIP_CE_MRU15_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU15_Int0_IRQHandler)1592 ISR(Mru_Ip_CE_MRU15_Int0_IRQHandler)
1593 {
1594 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU15_INSTANCE];
1595 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU15_ID];
1596 uint8 ChannelIdx;
1597
1598 if(NULL_PTR != State)
1599 {
1600 /* the driver has been initialized */
1601 /* Processing IRQ */
1602 Mru_Ip_IrqHandler(MRU_IP_CE_MRU15_ID, MRU_IP_INT_GROUP_0);
1603 }
1604 else
1605 {
1606 /* the driver has not been initialized */
1607 /* clear all flags for all channels */
1608 for(ChannelIdx = 0u; ChannelIdx < CE_MRU15_CH_NUM; ChannelIdx++)
1609 {
1610 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1611 }
1612 }
1613 }
1614 #endif
1615 #if (!defined MRU_IP_SKIP_CE_MRU15_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU15_Int1_IRQHandler)1616 ISR(Mru_Ip_CE_MRU15_Int1_IRQHandler)
1617 {
1618 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU15_INSTANCE];
1619 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU15_ID];
1620 uint8 ChannelIdx;
1621
1622 if(NULL_PTR != State)
1623 {
1624 /* the driver has been initialized */
1625 /* Processing IRQ */
1626 Mru_Ip_IrqHandler(MRU_IP_CE_MRU15_ID, MRU_IP_INT_GROUP_1);
1627 }
1628 else
1629 {
1630 /* the driver has not been initialized */
1631 /* clear all flags for all channels */
1632 for(ChannelIdx = 0u; ChannelIdx < CE_MRU15_CH_NUM; ChannelIdx++)
1633 {
1634 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1635 }
1636 }
1637 }
1638 #endif
1639 #endif
1640
1641 #ifdef CE_MRU16_ENABLED
1642 #if (!defined MRU_IP_SKIP_CE_MRU16_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU16_Int0_IRQHandler)1643 ISR(Mru_Ip_CE_MRU16_Int0_IRQHandler)
1644 {
1645 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU16_INSTANCE];
1646 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU16_ID];
1647 uint8 ChannelIdx;
1648
1649 if(NULL_PTR != State)
1650 {
1651 /* the driver has been initialized */
1652 /* Processing IRQ */
1653 Mru_Ip_IrqHandler(MRU_IP_CE_MRU16_ID, MRU_IP_INT_GROUP_0);
1654 }
1655 else
1656 {
1657 /* the driver has not been initialized */
1658 /* clear all flags for all channels */
1659 for(ChannelIdx = 0u; ChannelIdx < CE_MRU16_CH_NUM; ChannelIdx++)
1660 {
1661 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1662 }
1663 }
1664 }
1665 #endif
1666 #if (!defined MRU_IP_SKIP_CE_MRU16_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU16_Int1_IRQHandler)1667 ISR(Mru_Ip_CE_MRU16_Int1_IRQHandler)
1668 {
1669 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU16_INSTANCE];
1670 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU16_ID];
1671 uint8 ChannelIdx;
1672
1673 if(NULL_PTR != State)
1674 {
1675 /* the driver has been initialized */
1676 /* Processing IRQ */
1677 Mru_Ip_IrqHandler(MRU_IP_CE_MRU16_ID, MRU_IP_INT_GROUP_1);
1678 }
1679 else
1680 {
1681 /* the driver has not been initialized */
1682 /* clear all flags for all channels */
1683 for(ChannelIdx = 0u; ChannelIdx < CE_MRU16_CH_NUM; ChannelIdx++)
1684 {
1685 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1686 }
1687 }
1688 }
1689 #endif
1690 #endif
1691
1692 #ifdef CE_MRU17_ENABLED
1693 #if (!defined MRU_IP_SKIP_CE_MRU17_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU17_Int0_IRQHandler)1694 ISR(Mru_Ip_CE_MRU17_Int0_IRQHandler)
1695 {
1696 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU17_INSTANCE];
1697 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU17_ID];
1698 uint8 ChannelIdx;
1699
1700 if(NULL_PTR != State)
1701 {
1702 /* the driver has been initialized */
1703 /* Processing IRQ */
1704 Mru_Ip_IrqHandler(MRU_IP_CE_MRU17_ID, MRU_IP_INT_GROUP_0);
1705 }
1706 else
1707 {
1708 /* the driver has not been initialized */
1709 /* clear all flags for all channels */
1710 for(ChannelIdx = 0u; ChannelIdx < CE_MRU17_CH_NUM; ChannelIdx++)
1711 {
1712 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1713 }
1714 }
1715 }
1716 #endif
1717 #if (!defined MRU_IP_SKIP_CE_MRU17_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU17_Int1_IRQHandler)1718 ISR(Mru_Ip_CE_MRU17_Int1_IRQHandler)
1719 {
1720 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU17_INSTANCE];
1721 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU17_ID];
1722 uint8 ChannelIdx;
1723
1724 if(NULL_PTR != State)
1725 {
1726 /* the driver has been initialized */
1727 /* Processing IRQ */
1728 Mru_Ip_IrqHandler(MRU_IP_CE_MRU17_ID, MRU_IP_INT_GROUP_1);
1729 }
1730 else
1731 {
1732 /* the driver has not been initialized */
1733 /* clear all flags for all channels */
1734 for(ChannelIdx = 0u; ChannelIdx < CE_MRU17_CH_NUM; ChannelIdx++)
1735 {
1736 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1737 }
1738 }
1739 }
1740 #endif
1741 #endif
1742
1743 #ifdef CE_MRU18_ENABLED
1744 #if (!defined MRU_IP_SKIP_CE_MRU18_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU18_Int0_IRQHandler)1745 ISR(Mru_Ip_CE_MRU18_Int0_IRQHandler)
1746 {
1747 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU18_INSTANCE];
1748 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU18_ID];
1749 uint8 ChannelIdx;
1750
1751 if(NULL_PTR != State)
1752 {
1753 /* the driver has been initialized */
1754 /* Processing IRQ */
1755 Mru_Ip_IrqHandler(MRU_IP_CE_MRU18_ID, MRU_IP_INT_GROUP_0);
1756 }
1757 else
1758 {
1759 /* the driver has not been initialized */
1760 /* clear all flags for all channels */
1761 for(ChannelIdx = 0u; ChannelIdx < CE_MRU18_CH_NUM; ChannelIdx++)
1762 {
1763 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1764 }
1765 }
1766 }
1767 #endif
1768 #if (!defined MRU_IP_SKIP_CE_MRU18_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU18_Int1_IRQHandler)1769 ISR(Mru_Ip_CE_MRU18_Int1_IRQHandler)
1770 {
1771 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU18_INSTANCE];
1772 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU18_ID];
1773 uint8 ChannelIdx;
1774
1775 if(NULL_PTR != State)
1776 {
1777 /* the driver has been initialized */
1778 /* Processing IRQ */
1779 Mru_Ip_IrqHandler(MRU_IP_CE_MRU18_ID, MRU_IP_INT_GROUP_1);
1780 }
1781 else
1782 {
1783 /* the driver has not been initialized */
1784 /* clear all flags for all channels */
1785 for(ChannelIdx = 0u; ChannelIdx < CE_MRU18_CH_NUM; ChannelIdx++)
1786 {
1787 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1788 }
1789 }
1790 }
1791 #endif
1792 #endif
1793
1794 #ifdef CE_MRU19_ENABLED
1795 #if (!defined MRU_IP_SKIP_CE_MRU19_INT0_HANDLER)
ISR(Mru_Ip_CE_MRU19_Int0_IRQHandler)1796 ISR(Mru_Ip_CE_MRU19_Int0_IRQHandler)
1797 {
1798 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU19_INSTANCE];
1799 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU19_ID];
1800 uint8 ChannelIdx;
1801
1802 if(NULL_PTR != State)
1803 {
1804 /* the driver has been initialized */
1805 /* Processing IRQ */
1806 Mru_Ip_IrqHandler(MRU_IP_CE_MRU19_ID, MRU_IP_INT_GROUP_0);
1807 }
1808 else
1809 {
1810 /* the driver has not been initialized */
1811 /* clear all flags for all channels */
1812 for(ChannelIdx = 0u; ChannelIdx < CE_MRU19_CH_NUM; ChannelIdx++)
1813 {
1814 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1815 }
1816 }
1817 }
1818 #endif
1819 #if (!defined MRU_IP_SKIP_CE_MRU19_INT1_HANDLER)
ISR(Mru_Ip_CE_MRU19_Int1_IRQHandler)1820 ISR(Mru_Ip_CE_MRU19_Int1_IRQHandler)
1821 {
1822 CE_MRU_Type* Base = Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU19_INSTANCE];
1823 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU19_ID];
1824 uint8 ChannelIdx;
1825
1826 if(NULL_PTR != State)
1827 {
1828 /* the driver has been initialized */
1829 /* Processing IRQ */
1830 Mru_Ip_IrqHandler(MRU_IP_CE_MRU19_ID, MRU_IP_INT_GROUP_1);
1831 }
1832 else
1833 {
1834 /* the driver has not been initialized */
1835 /* clear all flags for all channels */
1836 for(ChannelIdx = 0u; ChannelIdx < CE_MRU19_CH_NUM; ChannelIdx++)
1837 {
1838 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1839 }
1840 }
1841 }
1842 #endif
1843 #endif
1844
1845 #if ((defined CE_MRU6_ENABLED && (!defined MRU_IP_SKIP_CE_MRU6_INT0_HANDLER)) || (defined CE_MRU7_ENABLED && (!defined MRU_IP_SKIP_CE_MRU7_INT0_HANDLER)) || (defined CE_MRU8_ENABLED && (!defined MRU_IP_SKIP_CE_MRU8_INT0_HANDLER)) || \
1846 (defined CE_MRU9_ENABLED && (!defined MRU_IP_SKIP_CE_MRU9_INT0_HANDLER)) || (defined CE_MRU10_ENABLED && (!defined MRU_IP_SKIP_CE_MRU10_INT0_HANDLER)) || (defined CE_MRU11_ENABLED && (!defined MRU_IP_SKIP_CE_MRU11_INT0_HANDLER)))
ISR(Mru_Ip_CE_MRU6_TO_MRU11_Int0_IRQHandler)1847 ISR(Mru_Ip_CE_MRU6_TO_MRU11_Int0_IRQHandler)
1848 {
1849 #if defined CE_MRU6_ENABLED
1850 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU6_ID];
1851 #elif defined CE_MRU7_ENABLED
1852 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU7_ID];
1853 #elif defined CE_MRU8_ENABLED
1854 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU8_ID];
1855 #elif defined CE_MRU9_ENABLED
1856 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU9_ID];
1857 #elif defined CE_MRU10_ENABLED
1858 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU10_ID];
1859 #elif defined CE_MRU11_ENABLED
1860 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU11_ID];
1861 #endif
1862 uint8 ChannelIdx;
1863
1864 if(NULL_PTR != State)
1865 {
1866 /* the driver has been initialized */
1867 /* Processing IRQ */
1868 #if defined CE_MRU6_ENABLED
1869 Mru_Ip_IrqHandler(MRU_IP_CE_MRU6_ID, MRU_IP_INT_GROUP_0);
1870 #endif
1871 #if defined CE_MRU7_ENABLED
1872 Mru_Ip_IrqHandler(MRU_IP_CE_MRU7_ID, MRU_IP_INT_GROUP_0);
1873 #endif
1874 #if defined CE_MRU8_ENABLED
1875 Mru_Ip_IrqHandler(MRU_IP_CE_MRU8_ID, MRU_IP_INT_GROUP_0);
1876 #endif
1877 #if defined CE_MRU9_ENABLED
1878 Mru_Ip_IrqHandler(MRU_IP_CE_MRU9_ID, MRU_IP_INT_GROUP_0);
1879 #endif
1880 #if defined CE_MRU10_ENABLED
1881 Mru_Ip_IrqHandler(MRU_IP_CE_MRU10_ID, MRU_IP_INT_GROUP_0);
1882 #endif
1883 #if defined CE_MRU11_ENABLED
1884 Mru_Ip_IrqHandler(MRU_IP_CE_MRU11_ID, MRU_IP_INT_GROUP_0);
1885 #endif
1886 }
1887 else
1888 {
1889 /* the driver has not been initialized */
1890 /* clear all flags for all channels */
1891 for(ChannelIdx = 0u; ChannelIdx < CE_MRU_CHXCONFIG_COUNT; ChannelIdx++)
1892 {
1893 #if defined CE_MRU6_ENABLED
1894 Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU6_INSTANCE]->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1895 #endif
1896 #if defined CE_MRU7_ENABLED
1897 Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU7_INSTANCE]->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1898 #endif
1899 #if defined CE_MRU8_ENABLED
1900 Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU8_INSTANCE]->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1901 #endif
1902 #if defined CE_MRU9_ENABLED
1903 Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU9_INSTANCE]->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1904 #endif
1905 #if defined CE_MRU10_ENABLED
1906 Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU10_INSTANCE]->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1907 #endif
1908 #if defined CE_MRU11_ENABLED
1909 Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU11_INSTANCE]->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1910 #endif
1911 }
1912 }
1913 }
1914 #endif
1915 #if ((defined CE_MRU6_ENABLED && (!defined MRU_IP_SKIP_CE_MRU6_INT1_HANDLER)) || (defined CE_MRU7_ENABLED && (!defined MRU_IP_SKIP_CE_MRU7_INT1_HANDLER)) || (defined CE_MRU8_ENABLED && (!defined MRU_IP_SKIP_CE_MRU8_INT1_HANDLER)) || \
1916 (defined CE_MRU9_ENABLED && (!defined MRU_IP_SKIP_CE_MRU9_INT1_HANDLER)) || (defined CE_MRU10_ENABLED && (!defined MRU_IP_SKIP_CE_MRU10_INT1_HANDLER)) || (defined CE_MRU11_ENABLED && (!defined MRU_IP_SKIP_CE_MRU11_INT1_HANDLER)))
ISR(Mru_Ip_CE_MRU6_TO_MRU11_Int1_IRQHandler)1917 ISR(Mru_Ip_CE_MRU6_TO_MRU11_Int1_IRQHandler)
1918 {
1919 #if defined CE_MRU6_ENABLED
1920 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU6_ID];
1921 #elif defined CE_MRU7_ENABLED
1922 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU7_ID];
1923 #elif defined CE_MRU8_ENABLED
1924 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU8_ID];
1925 #elif defined CE_MRU9_ENABLED
1926 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU9_ID];
1927 #elif defined CE_MRU10_ENABLED
1928 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU10_ID];
1929 #elif defined CE_MRU11_ENABLED
1930 const Mru_Ip_StateStructureType* State = Mru_Ip_apxStateStructureArray[MRU_IP_CE_MRU11_ID];
1931 #endif
1932 uint8 ChannelIdx;
1933
1934 if(NULL_PTR != State)
1935 {
1936 /* the driver has been initialized */
1937 /* Processing IRQ */
1938 #if defined CE_MRU6_ENABLED
1939 Mru_Ip_IrqHandler(MRU_IP_CE_MRU6_ID, MRU_IP_INT_GROUP_1);
1940 #endif
1941 #if defined CE_MRU7_ENABLED
1942 Mru_Ip_IrqHandler(MRU_IP_CE_MRU7_ID, MRU_IP_INT_GROUP_1);
1943 #endif
1944 #if defined CE_MRU8_ENABLED
1945 Mru_Ip_IrqHandler(MRU_IP_CE_MRU8_ID, MRU_IP_INT_GROUP_1);
1946 #endif
1947 #if defined CE_MRU9_ENABLED
1948 Mru_Ip_IrqHandler(MRU_IP_CE_MRU9_ID, MRU_IP_INT_GROUP_1);
1949 #endif
1950 #if defined CE_MRU10_ENABLED
1951 Mru_Ip_IrqHandler(MRU_IP_CE_MRU10_ID, MRU_IP_INT_GROUP_1);
1952 #endif
1953 #if defined CE_MRU11_ENABLED
1954 Mru_Ip_IrqHandler(MRU_IP_CE_MRU11_ID, MRU_IP_INT_GROUP_1);
1955 #endif
1956 }
1957 else
1958 {
1959 /* the driver has not been initialized */
1960 /* clear all flags for all channels */
1961 for(ChannelIdx = 0u; ChannelIdx < CE_MRU_CHXCONFIG_COUNT; ChannelIdx++)
1962 {
1963 #if defined CE_MRU6_ENABLED
1964 Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU6_INSTANCE]->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1965 #endif
1966 #if defined CE_MRU7_ENABLED
1967 Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU7_INSTANCE]->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1968 #endif
1969 #if defined CE_MRU8_ENABLED
1970 Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU8_INSTANCE]->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1971 #endif
1972 #if defined CE_MRU9_ENABLED
1973 Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU9_INSTANCE]->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1974 #endif
1975 #if defined CE_MRU10_ENABLED
1976 Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU10_INSTANCE]->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1977 #endif
1978 #if defined CE_MRU11_ENABLED
1979 Mru_Ip_apxCE_Bases[MRU_IP_CE_MRU11_INSTANCE]->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu;
1980 #endif
1981 }
1982 }
1983 }
1984 #endif
1985
1986 #define PLATFORM_STOP_SEC_CODE
1987 #include "Platform_MemMap.h"
1988
1989 #ifdef __cplusplus
1990 }
1991 #endif
1992
1993 /** @} */
1994
1995
1996
1997
