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Searched refs:CHXCONFIG (Results 1 – 8 of 8) sorted by relevance

/hal_nxp-3.6.0/s32/drivers/s32ze/Platform/src/
DMru_Ip_Irq.c386 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
410 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
437 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
461 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
488 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
512 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
539 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
563 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
590 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
614 Base->CHXCONFIG[ChannelIdx].CH_MBSTAT &= (uint32)0xFFFFFFFFu; in ISR()
[all …]
/hal_nxp-3.6.0/s32/drivers/s32ze/Can_CANEXCEL/src/
DCanEXCEL_Ip_Irq.c71 …if ((IP_CANXL_0__MRU->CHXCONFIG[0u].CH_CFG0 & CANXL_MRU_CH_CFG0_CHE_MASK) == CANXL_MRU_CH_CFG0_CHE… in ISR()
89 …if ((IP_CANXL_1__MRU->CHXCONFIG[0u].CH_CFG0 & CANXL_MRU_CH_CFG0_CHE_MASK) == CANXL_MRU_CH_CFG0_CHE… in ISR()
DCanEXCEL_Ip.c62 if ((base->CHXCONFIG[0u].CH_MBSTAT & CANXL_MRU_CH_MBSTAT_MBS0_MASK) != 0U) in Canexcel_GetControllerMRU()
69 …base->CHXCONFIG[0u].CH_CFG0 |= CANXL_MRU_CH_CFG0_MBE0_MASK | CANXL_MRU_CH_CFG0_MBE3_MASK | CANXL_M… in Canexcel_GetControllerMRU()
70 base->CHXCONFIG[0u].CH_CFG1 |= CANXL_MRU_CH_CFG1_MBIC3_MASK; in Canexcel_GetControllerMRU()
71 base->CHXCONFIG[0u].CH_MBSTAT |= CANXL_MRU_CH_MBSTAT_MBS3_MASK; in Canexcel_GetControllerMRU()
991 if ((base->CHXCONFIG[0u].CH_CFG0 & CANXL_MRU_CH_CFG0_IE_MASK) == CANXL_MRU_CH_CFG0_IE_MASK) in Canexcel_Ip_MruIRQHandler()
995 uint32 tmp = base->CHXCONFIG[0u].CH_CFG1; in Canexcel_Ip_MruIRQHandler()
999 if ((base->CHXCONFIG[0u].CH_MBSTAT & mask) == mask) in Canexcel_Ip_MruIRQHandler()
1003 base->CHXCONFIG[0u].CH_MBSTAT |= mask; in Canexcel_Ip_MruIRQHandler()
/hal_nxp-3.6.0/s32/drivers/s32ze/Can_CANEXCEL/include/
DCanEXCEL_Ip_HwAccess.h752 base->CHXCONFIG[0u].CH_CFG0 = CANXL_MRU_CH_CFG0_CHR_MASK; in CanXL_MruEnable()
753 base->CHXCONFIG[0u].CH_CFG0 = CANXL_MRU_CH_CFG0_CHE_MASK; in CanXL_MruEnable()
762 base->CHXCONFIG[0u].CH_CFG0 = CANXL_MRU_CH_CFG0_CHR_MASK; in CanXL_MruDisable()
763 base->CHXCONFIG[0u].CH_CFG0 &= ~CANXL_MRU_CH_CFG0_CHE_MASK; in CanXL_MruDisable()
/hal_nxp-3.6.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_CANXL_MRU.h81 } CHXCONFIG[CANXL_MRU_CHXCONFIG_COUNT]; member
DS32Z2_SMU_MRU.h82 } CHXCONFIG[SMU_MRU_CHXCONFIG_COUNT]; member
DS32Z2_RTU_MRU.h82 } CHXCONFIG[RTU_MRU_CHXCONFIG_COUNT]; member
DS32Z2_CE_MRU.h82 } CHXCONFIG[CE_MRU_CHXCONFIG_COUNT]; member