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Searched refs:kLPSPI_MasterPcs0 (Results 1 – 25 of 33) sorted by relevance

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/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX3/template/
DRTE_Device.h159 #define RTE_SPI0_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
173 #define RTE_SPI1_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
187 #define RTE_SPI2_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
201 #define RTE_SPI3_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX5/template/
DRTE_Device.h159 #define RTE_SPI0_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
173 #define RTE_SPI1_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
187 #define RTE_SPI2_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
201 #define RTE_SPI3_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX4/template/
DRTE_Device.h159 #define RTE_SPI0_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
173 #define RTE_SPI1_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
187 #define RTE_SPI2_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
201 #define RTE_SPI3_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX6/template/
DRTE_Device.h159 #define RTE_SPI0_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
173 #define RTE_SPI1_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
187 #define RTE_SPI2_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
201 #define RTE_SPI3_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8UX5/template/
DRTE_Device.h159 #define RTE_SPI0_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
173 #define RTE_SPI1_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
187 #define RTE_SPI2_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
201 #define RTE_SPI3_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8UX6/template/
DRTE_Device.h159 #define RTE_SPI0_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
173 #define RTE_SPI1_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
187 #define RTE_SPI2_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
201 #define RTE_SPI3_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX3/template/
DRTE_Device.h159 #define RTE_SPI0_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
173 #define RTE_SPI1_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
187 #define RTE_SPI2_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
201 #define RTE_SPI3_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX2/template/
DRTE_Device.h159 #define RTE_SPI0_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
173 #define RTE_SPI1_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
187 #define RTE_SPI2_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
201 #define RTE_SPI3_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX5/template/
DRTE_Device.h159 #define RTE_SPI0_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
173 #define RTE_SPI1_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
187 #define RTE_SPI2_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
201 #define RTE_SPI3_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX1/template/
DRTE_Device.h159 #define RTE_SPI0_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
173 #define RTE_SPI1_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
187 #define RTE_SPI2_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
201 #define RTE_SPI3_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX4/template/
DRTE_Device.h159 #define RTE_SPI0_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
173 #define RTE_SPI1_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
187 #define RTE_SPI2_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
201 #define RTE_SPI3_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX1/template/
DRTE_Device.h159 #define RTE_SPI0_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
173 #define RTE_SPI1_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
187 #define RTE_SPI2_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
201 #define RTE_SPI3_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QX2/template/
DRTE_Device.h159 #define RTE_SPI0_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
173 #define RTE_SPI1_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
187 #define RTE_SPI2_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
201 #define RTE_SPI3_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8DX6/template/
DRTE_Device.h159 #define RTE_SPI0_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
173 #define RTE_SPI1_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
187 #define RTE_SPI2_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
201 #define RTE_SPI3_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMX8QM6/template/
DRTE_Device.h191 #define RTE_SPI0_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
204 #define RTE_SPI1_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
217 #define RTE_SPI2_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
230 #define RTE_SPI3_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1061/template/
DRTE_Device.h145 #define RTE_SPI0_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
161 #define RTE_SPI1_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
177 #define RTE_SPI2_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
193 #define RTE_SPI3_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1051/template/
DRTE_Device.h145 #define RTE_SPI0_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
161 #define RTE_SPI1_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
177 #define RTE_SPI2_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
193 #define RTE_SPI3_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1041/template/
DRTE_Device.h145 #define RTE_SPI0_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
161 #define RTE_SPI1_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
177 #define RTE_SPI2_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
193 #define RTE_SPI3_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MCIMX7U5/template/
DRTE_Device.h143 #define RTE_SPI0_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
159 #define RTE_SPI1_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
175 #define RTE_SPI2_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
191 #define RTE_SPI3_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MCIMX7U3/template/
DRTE_Device.h143 #define RTE_SPI0_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
159 #define RTE_SPI1_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
175 #define RTE_SPI2_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
191 #define RTE_SPI3_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
/hal_nxp-3.5.0/mcux/mcux-sdk/middleware/issdk/boardkit/evk-mimxrt1050/
DRTE_Device.h90 #define RTE_SPI1_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
104 #define RTE_SPI2_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
118 #define RTE_SPI3_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
132 #define RTE_SPI4_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
/hal_nxp-3.5.0/mcux/mcux-sdk/middleware/issdk/boardkit/evkb-imxrt1050/
DRTE_Device.h90 #define RTE_SPI1_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
104 #define RTE_SPI2_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
118 #define RTE_SPI3_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
132 #define RTE_SPI4_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1064/template/
DRTE_Device.h197 #define RTE_SPI1_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
213 #define RTE_SPI2_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
229 #define RTE_SPI3_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
245 #define RTE_SPI4_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L2A41A/template/
DRTE_Device.h121 #define RTE_SPI0_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
137 #define RTE_SPI1_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
153 #define RTE_SPI2_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L2A31A/template/
DRTE_Device.h121 #define RTE_SPI0_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
137 #define RTE_SPI1_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)
153 #define RTE_SPI2_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0)

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