1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2017-2020 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef _RTE_DEVICE_H 9 #define _RTE_DEVICE_H 10 11 #include "pin_mux.h" 12 13 /* UART Select, LPUART0 - LPUART4. */ 14 /* USART instance mapping */ 15 #define LPUART0 CM4__LPUART 16 #define LPUART1 ADMA__LPUART0 17 #define LPUART2 ADMA__LPUART1 18 #define LPUART3 ADMA__LPUART2 19 #define LPUART4 ADMA__LPUART3 20 21 /* User needs to provide the implementation of LPUARTX_GetFreq/LPUARTX_InitPins/LPUARTX_DeinitPins for the enabled 22 * LPUART instance. */ 23 #define RTE_USART0 0 24 #define RTE_USART0_DMA_EN 0 25 #define RTE_USART1 0 26 #define RTE_USART1_DMA_EN 0 27 #define RTE_USART2 0 28 #define RTE_USART2_DMA_EN 0 29 #define RTE_USART3 0 30 #define RTE_USART3_DMA_EN 0 31 #define RTE_USART4 0 32 #define RTE_USART4_DMA_EN 0 33 34 /* UART configuration. */ 35 #define USART_RX_BUFFER_LEN 64 36 #define USART0_RX_BUFFER_ENABLE 0 37 #define USART1_RX_BUFFER_ENABLE 0 38 #define USART2_RX_BUFFER_ENABLE 0 39 #define USART3_RX_BUFFER_ENABLE 0 40 #define USART4_RX_BUFFER_ENABLE 0 41 42 /* Note: LPUART0 not support DMA mode */ 43 #define RTE_USART1_PIN_INIT LPUART1_InitPins 44 #define RTE_USART1_PIN_DEINIT LPUART1_DeinitPins 45 #define RTE_USART1_DMA_TX_CH 9 46 #define RTE_USART1_DMA_TX_PERI_SEL 9 47 #define RTE_USART1_DMA_TX_DMA_BASE ADMA__EDMA2 48 #define RTE_USART1_DMA_RX_CH 8 49 #define RTE_USART1_DMA_RX_PERI_SEL 8 50 #define RTE_USART1_DMA_RX_DMA_BASE ADMA__EDMA2 51 52 #define RTE_USART2_PIN_INIT LPUART2_InitPins 53 #define RTE_USART2_PIN_DEINIT LPUART2_DeinitPins 54 #define RTE_USART2_DMA_TX_CH 11 55 #define RTE_USART2_DMA_TX_PERI_SEL 11 56 #define RTE_USART2_DMA_TX_DMA_BASE ADMA__EDMA2 57 #define RTE_USART2_DMA_RX_CH 10 58 #define RTE_USART2_DMA_RX_PERI_SEL 10 59 #define RTE_USART2_DMA_RX_DMA_BASE ADMA__EDMA2 60 61 #define RTE_USART3_PIN_INIT LPUART3_InitPins 62 #define RTE_USART3_PIN_DEINIT LPUART3_DeinitPins 63 #define RTE_USART3_DMA_TX_CH 13 64 #define RTE_USART3_DMA_TX_PERI_SEL 13 65 #define RTE_USART3_DMA_TX_DMA_BASE ADMA__EDMA2 66 #define RTE_USART3_DMA_RX_CH 12 67 #define RTE_USART3_DMA_RX_PERI_SEL 12 68 #define RTE_USART3_DMA_RX_DMA_BASE ADMA__EDMA2 69 70 #define RTE_USART4_PIN_INIT LPUART4_InitPins 71 #define RTE_USART4_PIN_DEINIT LPUART4_DeinitPins 72 #define RTE_USART4_DMA_TX_CH 15 73 #define RTE_USART4_DMA_TX_PERI_SEL 15 74 #define RTE_USART4_DMA_TX_DMA_BASE ADMA__EDMA2 75 #define RTE_USART4_DMA_RX_CH 14 76 #define RTE_USART4_DMA_RX_PERI_SEL 14 77 #define RTE_USART4_DMA_RX_DMA_BASE ADMA__EDMA2 78 79 /* I2C Select, LPI2C0 - LPI2C4. */ 80 /* LPI2C instance mapping */ 81 #define LPI2C0 CM4__LPI2C 82 #define LPI2C1 ADMA__LPI2C0 83 #define LPI2C2 ADMA__LPI2C1 84 #define LPI2C3 ADMA__LPI2C2 85 #define LPI2C4 ADMA__LPI2C3 86 87 /* User needs to provide the implementation of LPI2CX_GetFreq/LPI2CX_InitPins/LPI2CX_DeinitPins for the enabled LPI2C 88 * instance. */ 89 #define RTE_I2C0 0 90 #define RTE_I2C0_DMA_EN 0 91 #define RTE_I2C1 0 92 #define RTE_I2C1_DMA_EN 0 93 #define RTE_I2C2 0 94 #define RTE_I2C2_DMA_EN 0 95 #define RTE_I2C3 0 96 #define RTE_I2C3_DMA_EN 0 97 #define RTE_I2C4 0 98 #define RTE_I2C4_DMA_EN 0 99 100 /* LPI2C configuration. */ 101 /*Note: LPI2C0 not support DMA */ 102 #define RTE_I2C1_PIN_INIT LPI2C1_InitPins 103 #define RTE_I2C1_PIN_DEINIT LPI2C1_DeinitPins 104 #define RTE_I2C1_DMA_TX_CH 1 105 #define RTE_I2C1_DMA_TX_PERI_SEL 1 106 #define RTE_I2C1_DMA_TX_DMA_BASE ADMA__EDMA3 107 #define RTE_I2C1_DMA_RX_CH 0 108 #define RTE_I2C1_DMA_RX_PERI_SEL 0 109 #define RTE_I2C1_DMA_RX_DMA_BASE ADMA__EDMA3 110 111 #define RTE_I2C2_PIN_INIT LPI2C2_InitPins 112 #define RTE_I2C2_PIN_DEINIT LPI2C2_DeinitPins 113 #define RTE_I2C2_DMA_TX_CH 3 114 #define RTE_I2C2_DMA_TX_PERI_SEL 3 115 #define RTE_I2C2_DMA_TX_DMA_BASE ADMA__EDMA3 116 #define RTE_I2C2_DMA_RX_CH 2 117 #define RTE_I2C2_DMA_RX_PERI_SEL 2 118 #define RTE_I2C2_DMA_RX_DMA_BASE ADMA__EDMA3 119 120 #define RTE_I2C3_PIN_INIT LPI2C3_InitPins 121 #define RTE_I2C3_PIN_DEINIT LPI2C3_DeinitPins 122 #define RTE_I2C3_DMA_TX_CH 5 123 #define RTE_I2C3_DMA_TX_PERI_SEL 5 124 #define RTE_I2C3_DMA_TX_DMA_BASE ADMA__EDMA3 125 #define RTE_I2C3_DMA_RX_CH 4 126 #define RTE_I2C3_DMA_RX_PERI_SEL 4 127 #define RTE_I2C3_DMA_RX_DMA_BASE ADMA__EDMA3 128 129 #define RTE_I2C4_PIN_INIT LPI2C4_InitPins 130 #define RTE_I2C4_PIN_DEINIT LPI2C4_DeinitPins 131 #define RTE_I2C4_DMA_TX_CH 7 132 #define RTE_I2C4_DMA_TX_PERI_SEL 7 133 #define RTE_I2C4_DMA_TX_DMA_BASE ADMA__EDMA3 134 #define RTE_I2C4_DMA_RX_CH 6 135 #define RTE_I2C4_DMA_RX_PERI_SEL 6 136 #define RTE_I2C4_DMA_RX_DMA_BASE ADMA__EDMA3 137 138 /* SPI Select, LPSPI0 - LPSPI3. */ 139 #define LPSPI0 ADMA__LPSPI0 140 #define LPSPI1 ADMA__LPSPI1 141 #define LPSPI2 ADMA__LPSPI2 142 #define LPSPI3 ADMA__LPSPI3 143 144 /* User needs to provide the implementation of SPIX_GetFreq/SPIX_InitPins/SPIX_DeinitPins for the enabled SPI instance. 145 */ 146 #define RTE_SPI0 0 147 #define RTE_SPI0_DMA_EN 0 148 #define RTE_SPI1 0 149 #define RTE_SPI1_DMA_EN 0 150 #define RTE_SPI2 0 151 #define RTE_SPI2_DMA_EN 0 152 #define RTE_SPI3 0 153 #define RTE_SPI3_DMA_EN 0 154 155 /* SPI configuration. */ 156 #define RTE_SPI0_PCS_TO_SCK_DELAY 1000 157 #define RTE_SPI0_SCK_TO_PSC_DELAY 1000 158 #define RTE_SPI0_BETWEEN_TRANSFER_DELAY 1000 159 #define RTE_SPI0_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0 160 #define RTE_SPI0_SLAVE_PCS_PIN_SEL kLPSPI_SlavePcs0 161 #define RTE_SPI0_PIN_INIT SPI0_InitPins 162 #define RTE_SPI0_PIN_DEINIT SPI0_DeinitPins 163 #define RTE_SPI0_DMA_TX_CH 1 164 #define RTE_SPI0_DMA_TX_PERI_SEL 1 165 #define RTE_SPI0_DMA_TX_DMA_BASE ADMA__EDMA2 166 #define RTE_SPI0_DMA_RX_CH 0 167 #define RTE_SPI0_DMA_RX_PERI_SEL 0 168 #define RTE_SPI0_DMA_RX_DMA_BASE ADMA__EDMA2 169 170 #define RTE_SPI1_PCS_TO_SCK_DELAY 1000 171 #define RTE_SPI1_SCK_TO_PSC_DELAY 1000 172 #define RTE_SPI1_BETWEEN_TRANSFER_DELAY 1000 173 #define RTE_SPI1_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0 174 #define RTE_SPI1_SLAVE_PCS_PIN_SEL kLPSPI_SlavePcs0 175 #define RTE_SPI1_PIN_INIT SPI1_InitPins 176 #define RTE_SPI1_PIN_DEINIT SPI1_DeinitPins 177 #define RTE_SPI1_DMA_TX_CH 3 178 #define RTE_SPI1_DMA_TX_PERI_SEL 3 179 #define RTE_SPI1_DMA_TX_DMA_BASE ADMA__EDMA2 180 #define RTE_SPI1_DMA_RX_CH 2 181 #define RTE_SPI1_DMA_RX_PERI_SEL 2 182 #define RTE_SPI1_DMA_RX_DMA_BASE ADMA__EDMA2 183 184 #define RTE_SPI2_PCS_TO_SCK_DELAY 1000 185 #define RTE_SPI2_SCK_TO_PSC_DELAY 1000 186 #define RTE_SPI2_BETWEEN_TRANSFER_DELAY 1000 187 #define RTE_SPI2_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0 188 #define RTE_SPI2_SLAVE_PCS_PIN_SEL kLPSPI_SlavePcs0 189 #define RTE_SPI2_PIN_INIT SPI2_InitPins 190 #define RTE_SPI2_PIN_DEINIT SPI2_DeinitPins 191 #define RTE_SPI2_DMA_TX_CH 5 192 #define RTE_SPI2_DMA_TX_PERI_SEL 5 193 #define RTE_SPI2_DMA_TX_DMA_BASE ADMA__EDMA2 194 #define RTE_SPI2_DMA_RX_CH 4 195 #define RTE_SPI2_DMA_RX_PERI_SEL 4 196 #define RTE_SPI2_DMA_RX_DMA_BASE ADMA__EDMA2 197 198 #define RTE_SPI3_PCS_TO_SCK_DELAY 1000 199 #define RTE_SPI3_SCK_TO_PSC_DELAY 1000 200 #define RTE_SPI3_BETWEEN_TRANSFER_DELAY 1000 201 #define RTE_SPI3_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0 202 #define RTE_SPI3_SLAVE_PCS_PIN_SEL kLPSPI_SlavePcs0 203 #define RTE_SPI3_PIN_INIT SPI3_InitPins 204 #define RTE_SPI3_PIN_DEINIT SPI3_DeinitPins 205 #define RTE_SPI3_DMA_TX_CH 7 206 #define RTE_SPI3_DMA_TX_PERI_SEL 7 207 #define RTE_SPI3_DMA_TX_DMA_BASE ADMA__EDMA2 208 #define RTE_SPI3_DMA_RX_CH 6 209 #define RTE_SPI3_DMA_RX_PERI_SEL 6 210 #define RTE_SPI3_DMA_RX_DMA_BASE ADMA__EDMA2 211 212 /* ENET configuration. */ 213 #define RTE_ENET 1 214 #define RTE_ENET_PHY_ADDRESS 0 215 #define RTE_ENET_MII 0 216 #define RTE_ENET_RMII 1 217 #define RTE_ENET_RGMII 1 218 219 #endif /* _RTE_DEVICE_H */ 220
