1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2017-2020 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef _RTE_DEVICE_H 9 #define _RTE_DEVICE_H 10 11 #include "pin_mux.h" 12 13 /* UART Select, LPUART0 - LPUART6. */ 14 /* USART instance mapping */ 15 #define LPUART0 CM4_0__LPUART 16 #define LPUART1 CM4_1__LPUART 17 #define LPUART2 DMA__LPUART0 18 #define LPUART3 DMA__LPUART1 19 #define LPUART4 DMA__LPUART2 20 #define LPUART5 DMA__LPUART3 21 #define LPUART6 DMA__LPUART4 22 23 /* User needs to provide the implementation of LPUARTX_GetFreq/LPUARTX_InitPins/LPUARTX_DeinitPins for the enabled 24 * LPUART instance. */ 25 #define RTE_USART0 0 26 #define RTE_USART0_DMA_EN 0 27 #define RTE_USART1 0 28 #define RTE_USART1_DMA_EN 0 29 #define RTE_USART2 0 30 #define RTE_USART2_DMA_EN 0 31 #define RTE_USART3 0 32 #define RTE_USART3_DMA_EN 0 33 #define RTE_USART4 0 34 #define RTE_USART4_DMA_EN 0 35 #define RTE_USART5 0 36 #define RTE_USART5_DMA_EN 0 37 #define RTE_USART6 0 38 #define RTE_USART6_DMA_EN 0 39 40 /* UART configuration. */ 41 #define USART_RX_BUFFER_LEN 64 42 #define USART0_RX_BUFFER_ENABLE 0 43 #define USART1_RX_BUFFER_ENABLE 0 44 #define USART2_RX_BUFFER_ENABLE 0 45 #define USART3_RX_BUFFER_ENABLE 0 46 #define USART4_RX_BUFFER_ENABLE 0 47 #define USART5_RX_BUFFER_ENABLE 0 48 #define USART6_RX_BUFFER_ENABLE 0 49 50 /* Note: LPUART0, LPUART1 not support DMA mode */ 51 #define RTE_USART2_PIN_INIT LPUART2_InitPins 52 #define RTE_USART2_PIN_DEINIT LPUART2_DeinitPins 53 #define RTE_USART2_DMA_TX_CH 13 54 #define RTE_USART2_DMA_TX_PERI_SEL 13 55 #define RTE_USART2_DMA_TX_DMA_BASE DMA__DMA0 56 #define RTE_USART2_DMA_RX_CH 12 57 #define RTE_USART2_DMA_RX_PERI_SEL 12 58 #define RTE_USART2_DMA_RX_DMA_BASE DMA__DMA0 59 60 #define RTE_USART3_PIN_INIT LPUART3_InitPins 61 #define RTE_USART3_PIN_DEINIT LPUART3_DeinitPins 62 #define RTE_USART3_DMA_TX_CH 15 63 #define RTE_USART3_DMA_TX_PERI_SEL 15 64 #define RTE_USART3_DMA_TX_DMA_BASE DMA__DMA0 65 #define RTE_USART3_DMA_RX_CH 14 66 #define RTE_USART3_DMA_RX_PERI_SEL 14 67 #define RTE_USART3_DMA_RX_DMA_BASE DMA__DMA0 68 69 #define RTE_USART4_PIN_INIT LPUART4_InitPins 70 #define RTE_USART4_PIN_DEINIT LPUART4_DeinitPins 71 #define RTE_USART4_DMA_TX_CH 17 72 #define RTE_USART4_DMA_TX_PERI_SEL 17 73 #define RTE_USART4_DMA_TX_DMA_BASE DMA__DMA0 74 #define RTE_USART4_DMA_RX_CH 16 75 #define RTE_USART4_DMA_RX_PERI_SEL 16 76 #define RTE_USART4_DMA_RX_DMA_BASE DMA__DMA0 77 78 #define RTE_USART5_PIN_INIT LPUART5_InitPins 79 #define RTE_USART5_PIN_DEINIT LPUART5_DeinitPins 80 #define RTE_USART5_DMA_TX_CH 19 81 #define RTE_USART5_DMA_TX_PERI_SEL 19 82 #define RTE_USART5_DMA_TX_DMA_BASE DMA__DMA0 83 #define RTE_USART5_DMA_RX_CH 18 84 #define RTE_USART5_DMA_RX_PERI_SEL 18 85 #define RTE_USART5_DMA_RX_DMA_BASE DMA__DMA0 86 87 #define RTE_USART6_PIN_INIT LPUART6_InitPins 88 #define RTE_USART6_PIN_DEINIT LPUART6_DeinitPins 89 #define RTE_USART6_DMA_TX_CH 21 90 #define RTE_USART6_DMA_TX_PERI_SEL 21 91 #define RTE_USART6_DMA_TX_DMA_BASE DMA__DMA0 92 #define RTE_USART6_DMA_RX_CH 20 93 #define RTE_USART6_DMA_RX_PERI_SEL 20 94 #define RTE_USART6_DMA_RX_DMA_BASE DMA__DMA0 95 96 /* I2C Select, LPI2C0 - LPI2C6. */ 97 /* LPI2C instance mapping */ 98 #define LPI2C0 CM4_0__LPI2C 99 #define LPI2C1 CM4_1__LPI2C 100 #define LPI2C2 DMA__LPI2C0 101 #define LPI2C3 DMA__LPI2C1 102 #define LPI2C4 DMA__LPI2C2 103 #define LPI2C5 DMA__LPI2C3 104 #define LPI2C6 DMA__LPI2C4 105 106 /* User needs to provide the implementation of LPI2CX_GetFreq/LPI2CX_InitPins/LPI2CX_DeinitPins for the enabled LPI2C 107 * instance. */ 108 #define RTE_I2C0 0 109 #define RTE_I2C0_DMA_EN 0 110 #define RTE_I2C1 0 111 #define RTE_I2C1_DMA_EN 0 112 #define RTE_I2C2 0 113 #define RTE_I2C2_DMA_EN 0 114 #define RTE_I2C3 0 115 #define RTE_I2C3_DMA_EN 0 116 #define RTE_I2C4 0 117 #define RTE_I2C4_DMA_EN 0 118 #define RTE_I2C5 0 119 #define RTE_I2C5_DMA_EN 0 120 #define RTE_I2C6 0 121 #define RTE_I2C6_DMA_EN 0 122 123 /* LPI2C configuration. */ 124 /*Note: LPI2C0 and LPI2C1 not support DMA */ 125 #define RTE_I2C2_PIN_INIT LPI2C2_InitPins 126 #define RTE_I2C2_PIN_DEINIT LPI2C2_DeinitPins 127 #define RTE_I2C2_DMA_TX_CH 1 128 #define RTE_I2C2_DMA_TX_PERI_SEL 1 129 #define RTE_I2C2_DMA_TX_DMA_BASE DMA__DMA1 130 #define RTE_I2C2_DMA_RX_CH 0 131 #define RTE_I2C2_DMA_RX_PERI_SEL 0 132 #define RTE_I2C2_DMA_RX_DMA_BASE DMA__DMA1 133 134 #define RTE_I2C3_PIN_INIT LPI2C3_InitPins 135 #define RTE_I2C3_PIN_DEINIT LPI2C3_DeinitPins 136 #define RTE_I2C3_DMA_TX_CH 3 137 #define RTE_I2C3_DMA_TX_PERI_SEL 3 138 #define RTE_I2C3_DMA_TX_DMA_BASE DMA__DMA1 139 #define RTE_I2C3_DMA_RX_CH 2 140 #define RTE_I2C3_DMA_RX_PERI_SEL 2 141 #define RTE_I2C3_DMA_RX_DMA_BASE DMA__DMA1 142 143 #define RTE_I2C4_PIN_INIT LPI2C4_InitPins 144 #define RTE_I2C4_PIN_DEINIT LPI2C4_DeinitPins 145 #define RTE_I2C4_DMA_TX_CH 5 146 #define RTE_I2C4_DMA_TX_PERI_SEL 5 147 #define RTE_I2C4_DMA_TX_DMA_BASE DMA__DMA1 148 #define RTE_I2C4_DMA_RX_CH 4 149 #define RTE_I2C4_DMA_RX_PERI_SEL 4 150 #define RTE_I2C4_DMA_RX_DMA_BASE DMA__DMA1 151 152 #define RTE_I2C5_PIN_INIT LPI2C5_InitPins 153 #define RTE_I2C5_PIN_DEINIT LPI2C5_DeinitPins 154 #define RTE_I2C5_DMA_TX_CH 7 155 #define RTE_I2C5_DMA_TX_PERI_SEL 7 156 #define RTE_I2C5_DMA_TX_DMA_BASE DMA__DMA1 157 #define RTE_I2C5_DMA_RX_CH 6 158 #define RTE_I2C5_DMA_RX_PERI_SEL 6 159 #define RTE_I2C5_DMA_RX_DMA_BASE DMA__DMA1 160 161 #define RTE_I2C6_PIN_INIT LPI2C6_InitPins 162 #define RTE_I2C6_PIN_DEINIT LPI2C6_DeinitPins 163 #define RTE_I2C6_DMA_TX_CH 9 164 #define RTE_I2C6_DMA_TX_PERI_SEL 9 165 #define RTE_I2C6_DMA_TX_DMA_BASE DMA__DMA1 166 #define RTE_I2C6_DMA_RX_CH 8 167 #define RTE_I2C6_DMA_RX_PERI_SEL 8 168 #define RTE_I2C6_DMA_RX_DMA_BASE DMA__DMA1 169 170 /* SPI Select, LPSPI0 - LPSPI3. */ 171 #define LPSPI0 DMA__LPSPI0 172 #define LPSPI1 DMA__LPSPI1 173 #define LPSPI2 DMA__LPSPI2 174 #define LPSPI3 DMA__LPSPI3 175 176 /* User needs to provide the implementation of SPIX_GetFreq/SPIX_InitPins/SPIX_DeinitPins for the enabled SPI instance. 177 */ 178 #define RTE_SPI0 0 179 #define RTE_SPI0_DMA_EN 0 180 #define RTE_SPI1 0 181 #define RTE_SPI1_DMA_EN 0 182 #define RTE_SPI2 0 183 #define RTE_SPI2_DMA_EN 0 184 #define RTE_SPI3 0 185 #define RTE_SPI3_DMA_EN 0 186 187 /* SPI configuration. */ 188 #define RTE_SPI0_PCS_TO_SCK_DELAY 1000 189 #define RTE_SPI0_SCK_TO_PSC_DELAY 1000 190 #define RTE_SPI0_BETWEEN_TRANSFER_DELAY 1000 191 #define RTE_SPI0_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0 192 #define RTE_SPI0_PIN_INIT SPI0_InitPins 193 #define RTE_SPI0_PIN_DEINIT SPI0_DeinitPins 194 #define RTE_SPI0_DMA_TX_CH 1 195 #define RTE_SPI0_DMA_TX_PERI_SEL 1 196 #define RTE_SPI0_DMA_TX_DMA_BASE DMA__DMA0 197 #define RTE_SPI0_DMA_RX_CH 0 198 #define RTE_SPI0_DMA_RX_PERI_SEL 0 199 #define RTE_SPI0_DMA_RX_DMA_BASE DMA__DMA0 200 201 #define RTE_SPI1_PCS_TO_SCK_DELAY 1000 202 #define RTE_SPI1_SCK_TO_PSC_DELAY 1000 203 #define RTE_SPI1_BETWEEN_TRANSFER_DELAY 1000 204 #define RTE_SPI1_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0 205 #define RTE_SPI1_PIN_INIT SPI1_InitPins 206 #define RTE_SPI1_PIN_DEINIT SPI1_DeinitPins 207 #define RTE_SPI1_DMA_TX_CH 3 208 #define RTE_SPI1_DMA_TX_PERI_SEL 3 209 #define RTE_SPI1_DMA_TX_DMA_BASE DMA__DMA0 210 #define RTE_SPI1_DMA_RX_CH 2 211 #define RTE_SPI1_DMA_RX_PERI_SEL 2 212 #define RTE_SPI1_DMA_RX_DMA_BASE DMA__DMA0 213 214 #define RTE_SPI2_PCS_TO_SCK_DELAY 1000 215 #define RTE_SPI2_SCK_TO_PSC_DELAY 1000 216 #define RTE_SPI2_BETWEEN_TRANSFER_DELAY 1000 217 #define RTE_SPI2_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0 218 #define RTE_SPI2_PIN_INIT SPI2_InitPins 219 #define RTE_SPI2_PIN_DEINIT SPI2_DeinitPins 220 #define RTE_SPI2_DMA_TX_CH 5 221 #define RTE_SPI2_DMA_TX_PERI_SEL 5 222 #define RTE_SPI2_DMA_TX_DMA_BASE DMA__DMA0 223 #define RTE_SPI2_DMA_RX_CH 4 224 #define RTE_SPI2_DMA_RX_PERI_SEL 4 225 #define RTE_SPI2_DMA_RX_DMA_BASE DMA__DMA0 226 227 #define RTE_SPI3_PCS_TO_SCK_DELAY 1000 228 #define RTE_SPI3_SCK_TO_PSC_DELAY 1000 229 #define RTE_SPI3_BETWEEN_TRANSFER_DELAY 1000 230 #define RTE_SPI3_MASTER_PCS_PIN_SEL kLPSPI_MasterPcs0 231 #define RTE_SPI3_PIN_INIT SPI3_InitPins 232 #define RTE_SPI3_PIN_DEINIT SPI3_DeinitPins 233 #define RTE_SPI3_DMA_TX_CH 7 234 #define RTE_SPI3_DMA_TX_PERI_SEL 7 235 #define RTE_SPI3_DMA_TX_DMA_BASE DMA__DMA0 236 #define RTE_SPI3_DMA_RX_CH 6 237 #define RTE_SPI3_DMA_RX_PERI_SEL 6 238 #define RTE_SPI3_DMA_RX_DMA_BASE DMA__DMA0 239 240 /* ENET configuration. */ 241 #define RTE_ENET 1 242 #define RTE_ENET_PHY_ADDRESS 0 243 #define RTE_ENET_MII 0 244 #define RTE_ENET_RMII 1 245 #define RTE_ENET_RGMII 1 246 247 #endif /* _RTE_DEVICE_H */ 248
