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Searched refs:clockDivider (Results 1 – 10 of 10) sorted by relevance

/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/adc_5v12b_ll18_015/
Dfsl_adc.c81 …K(config->clockSource) | ADC_SC3_MODE(config->ResolutionMode) | ADC_SC3_ADIV(config->clockDivider); in ADC_Init()
132 config->clockDivider = kADC_ClockDivider1; in ADC_GetDefaultConfig()
Dfsl_adc.h108 adc_clock_divider_t clockDivider; /*!< Select the divider of input clock source. >*/ member
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/afe/
Dfsl_afe.c68 regData |= AFE_CKR_CLS(config->clockSource) | AFE_CKR_DIV(config->clockDivider); in AFE_Init()
123 config->clockDivider = kAFE_ClockDivider2; in AFE_GetDefaultConfig()
Dfsl_afe.h193 … afe_clock_divider_t clockDivider; /*!< Select the clock divider ration for the modulator clock. */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/capt/
Dfsl_capt.c93 tmp32 |= CAPT_CTRL_TRIGGER(config->triggerMode) | CAPT_CTRL_FDIV(config->clockDivider) | in CAPT_Init()
164 config->clockDivider = 15U; in CAPT_GetDefaultConfig()
Dfsl_capt.h171 …uint8_t clockDivider; /*!< Function clock divider. The function clock is divided by clockDivider+… member
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/adc16/
Dfsl_adc16.c81 tmp32 |= ADC_CFG1_ADIV(config->clockDivider); in ADC16_Init()
165 config->clockDivider = kADC16_ClockDivider8; in ADC16_GetDefaultConfig()
Dfsl_adc16.h193 …adc16_clock_divider_t clockDivider; /*!< Select the divider of input clock so… member
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/adc12/
Dfsl_adc12.c146 tmp32 |= (ADC_CFG1_ADICLK(config->clockSource) | ADC_CFG1_ADIV(config->clockDivider) | in ADC12_Init()
207 config->clockDivider = kADC12_ClockDivider1; in ADC12_GetDefaultConfig()
Dfsl_adc12.h115 …adc12_clock_divider_t clockDivider; /*!< Select the divider of input clock so… member