1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2020 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include "fsl_afe.h"
10
11 /* Component ID definition, used by tools. */
12 #ifndef FSL_COMPONENT_ID
13 #define FSL_COMPONENT_ID "platform.drivers.afe"
14 #endif
15
16 /*******************************************************************************
17 * Variables
18 ******************************************************************************/
19 /*! @brief Pointers to AFE bases for each instance. */
20 static AFE_Type *const s_AFEBases[] = AFE_BASE_PTRS;
21
22 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
23 /*! @brief Pointers to AFE clocks for each instance. */
24 static const clock_ip_name_t s_AFEClocks[] = AFE_CLOCKS;
25 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
26
27 /*******************************************************************************
28 * Code
29 *******************************************************************************/
AFE_GetInstance(AFE_Type * base)30 static uint32_t AFE_GetInstance(AFE_Type *base)
31 {
32 uint32_t instance;
33
34 /* Find the instance index from base address mappings. */
35 for (instance = 0; instance < ARRAY_SIZE(s_AFEBases); instance++)
36 {
37 if (s_AFEBases[instance] == base)
38 {
39 break;
40 }
41 }
42 assert(instance < ARRAY_SIZE(s_AFEBases));
43
44 return instance;
45 }
46
47 /*!
48 * brief Initialization for the AFE module.
49 *
50 * This function configures the AFE module for the configuration
51 * which are shared by all channels.
52 *
53 * param base AFE peripheral base address.
54 * param config Pointer to structure of "afe_config_t".
55 *
56 */
AFE_Init(AFE_Type * base,const afe_config_t * config)57 void AFE_Init(AFE_Type *base, const afe_config_t *config)
58 {
59 assert(config != NULL);
60
61 uint32_t regData = 0U;
62
63 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
64 /* Enable clock gate */
65 CLOCK_EnableClock(s_AFEClocks[AFE_GetInstance(base)]);
66 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
67 regData = base->CKR & ~(AFE_CKR_CLS_MASK | AFE_CKR_DIV_MASK); /* Clear old clock select, divider value */
68 regData |= AFE_CKR_CLS(config->clockSource) | AFE_CKR_DIV(config->clockDivider);
69 base->CKR = regData;
70
71 /* Clear old startup time, result format, low power mode value */
72 regData = base->CR & ~(AFE_CR_STRTUP_CNT_MASK | AFE_CR_RESULT_FORMAT_MASK | AFE_CR_RST_B_MASK | AFE_CR_LPM_EN_MASK);
73 /* Set new startup time, result format, low power mode value */
74 regData |= AFE_CR_STRTUP_CNT((uint8_t)config->startupCount) | AFE_CR_RESULT_FORMAT(config->resultFormat) |
75 AFE_CR_LPM_EN(config->enableLowPower);
76 /* Write value to CR register */
77 base->CR = regData;
78
79 AFE_Enable(base, true); /* Enable the AFE after the initialization. */
80 }
81
82 /*!
83 * brief De-Initialization for the AFE module.
84 *
85 * This function disables clock.
86 *
87 * param base AFE peripheral base address.
88 */
AFE_Deinit(AFE_Type * base)89 void AFE_Deinit(AFE_Type *base)
90 {
91 AFE_Enable(base, false); /* Disable the AFE module. */
92 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
93 /* Disable clock gate */
94 CLOCK_DisableClock(s_AFEClocks[AFE_GetInstance(base)]);
95 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
96 }
97
98 /*!
99 * brief Fills the user configure structure.
100 *
101 * This function fills the afe_config_t structure with default settings.
102 * Defaut value are:
103 * code
104 * config->enableLowPower = false;
105 * config->resultFormat = kAFE_ResultFormatRight;
106 * config->clockDivider = kAFE_ClockDivider2;
107 * config->clockSource = kAFE_ClockSource1;
108 * config->startupCount = 2U;
109 * endcode
110 *
111 * param config Pointer to structure of "afe_config_t".
112 */
AFE_GetDefaultConfig(afe_config_t * config)113 void AFE_GetDefaultConfig(afe_config_t *config)
114 {
115 assert(config != NULL);
116
117 /* Initializes the configure structure to zero. */
118 (void)memset(config, 0, sizeof(*config));
119
120 /* Fills the user configure structure. */
121 config->enableLowPower = false;
122 config->resultFormat = kAFE_ResultFormatRight;
123 config->clockDivider = kAFE_ClockDivider2;
124 config->clockSource = kAFE_ClockSource1;
125 /* Minimum value of startup time */
126 config->startupCount = 2U;
127 }
128
129 /*!
130 * brief Configure the selected AFE channel.
131 *
132 * This function configures the selected AFE channel.
133 *
134 * param base AFE peripheral base address.
135 * param channel AFE channel index.
136 * param config Pointer to structure of "afe_channel_config_t".
137 *
138 */
AFE_SetChannelConfig(AFE_Type * base,uint32_t channel,const afe_channel_config_t * config)139 void AFE_SetChannelConfig(AFE_Type *base, uint32_t channel, const afe_channel_config_t *config)
140 {
141 assert(config != NULL);
142 assert((uint8_t)channel < (uint8_t)FSL_FEATURE_AFE_CHANNEL_NUMBER);
143
144 uint32_t regData = 0U;
145
146 regData = base->CFR[channel];
147 /* Enable decimation filter. */
148 regData |= AFE_CFR_DEC_EN_MASK;
149 /* If bypass mode is enabled. */
150 if (config->channelMode != kAFE_BypassDisable)
151 {
152 regData &= ~(AFE_CFR_DEC_CLK_EDGE_SEL_MASK | AFE_CFR_DEC_CLK_INP_SEL_MASK);
153 regData |= (AFE_CFR_BYP_MODE_MASK | AFE_CFR_DEC_CLK_EDGE_SEL((((uint32_t)config->channelMode) >> 1UL) & 0x1UL) |
154 AFE_CFR_DEC_CLK_INP_SEL(((uint32_t)config->channelMode) & 0x1UL));
155 }
156 else
157 {
158 regData |= AFE_CFR_SD_MOD_EN_MASK;
159 if (config->pgaGainSelect == kAFE_PgaDisable)
160 {
161 regData &= ~AFE_CFR_PGA_EN_MASK; /* PGA is disabled. */
162 }
163 else
164 {
165 /* Set PGA value*/
166 regData &= ~AFE_CFR_PGA_GAIN_SEL_MASK;
167 regData |= (AFE_CFR_PGA_EN_MASK | AFE_CFR_PGA_GAIN_SEL(config->pgaGainSelect));
168 }
169 }
170 /* Clear old Decimator OverSample Ratio, Conversion Mode, Trigger Select value */
171 regData &= ~(AFE_CFR_DEC_OSR_MASK | AFE_CFR_HW_TRG_MASK | AFE_CFR_CC_MASK);
172 /* Set new Decimator OverSampling Ratio, Conversion Mode, Trigger Select value */
173 regData |= AFE_CFR_DEC_OSR((uint32_t)config->decimatorOversampleRatio) |
174 AFE_CFR_CC(config->enableContinuousConversion) | AFE_CFR_HW_TRG(config->enableHardwareTrigger);
175
176 base->CFR[channel] = regData;
177 }
178
179 /*!
180 * brief Fills the channel configuration structure.
181 *
182 * This function fills the afe_channel_config_t structure with default settings.
183 * Default value are:
184 * code
185 * config->enableHardwareTrigger = false;
186 * config->enableContinuousConversion = false;
187 * config->channelMode = kAFE_Normal;
188 * config->decimatorOversampleRatio = kAFE_DecimatorOversampleRatio64;
189 * config->pgaGainSelect = kAFE_PgaGain1;
190 * endcode
191 *
192 * param config Pointer to structure of "afe_channel_config_t".
193 */
AFE_GetDefaultChannelConfig(afe_channel_config_t * config)194 void AFE_GetDefaultChannelConfig(afe_channel_config_t *config)
195 {
196 assert(config != NULL);
197
198 /* Initializes the configure structure to zero. */
199 (void)memset(config, 0, sizeof(*config));
200
201 /* Fills the channel configuration structure. */
202 config->enableHardwareTrigger = false;
203 config->enableContinuousConversion = false;
204 config->channelMode = kAFE_BypassDisable;
205 config->decimatorOversampleRatio = kAFE_DecimatorOversampleRatio64;
206 config->pgaGainSelect = kAFE_PgaDisable;
207 }
208
209 /*!
210 * brief Reads the raw conversion value.
211 *
212 * This function returns the raw conversion value of the selected channel.
213 *
214 * param base AFE peripheral base address.
215 * param channel AFE channel index.
216 * return Conversion value.
217 * note The returned value could be left or right adjusted according to the AFE module configuration.
218 */
AFE_GetChannelConversionValue(AFE_Type * base,uint32_t channel)219 uint32_t AFE_GetChannelConversionValue(AFE_Type *base, uint32_t channel)
220 {
221 assert((uint8_t)channel < (uint8_t)FSL_FEATURE_AFE_CHANNEL_NUMBER);
222
223 return base->RR[channel];
224 }
225
226 /*!
227 * brief Sets phase delays value.
228 *
229 * This function sets the phase delays for channels. This delay is inserted before
230 * the trigger response of the decimation filters. The delay is used to provide
231 * a phase compensation between AFE channels in step of prescaled modulator clock
232 * periods.
233 * param base AFE peripheral base address.
234 * param channel AFE channel index.
235 * param value delay time value.
236 */
AFE_SetChannelPhaseDelayValue(AFE_Type * base,uint32_t channel,uint32_t value)237 void AFE_SetChannelPhaseDelayValue(AFE_Type *base, uint32_t channel, uint32_t value)
238 {
239 assert((uint8_t)channel < (uint8_t)FSL_FEATURE_AFE_CHANNEL_NUMBER);
240
241 /* Set delay value for this channel */
242 base->DR[channel] = AFE_DR_DLY(value);
243 }
244
245 /*!
246 * brief Enables/Disables AFE DMA.
247 *
248 * This function enables/disables one channel DMA request.
249 *
250 * param base AFE peripheral base address.
251 * param mask AFE channel dma mask.
252 * param enable Pass true to enable interrupt, false to disable.
253 * The parameter can be combination of the following source if defined:
254 * arg kAFE_Channel0DMAEnable
255 * arg kAFE_Channel1DMAEnable
256 * arg kAFE_Channel2DMAEnable
257 * arg kAFE_Channel3DMAEnable
258 */
AFE_EnableChannelDMA(AFE_Type * base,uint32_t mask,bool enable)259 void AFE_EnableChannelDMA(AFE_Type *base, uint32_t mask, bool enable)
260 {
261 uint32_t regData = mask & ((uint32_t)kAFE_Channel0DMAEnable | (uint32_t)kAFE_Channel1DMAEnable |
262 (uint32_t)kAFE_Channel2DMAEnable | (uint32_t)kAFE_Channel3DMAEnable);
263
264 if (enable)
265 {
266 base->DI |= regData;
267 }
268 else
269 {
270 base->DI &= ~regData;
271 }
272 }
273
