Searched refs:SRAM2 (Results 1 – 25 of 47) sorted by relevance
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| /Zephyr-latest/tests/application_development/code_relocation/ |
| D | CMakeLists.txt | 18 zephyr_code_relocate(FILES src/test_file1.c ${SRAM2_PHDR} LOCATION SRAM2)
27 zephyr_code_relocate(LIBRARY test_lib LOCATION SRAM2)
33 zephyr_code_relocate(FILES ${genex_expr} LOCATION SRAM2)
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| D | linker_xtensa_qemu_sram2.ld | 18 SRAM2 (wx) : ORIGIN = (CONFIG_SRAM_BASE_ADDRESS + RAM_SIZE2), LENGTH = RAM_SIZE2
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| D | linker_riscv_qemu_sram2.ld | 24 … SRAM2 (wx) : ORIGIN = (CONFIG_SRAM_BASE_ADDRESS + RAM_SIZE2), LENGTH = RAM_SIZE2
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| D | linker_arm_sram2.ld | 35 … SRAM2 (wx) : ORIGIN = (CONFIG_SRAM_BASE_ADDRESS + RAM_SIZE2), LENGTH = RAM_SIZE2
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| /Zephyr-latest/samples/subsys/display/lvgl/boards/ |
| D | max32662evkit.overlay | 14 * Concatenate SRAM0(16KB), SRAM1(16KB) and SRAM2(16KB)
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| /Zephyr-latest/doc/kernel/ |
| D | code-relocation.rst | 22 ``SRAM2:/home/xyz/zephyr/samples/hello_world/src/main.c,SRAM1:/home/xyz/zephyr/samples/hello_world/…
57 ``zephyr_code_relocate(FILES src/*.c LOCATION SRAM2)``
71 * if the memory is SRAM1, SRAM2, CCD, or AON, then place the full object in the
76 zephyr_code_relocate(FILES src/file1.c LOCATION SRAM2)
89 This will place data and bss inside SRAM2.
114 sections of ``file1.c`` will not stick to SRAM2.
138 snippet will relocate serial drivers to SRAM2:
142 zephyr_code_relocate(LIBRARY drivers__serial LOCATION SRAM2)
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| /Zephyr-latest/dts/arm/st/u5/ |
| D | stm32u575Xi.dtsi | 11 /* SRAM1 + SRAM2 + SRAM3 */
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| D | stm32u585Xi.dtsi | 11 /* SRAM1 + SRAM2 + SRAM3 */
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| D | stm32u5a5Xj.dtsi | 12 /* SRAM1 + SRAM2 + SRAM3 + SRAM5 */
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| D | stm32u599Xj.dtsi | 11 /* SRAM1 + SRAM2 + SRAM3 + SRAM5 */
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| D | stm32u545Xi.dtsi | 11 /* SRAM1 + SRAM2 */
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| D | stm32u5a9Xj.dtsi | 12 /* SRAM1 + SRAM2 + SRAM3 + SRAM5 */
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| /Zephyr-latest/samples/boards/intel/adsp/code_relocation/ |
| D | linker_xtensa_intel_adsp_cavs.ld | 13 /* Use SRAM2 for TEXT, SRAM3 for DATA and SRAM4 for BSS.
18 * |Reserved | SRAM4 | SRAM2 | SRAM0 | SRAM3 |
44 SRAM2 (wx) : ORIGIN = (SRAM2_ADDR), LENGTH = RAM_SIZE2
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| /Zephyr-latest/dts/arm/nxp/ |
| D | nxp_lpc55S36_ns.dtsi | 23 * Combine SRAM0, SRAM1, SRAM2, SRAM3, SRAM4 for total of 112K RAM
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| D | nxp_lpc55S06_ns.dtsi | 33 * Combine SRAM0, SRAM1, SRAM2 for total of 80K RAM
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| D | nxp_lpc54xxx.dtsi | 56 * LPC540xx: RAMX: 192K, SRAM0: 64K, SRAM1: 32K, SRAM2: 32K, SRAM3: 32K, USBRAM: 8K
58 * LPC5411x: RAMX: 32K, SRAM0: 64K, SRAM1: 64K, SRAM2: 32K
79 zephyr,memory-region = "SRAM2";
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| /Zephyr-latest/tests/drivers/spi/spi_loopback/boards/ |
| D | max32662evkit.overlay | 7 /* Increase SRAM2 size to get enough space for image */
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| /Zephyr-latest/dts/arm/st/u0/ |
| D | stm32u031X4.dtsi | 20 zephyr,memory-region = "SRAM2";
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| D | stm32u031X6.dtsi | 20 zephyr,memory-region = "SRAM2";
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| D | stm32u031X8.dtsi | 20 zephyr,memory-region = "SRAM2";
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| D | stm32u083Xc.dtsi | 20 zephyr,memory-region = "SRAM2";
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| /Zephyr-latest/soc/nxp/lpc/lpc54xxx/ |
| D | CMakeLists.txt | 17 # CMSIS SystemInit allows us to skip enabling clock to SRAM2 bank via
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| D | Kconfig | 62 bool "Clock LPC54XXX SRAM2"
65 SRAM2 ram bank is disabled out of reset. By default, CMSIS SystemInit
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| /Zephyr-latest/dts/arm/st/h5/ |
| D | stm32h533Xe.dtsi | 19 zephyr,memory-region = "SRAM2";
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| /Zephyr-latest/dts/arm/st/h7/ |
| D | stm32h7a3.dtsi | 118 /* System data RAM accessible over AXI bus: AXI SRAM2 in CD domain */
129 zephyr,memory-region = "SRAM2";
139 /* System data RAM accessible over AHB bus: SRAM2 in CD domain */
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