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Searched refs:PLLLSR (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Pll.c436 …PllEnableStatus = ((Clock_Ip_apxLfastPll[Instance].PllInstance->PLLLSR & LFAST_PLLLSR_PLLDIS_MASK)… in Clock_Ip_CompleteLfastPLL()
450 …PllLockStatus = ((Clock_Ip_apxLfastPll[Instance].PllInstance->PLLLSR & LFAST_PLLLSR_PLDCR_MASK) >>… in Clock_Ip_CompleteLfastPLL()
DClock_Ip_Frequency.c4048 … return (((Base->PLLLSR & LFAST_PLLLSR_PLDCR_MASK) >> LFAST_PLLLSR_PLDCR_SHIFT) == 1U) ? Fout : 0U; in LFAST_PLL_VCO()
4095 …return (((IP_LFAST_0->PLLLSR & LFAST_PLLLSR_PLDCR_MASK) >> LFAST_PLLLSR_PLDCR_SHIFT) == 1U) ? LFAS… in Clock_Ip_Get_LFAST0_PLL_CLK_Frequency()
4100 …return (((IP_LFAST_1->PLLLSR & LFAST_PLLLSR_PLDCR_MASK) >> LFAST_PLLLSR_PLDCR_SHIFT) == 1U) ? LFAS… in Clock_Ip_Get_LFAST1_PLL_CLK_Frequency()
/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_LFAST.h104 …__I uint32_t PLLLSR; /**< LFAST PLL and LVDS Status Register, offset: … member