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Searched refs:PLLDIG_PLLODIV_DE_MASK (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_PLLDIG.h209 #define PLLDIG_PLLODIV_DE_MASK (0x80000000U) macro
212 … (((uint32_t)(((uint32_t)(x)) << PLLDIG_PLLODIV_DE_SHIFT)) & PLLDIG_PLLODIV_DE_MASK)
/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Divider.c273 …V_ASSERT(!(Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] & PLLDIG_PLLODIV_DE_MASK)); in Clock_Ip_SetPlldigPll0divDeDivOutput()
279 RegValue |= PLLDIG_PLLODIV_DE_MASK; in Clock_Ip_SetPlldigPll0divDeDivOutput()
DClock_Ip_Pll.c176 Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] &= ~PLLDIG_PLLODIV_DE_MASK; in Clock_Ip_ResetPlldigRdivMfiMfnSdmenSsscgbypSpreadctlStepnoStepsize()
286 Clock_Ip_apxPll[Instance].PllInstance->PLLODIV[DividerIndex] &= ~PLLDIG_PLLODIV_DE_MASK; in Clock_Ip_ResetPlldigRdivMfiMfnSdmen()
DClock_Ip_Frequency.c1414 …Frequency &= Clock_Ip_au32EnableDivider[((IP_CORE_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DE_MASK) >> PL… in Clock_Ip_Get_COREPLL_PHI0_Frequency()
1483 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DE_MASK) >> … in Clock_Ip_Get_PERIPHPLL_PHI0_Frequency()
1492 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[1U] & PLLDIG_PLLODIV_DE_MASK) >> … in Clock_Ip_Get_PERIPHPLL_PHI1_Frequency()
1500 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[2U] & PLLDIG_PLLODIV_DE_MASK) >> … in Clock_Ip_Get_PERIPHPLL_PHI2_Frequency()
1508 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[3U] & PLLDIG_PLLODIV_DE_MASK) >> … in Clock_Ip_Get_PERIPHPLL_PHI3_Frequency()
1516 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[4U] & PLLDIG_PLLODIV_DE_MASK) >> … in Clock_Ip_Get_PERIPHPLL_PHI4_Frequency()
1524 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[5U] & PLLDIG_PLLODIV_DE_MASK) >> … in Clock_Ip_Get_PERIPHPLL_PHI5_Frequency()
1532 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[6U] & PLLDIG_PLLODIV_DE_MASK) >> … in Clock_Ip_Get_PERIPHPLL_PHI6_Frequency()
1601 …Frequency &= Clock_Ip_au32EnableDivider[((IP_DDR_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DE_MASK) >> PLL… in Clock_Ip_Get_DDRPLL_PHI0_Frequency()