Searched refs:Mfn (Results 1 – 2 of 2) sorted by relevance
3993 uint32 Mfn; in Clock_Ip_PLL_VCO() local4009 Mfn = ((Base->PLLFD & PLL_PLLFD_MFN_MASK) >> PLL_PLLFD_MFN_SHIFT); /* Mfn */ in Clock_Ip_PLL_VCO()4015 Mfn = 0; in Clock_Ip_PLL_VCO()4046 if ((Mfn == ((uint32)(Var4 * Mfn) / Var4)) && (CLOCK_IP_PLL_VCO_MAX_FREQ >= Fout)) in Clock_Ip_PLL_VCO()4048 Fout += Var4 * Mfn; /* Mfn multiplied by Var4 */ in Clock_Ip_PLL_VCO()4056 if (0U != Mfn) in Clock_Ip_PLL_VCO()4058 if ((Var5 == ((uint32)(Var5 * Mfn) / Mfn)) && (CLOCK_IP_PLL_VCO_MAX_FREQ >= Fout)) in Clock_Ip_PLL_VCO()4060 …Fout += Var5 * Mfn / Var3; /* Var5 multiplied by Mfn and divide by (R… in Clock_Ip_PLL_VCO()
3995 uint32 Mfn; in PLL_VCO() local4005 … Mfn = ((Base->PLLFD & PLLDIG_PLLFD_MFN_MASK) >> PLLDIG_PLLFD_MFN_SHIFT); /* Mfn */ in PLL_VCO()4016 Fout += Var4 * Mfn; /* Mfn multiplied by Var4 */ in PLL_VCO()4017 …Fout += Var5 * Mfn / Var3; /* Var5 multiplied by Mfn and divide by (R… in PLL_VCO()4055 uint32 Mfn; in DFS_OUTPUT() local4061 …Mfn = ((Base->DVPORT[Channel] & DFS_DVPORT_MFN_MASK) >> DFS_DVPORT_MFN_SHIFT); /* Mfn… in DFS_OUTPUT()4063 …Divider = ((Mfi << CLOCK_IP_MUL_BY_32) + (Mfi << CLOCK_IP_MUL_BY_4) + Mfn); /* mfi m… in DFS_OUTPUT()
