Searched refs:MUX_9_DC_0 (Results 1 – 4 of 4) sorted by relevance
2380 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_9_DC_0 & MC_CGM_MUX_9_DC_0_DE_MASK) >> … in Clock_Ip_Get_CTU_CLK_Frequency()2381 …Frequency /= (((IP_MC_CGM_0->MUX_9_DC_0 & MC_CGM_MUX_9_DC_0_DIV_MASK) >> MC_CGM_MUX_9_DC_0_DIV_SHI… in Clock_Ip_Get_CTU_CLK_Frequency()2956 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_9_DC_0 & MC_CGM_MUX_9_DC_0_DE_MASK) >> … in Clock_Ip_Get_P0_CTU_PER_CLK_Frequency()2957 …Frequency /= (((IP_MC_CGM_0->MUX_9_DC_0 & MC_CGM_MUX_9_DC_0_DIV_MASK) >> MC_CGM_MUX_9_DC_0_DIV_SHI… in Clock_Ip_Get_P0_CTU_PER_CLK_Frequency()3257 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_9_DC_0 & MC_CGM_MUX_9_DC_0_DE_MASK) >> … in Clock_Ip_Get_ETH1_RX_MII_CLK_Frequency()3258 …Frequency /= (((IP_MC_CGM_1->MUX_9_DC_0 & MC_CGM_MUX_9_DC_0_DIV_MASK) >> MC_CGM_MUX_9_DC_0_DIV_SHI… in Clock_Ip_Get_ETH1_RX_MII_CLK_Frequency()3826 …Frequency /= (((IP_MC_CGM_4->MUX_9_DC_0 & MC_CGM_MUX_9_DC_0_DIV_MASK) >> MC_CGM_MUX_9_DC_0_DIV_SHI… in Clock_Ip_Get_P4_SDHC_CLK_Frequency()3836 …Frequency /= (((IP_MC_CGM_4->MUX_9_DC_0 & MC_CGM_MUX_9_DC_0_DIV_MASK) >> MC_CGM_MUX_9_DC_0_DIV_SHI… in Clock_Ip_Get_SDHC0_CLK_Frequency()
2855 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_9_DC_0 & MC_CGM_MUX_9_DC_0_DE_MASK) >> MC… in Clock_Ip_Get_EMAC_TS_CLK_Frequency()2856 …Frequency /= (((IP_MC_CGM->MUX_9_DC_0 & MC_CGM_MUX_9_DC_0_DIV_MASK) >> MC_CGM_MUX_9_DC_0_DIV_SHIFT… in Clock_Ip_Get_EMAC_TS_CLK_Frequency()3729 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_9_DC_0 & MC_CGM_MUX_9_DC_0_DE_MASK) >> MC… in Clock_Ip_Get_GMAC_TS_CLK_Frequency()3730 …Frequency /= (((IP_MC_CGM->MUX_9_DC_0 & MC_CGM_MUX_9_DC_0_DIV_MASK) >> MC_CGM_MUX_9_DC_0_DIV_SHIFT… in Clock_Ip_Get_GMAC_TS_CLK_Frequency()
134 …__IO uint32_t MUX_9_DC_0; /**< Clock Mux 9 Divider 0 Control Register, offs… member
156 …__IO uint32_t MUX_9_DC_0; /**< Clock Mux 9 Divider 0 Control Register, offs… member
