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Searched refs:MUX_6_DC_0 (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Frequency.c1656 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DE_MASK) >> … in Clock_Ip_Get_P0_FR_PE_CLK_Frequency()
1657 …Frequency /= (((IP_MC_CGM_0->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHI… in Clock_Ip_Get_P0_FR_PE_CLK_Frequency()
1665 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DE_MASK) >> … in Clock_Ip_Get_FRAY0_CLK_Frequency()
1666 …Frequency /= (((IP_MC_CGM_0->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHI… in Clock_Ip_Get_FRAY0_CLK_Frequency()
1675 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DE_MASK) >> … in Clock_Ip_Get_FRAY1_CLK_Frequency()
1676 …Frequency /= (((IP_MC_CGM_0->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHI… in Clock_Ip_Get_FRAY1_CLK_Frequency()
2513 …Frequency /= (((IP_MC_CGM_4->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHI… in Clock_Ip_Get_CLKOUT2_CLK_Frequency()
2612 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DE_MASK) >> … in Clock_Ip_Get_ETH0_TX_MII_CLK_Frequency()
2613 …Frequency /= (((IP_MC_CGM_1->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHI… in Clock_Ip_Get_ETH0_TX_MII_CLK_Frequency()
2623 …Frequency /= (((IP_MC_CGM_1->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHI… in Clock_Ip_Get_ENET0_CLK_Frequency()
/hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/header/
DS32K344_MC_CGM.h119 …__IO uint32_t MUX_6_DC_0; /**< Clock Mux 6 Divider 0 Control Register, offs… member
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Frequency.c2004 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DE_MASK) >> MC… in Clock_Ip_Get_CLKOUT_RUN_CLK_Frequency()
2005 …Frequency /= (((IP_MC_CGM->MUX_6_DC_0 & MC_CGM_MUX_6_DC_0_DIV_MASK) >> MC_CGM_MUX_6_DC_0_DIV_SHIFT… in Clock_Ip_Get_CLKOUT_RUN_CLK_Frequency()
/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_MC_CGM.h135 …__IO uint32_t MUX_6_DC_0; /**< Clock Mux 6 Divider 0 Control Register, offs… member