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Searched refs:MUX_5_DC_0 (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Frequency.c3177 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_5_DC_0 & MC_CGM_MUX_5_DC_0_DE_MASK) >> … in Clock_Ip_Get_ETH_TS_CLK_Frequency()
3178 …Frequency /= (((IP_MC_CGM_1->MUX_5_DC_0 & MC_CGM_MUX_5_DC_0_DIV_MASK) >> MC_CGM_MUX_5_DC_0_DIV_SHI… in Clock_Ip_Get_ETH_TS_CLK_Frequency()
3187 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_5_DC_0 & MC_CGM_MUX_5_DC_0_DE_MASK) >> … in Clock_Ip_Get_ETH_TS_DIV4_CLK_Frequency()
3188 …Frequency /= ((((IP_MC_CGM_1->MUX_5_DC_0 & MC_CGM_MUX_5_DC_0_DIV_MASK) >> MC_CGM_MUX_5_DC_0_DIV_SH… in Clock_Ip_Get_ETH_TS_DIV4_CLK_Frequency()
3637 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_5_DC_0 & MC_CGM_MUX_5_DC_0_DE_MASK) >> … in Clock_Ip_Get_P5_AE_CLK_Frequency()
3638 …Frequency /= (((IP_MC_CGM_5->MUX_5_DC_0 & MC_CGM_MUX_5_DC_0_DIV_MASK) >> MC_CGM_MUX_5_DC_0_DIV_SHI… in Clock_Ip_Get_P5_AE_CLK_Frequency()
/hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/header/
DS32K344_MC_CGM.h114 …__IO uint32_t MUX_5_DC_0; /**< Clock Mux 5 Divider 0 Control Register, offs… member
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Frequency.c2142 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_5_DC_0 & MC_CGM_MUX_5_DC_0_DE_MASK) >> MC… in Clock_Ip_Get_CLKOUT_STANDBY_CLK_Frequency()
2143 …Frequency /= (((IP_MC_CGM->MUX_5_DC_0 & MC_CGM_MUX_5_DC_0_DIV_MASK) >> MC_CGM_MUX_5_DC_0_DIV_SHIFT… in Clock_Ip_Get_CLKOUT_STANDBY_CLK_Frequency()
/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_MC_CGM.h128 …__IO uint32_t MUX_5_DC_0; /**< Clock Mux 5 Divider 0 Control Register, offs… member