Searched refs:MUX_4_DC_0 (Results 1 – 4 of 4) sorted by relevance
1697 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DE_MASK) >> … in Clock_Ip_Get_P0_LIN_BAUD_CLK_Frequency()1698 …Frequency /= (((IP_MC_CGM_0->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHI… in Clock_Ip_Get_P0_LIN_BAUD_CLK_Frequency()1706 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DE_MASK) >> … in Clock_Ip_Get_LIN0_CLK_Frequency()1707 …Frequency /= (((IP_MC_CGM_0->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHI… in Clock_Ip_Get_LIN0_CLK_Frequency()1716 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DE_MASK) >> … in Clock_Ip_Get_LIN1_CLK_Frequency()1717 …Frequency /= (((IP_MC_CGM_0->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHI… in Clock_Ip_Get_LIN1_CLK_Frequency()1726 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DE_MASK) >> … in Clock_Ip_Get_LIN2_CLK_Frequency()1727 …Frequency /= (((IP_MC_CGM_0->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHI… in Clock_Ip_Get_LIN2_CLK_Frequency()1736 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DE_MASK) >> … in Clock_Ip_Get_P1_LIN_BAUD_CLK_Frequency()1737 …Frequency /= (((IP_MC_CGM_1->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHI… in Clock_Ip_Get_P1_LIN_BAUD_CLK_Frequency()[all …]
109 …__IO uint32_t MUX_4_DC_0; /**< Clock Mux 4 Divider 0 Control Register, offs… member
3039 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DE_MASK) >> MC… in Clock_Ip_Get_FLEXCANB_CLK_Frequency()3040 …Frequency /= (((IP_MC_CGM->MUX_4_DC_0 & MC_CGM_MUX_4_DC_0_DIV_MASK) >> MC_CGM_MUX_4_DC_0_DIV_SHIFT… in Clock_Ip_Get_FLEXCANB_CLK_Frequency()
123 …__IO uint32_t MUX_4_DC_0; /**< Clock Mux 4 Divider 0 Control Register, offs… member