Searched refs:MUX_3_DC_0 (Results 1 – 4 of 4) sorted by relevance
1897 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DE_MASK) >> … in Clock_Ip_Get_P0_PSI5_S_TRIG0_CLK_Frequency()1898 …Frequency /= (((IP_MC_CGM_0->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHI… in Clock_Ip_Get_P0_PSI5_S_TRIG0_CLK_Frequency()2632 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DE_MASK) >> … in Clock_Ip_Get_P3_CAN_PE_CLK_Frequency()2633 …Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHI… in Clock_Ip_Get_P3_CAN_PE_CLK_Frequency()2643 …Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHI… in Clock_Ip_Get_FLEXCAN0_CLK_Frequency()2653 …Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHI… in Clock_Ip_Get_FLEXCAN1_CLK_Frequency()2663 …Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHI… in Clock_Ip_Get_FLEXCAN2_CLK_Frequency()2673 …Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHI… in Clock_Ip_Get_FLEXCAN3_CLK_Frequency()2683 …Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHI… in Clock_Ip_Get_FLEXCAN4_CLK_Frequency()2693 …Frequency /= (((IP_MC_CGM_3->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHI… in Clock_Ip_Get_FLEXCAN5_CLK_Frequency()[all …]
104 …__IO uint32_t MUX_3_DC_0; /**< Clock Mux 3 Divider 0 Control Register, offs… member
3013 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DE_MASK) >> MC… in Clock_Ip_Get_FLEXCANA_CLK_Frequency()3014 …Frequency /= (((IP_MC_CGM->MUX_3_DC_0 & MC_CGM_MUX_3_DC_0_DIV_MASK) >> MC_CGM_MUX_3_DC_0_DIV_SHIFT… in Clock_Ip_Get_FLEXCANA_CLK_Frequency()
111 …__IO uint32_t MUX_3_DC_0; /**< Clock Mux 3 Divider 0 Control Register, offs… member
