MUX_2_DC_0 (reference) in projects: hal_nxp-3.5.0

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Searched refs:MUX_2_DC_0 (Results 1 – 4 of 4) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
D	Clock_Ip_Frequency.c	1775 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DE_MASK) >> … in Clock_Ip_Get_LIN9_CLK_Frequency() 1776 …Frequency /= (((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DIV_MASK) >> MC_CGM_MUX_2_DC_0_DIV_SHI… in Clock_Ip_Get_LIN9_CLK_Frequency() 1785 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DE_MASK) >> … in Clock_Ip_Get_LIN10_CLK_Frequency() 1786 …Frequency /= (((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DIV_MASK) >> MC_CGM_MUX_2_DC_0_DIV_SHI… in Clock_Ip_Get_LIN10_CLK_Frequency() 1795 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DE_MASK) >> … in Clock_Ip_Get_LIN11_CLK_Frequency() 1796 …Frequency /= (((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DIV_MASK) >> MC_CGM_MUX_2_DC_0_DIV_SHI… in Clock_Ip_Get_LIN11_CLK_Frequency() 1836 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DE_MASK) >> … in Clock_Ip_Get_P5_LIN_BAUD_CLK_Frequency() 1837 …Frequency /= (((IP_MC_CGM_5->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DIV_MASK) >> MC_CGM_MUX_2_DC_0_DIV_SHI… in Clock_Ip_Get_P5_LIN_BAUD_CLK_Frequency() 1877 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_0->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DE_MASK) >> … in Clock_Ip_Get_P0_PSI5_1US_CLK_Frequency() 1878 …Frequency /= (((IP_MC_CGM_0->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DIV_MASK) >> MC_CGM_MUX_2_DC_0_DIV_SHI… in Clock_Ip_Get_P0_PSI5_1US_CLK_Frequency() [all …]
/hal_nxp-3.5.0/s32/drivers/s32k3/BaseNXP/header/
D	S32K344_MC_CGM.h	`99 …__IO uint32_t MUX_2_DC_0; /**< Clock Mux 2 Divider 0 Control Register, offs… member`
/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/src/
D	Clock_Ip_Frequency.c	`3656 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DE_MASK) >> MC… in Clock_Ip_Get_STMB_CLK_Frequency() 3657 …Frequency /= (((IP_MC_CGM->MUX_2_DC_0 & MC_CGM_MUX_2_DC_0_DIV_MASK) >> MC_CGM_MUX_2_DC_0_DIV_SHIFT… in Clock_Ip_Get_STMB_CLK_Frequency()`
/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
D	S32Z2_MC_CGM.h	`101 …__IO uint32_t MUX_2_DC_0; /**< Clock Mux 2 Divider 0 Control Register, offs… member`

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TraceRecorderSource-3.4.0
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