Searched refs:MUX_14_DC_0 (Results 1 – 3 of 3) sorted by relevance
3690 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_14_DC_0 & MC_CGM_MUX_14_DC_0_DE_MASK) >> … in Clock_Ip_Get_USDHC_CLK_Frequency()3691 …Frequency /= (((IP_MC_CGM->MUX_14_DC_0 & MC_CGM_MUX_14_DC_0_DIV_MASK) >> MC_CGM_MUX_14_DC_0_DIV_SH… in Clock_Ip_Get_USDHC_CLK_Frequency()
181 …__IO uint32_t MUX_14_DC_0; /**< Clock Mux 14 Divider 0 Control Register, off… member
3325 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_14_DC_0 & MC_CGM_MUX_14_DC_0_DE_MASK) >… in Clock_Ip_Get_P1_NETC_AXI_CLK_Frequency()3326 …Frequency /= (((IP_MC_CGM_1->MUX_14_DC_0 & MC_CGM_MUX_14_DC_0_DIV_MASK) >> MC_CGM_MUX_14_DC_0_DIV_… in Clock_Ip_Get_P1_NETC_AXI_CLK_Frequency()