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Searched refs:MUX_12_DC_0 (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32k3/Mcu/src/
DClock_Ip_Frequency.c2889 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_12_DC_0 & MC_CGM_MUX_12_DC_0_DE_MASK) >> … in Clock_Ip_Get_EMAC_TX_RMII_CLK_Frequency()
2890 …Frequency /= (((IP_MC_CGM->MUX_12_DC_0 & MC_CGM_MUX_12_DC_0_DIV_MASK) >> MC_CGM_MUX_12_DC_0_DIV_SH… in Clock_Ip_Get_EMAC_TX_RMII_CLK_Frequency()
3739 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_12_DC_0 & MC_CGM_MUX_12_DC_0_DE_MASK) >> … in Clock_Ip_Get_GMAC0_TX_RMII_CLK_Frequency()
3740 …Frequency /= (((IP_MC_CGM->MUX_12_DC_0 & MC_CGM_MUX_12_DC_0_DIV_MASK) >> MC_CGM_MUX_12_DC_0_DIV_SH… in Clock_Ip_Get_GMAC0_TX_RMII_CLK_Frequency()
/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_MC_CGM.h173 …__IO uint32_t MUX_12_DC_0; /**< Clock Mux 12 Divider 0 Control Register, off… member
/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Frequency.c3307 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM_1->MUX_12_DC_0 & MC_CGM_MUX_12_DC_0_DE_MASK) >… in Clock_Ip_Get_P1_LFAST1_REF_CLK_Frequency()
3308 …Frequency /= (((IP_MC_CGM_1->MUX_12_DC_0 & MC_CGM_MUX_12_DC_0_DIV_MASK) >> MC_CGM_MUX_12_DC_0_DIV_… in Clock_Ip_Get_P1_LFAST1_REF_CLK_Frequency()