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Searched refs:MCR0 (Results 1 – 25 of 88) sorted by relevance

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/hal_nxp-3.5.0/mcux/mcux-sdk/boards/mimxrt685audevk/project_template/
Dboard.c299 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in BOARD_DeinitXip()
306 base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; in BOARD_DeinitXip()
317 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in BOARD_InitXip()
319 base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; in BOARD_InitXip()
320 while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) in BOARD_InitXip()
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/mimxrt685audevk/
Dboard.c299 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in BOARD_DeinitXip()
306 base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; in BOARD_DeinitXip()
317 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in BOARD_InitXip()
319 base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; in BOARD_InitXip()
320 while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) in BOARD_InitXip()
/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/flexspi/
Dfsl_flexspi.h433 base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; in FLEXSPI_SoftwareReset()
434 while (0U != (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK)) in FLEXSPI_SoftwareReset()
449 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in FLEXSPI_Enable()
453 base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; in FLEXSPI_Enable()
Dfsl_flexspi.c157 … uint32_t rxSampleClock = (base->MCR0 & FLEXSPI_MCR0_RXCLKSRC_MASK) >> FLEXSPI_MCR0_RXCLKSRC_SHIFT; in FLEXSPI_CalculateDll()
268 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in FLEXSPI_Init()
287 base->MCR0 = configValue; in FLEXSPI_Init()
445 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in FLEXSPI_UpdateDllValue()
541 base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; in FLEXSPI_SetFlashConfig()
567 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in FLEXSPI_SetFlashConfig()
629 mcr0Val = base->MCR0; in FLEXSPI_UpdateRxSampleClock()
632 base->MCR0 = mcr0Val; in FLEXSPI_UpdateRxSampleClock()
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/evkmimxrt685/
Dboard.c303 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in BOARD_DeinitXip()
310 base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; in BOARD_DeinitXip()
321 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in BOARD_InitXip()
323 base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; in BOARD_InitXip()
324 while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) in BOARD_InitXip()
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/evkmimxrt685/project_template/
Dboard.c303 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in BOARD_DeinitXip()
310 base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; in BOARD_DeinitXip()
321 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in BOARD_InitXip()
323 base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; in BOARD_InitXip()
324 while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) in BOARD_InitXip()
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/evkmimxrt595/
Dboard.c299 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in BOARD_DeinitFlash()
306 base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; in BOARD_DeinitFlash()
320 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in BOARD_InitFlash()
322 base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; in BOARD_InitFlash()
323 while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) in BOARD_InitFlash()
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/evkmimxrt595/project_template/
Dboard.c299 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in BOARD_DeinitFlash()
306 base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; in BOARD_DeinitFlash()
320 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in BOARD_InitFlash()
322 base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; in BOARD_InitFlash()
323 while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) in BOARD_InitFlash()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT685S/project_template/
Dboard.c291 base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; in BOARD_DeinitXip()
302 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in BOARD_InitXip()
304 base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; in BOARD_InitXip()
305 while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) in BOARD_InitXip()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT595S/project_template/
Dboard.c312 base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; in BOARD_DeinitXip()
326 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in BOARD_InitXip()
328 base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; in BOARD_InitXip()
329 while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) in BOARD_InitXip()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT595S/drivers/
Dfsl_power.c626 FLEXSPI0->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; in AT_QUICKACCESS_SECTION_CODE()
638 FLEXSPI1->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; in AT_QUICKACCESS_SECTION_CODE()
655 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in AT_QUICKACCESS_SECTION_CODE()
657 base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; in AT_QUICKACCESS_SECTION_CODE()
658 while ((base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) != 0U) in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT555S/drivers/
Dfsl_power.c626 FLEXSPI0->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; in AT_QUICKACCESS_SECTION_CODE()
638 FLEXSPI1->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; in AT_QUICKACCESS_SECTION_CODE()
655 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in AT_QUICKACCESS_SECTION_CODE()
657 base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; in AT_QUICKACCESS_SECTION_CODE()
658 while ((base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) != 0U) in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT533S/drivers/
Dfsl_power.c626 FLEXSPI0->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; in AT_QUICKACCESS_SECTION_CODE()
638 FLEXSPI1->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; in AT_QUICKACCESS_SECTION_CODE()
655 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in AT_QUICKACCESS_SECTION_CODE()
657 base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; in AT_QUICKACCESS_SECTION_CODE()
658 while ((base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) != 0U) in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-3.5.0/mcux/mcux-sdk/components/flash/nor/flexspi/
Dfsl_flexspi_nor_flash.c2389 ((FLEXSPI_Type *)handle->driverBaseAddr)->MCR0 &= ~FLEXSPI_MCR0_RXCLKSRC_MASK; in FLEXSPI_NOR_MacronixEnterOctalMode()
2390 ((FLEXSPI_Type *)handle->driverBaseAddr)->MCR0 |= in FLEXSPI_NOR_MacronixEnterOctalMode()
2406 ((FLEXSPI_Type *)handle->driverBaseAddr)->MCR0 &= ~FLEXSPI_MCR0_RXCLKSRC_MASK; in FLEXSPI_NOR_MacronixEnterOctalMode()
2407 ((FLEXSPI_Type *)handle->driverBaseAddr)->MCR0 |= in FLEXSPI_NOR_MacronixEnterOctalMode()
2501 ((FLEXSPI_Type *)handle->driverBaseAddr)->MCR0 &= ~FLEXSPI_MCR0_RXCLKSRC_MASK; in FLEXSPI_NOR_MacronixEnterOctalMode()
2502 ((FLEXSPI_Type *)handle->driverBaseAddr)->MCR0 |= in FLEXSPI_NOR_MacronixEnterOctalMode()
2683 ((FLEXSPI_Type *)handle->driverBaseAddr)->MCR0 &= ~FLEXSPI_MCR0_RXCLKSRC_MASK; in FLEXSPI_NOR_MacronixExitOctalMode()
2684 ((FLEXSPI_Type *)handle->driverBaseAddr)->MCR0 |= in FLEXSPI_NOR_MacronixExitOctalMode()
3079 ((FLEXSPI_Type *)handle->driverBaseAddr)->MCR0 &= ~FLEXSPI_MCR0_RXCLKSRC_MASK; in FLEXSPI_NOR_AdestoEnterOctalMode()
3080 ((FLEXSPI_Type *)handle->driverBaseAddr)->MCR0 |= in FLEXSPI_NOR_AdestoEnterOctalMode()
[all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT685S/drivers/
Dfsl_power.c631 FLEXSPI->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; in AT_QUICKACCESS_SECTION_CODE()
645 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in AT_QUICKACCESS_SECTION_CODE()
647 base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; in AT_QUICKACCESS_SECTION_CODE()
648 while ((base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) != 0U) in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT633S/drivers/
Dfsl_power.c631 FLEXSPI->MCR0 |= FLEXSPI_MCR0_MDIS_MASK; in AT_QUICKACCESS_SECTION_CODE()
645 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK; in AT_QUICKACCESS_SECTION_CODE()
647 base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK; in AT_QUICKACCESS_SECTION_CODE()
648 while ((base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK) != 0U) in AT_QUICKACCESS_SECTION_CODE()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT685S/
DMIMXRT685S_dsp.h7244 __IO uint32_t MCR0; /**< Module Control Register 0, offset: 0x0 */ member
DMIMXRT685S_cm33.h13346 __IO uint32_t MCR0; /**< Module Control Register 0, offset: 0x0 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h16101 __IO uint32_t MCR0; /**< Module Control Register 0, offset: 0x0 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h13502 __IO uint32_t MCR0; /**< Module Control Register 0, offset: 0x0 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT633S/
DMIMXRT633S.h13346 __IO uint32_t MCR0; /**< Module Control Register 0, offset: 0x0 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5536/
DLPC5536.h12296 __IO uint32_t MCR0; /**< Module Control Register 0, offset: 0x0 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT595S/
DMIMXRT595S_dsp.h12982 __IO uint32_t MCR0; /**< Module Control Register 0, offset: 0x0 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/LPC5534/
DLPC5534.h12296 __IO uint32_t MCR0; /**< Module Control Register 0, offset: 0x0 */ member
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h19563 __IO uint32_t MCR0; /**< Module Control Register 0, offset: 0x0 */ member

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