1 /*
2 * Copyright 2018 NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include <stdint.h>
10 #include "fsl_common.h"
11 #include "fsl_debug_console.h"
12 #include "board.h"
13 #include "fsl_clock.h"
14 #include "fsl_flexspi.h"
15 #include "fsl_cache.h"
16 #include "fsl_power.h"
17 #if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
18 #include "fsl_i2c.h"
19 #endif /* SDK_I2C_BASED_COMPONENT_USED */
20 #if defined BOARD_USE_CODEC
21 #include "fsl_i3c.h"
22 #endif
23
24 /*******************************************************************************
25 * Definitions
26 ******************************************************************************/
27 #define BOARD_FLEXSPI_DLL_LOCK_RETRY (10)
28 #define BOARD_IS_XIP_FLEXSPI() \
29 ((((uint32_t)BOARD_InitDebugConsole >= 0x08000000U) && ((uint32_t)BOARD_InitDebugConsole < 0x10000000U)) || \
30 (((uint32_t)BOARD_InitDebugConsole >= 0x18000000U) && ((uint32_t)BOARD_InitDebugConsole < 0x20000000U)))
31 /*******************************************************************************
32 * Variables
33 ******************************************************************************/
34 static status_t flexspi_hyper_ram_write_mcr(FLEXSPI_Type *base, uint8_t regAddr, uint32_t *mrVal);
35 static status_t flexspi_hyper_ram_get_mcr(FLEXSPI_Type *base, uint8_t regAddr, uint32_t *mrVal);
36 static status_t flexspi_hyper_ram_reset(FLEXSPI_Type *base);
37 /*******************************************************************************
38 * Code
39 ******************************************************************************/
40 /* Initialize debug console. */
BOARD_InitDebugConsole(void)41 void BOARD_InitDebugConsole(void)
42 {
43 uint32_t uartClkSrcFreq;
44
45 /* attach FRG0 clock to FLEXCOMM0 (debug console) */
46 CLOCK_SetFRGClock(BOARD_DEBUG_UART_FRG_CLK);
47 CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
48
49 uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
50
51 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
52 }
53
flexspi_hyper_ram_write_mcr(FLEXSPI_Type * base,uint8_t regAddr,uint32_t * mrVal)54 static status_t flexspi_hyper_ram_write_mcr(FLEXSPI_Type *base, uint8_t regAddr, uint32_t *mrVal)
55 {
56 flexspi_transfer_t flashXfer;
57 status_t status;
58
59 /* Write data */
60 flashXfer.deviceAddress = regAddr;
61 flashXfer.port = kFLEXSPI_PortA1;
62 flashXfer.cmdType = kFLEXSPI_Write;
63 flashXfer.SeqNumber = 1;
64 flashXfer.seqIndex = 3;
65 flashXfer.data = mrVal;
66 flashXfer.dataSize = 1;
67
68 status = FLEXSPI_TransferBlocking(base, &flashXfer);
69
70 return status;
71 }
72
flexspi_hyper_ram_get_mcr(FLEXSPI_Type * base,uint8_t regAddr,uint32_t * mrVal)73 static status_t flexspi_hyper_ram_get_mcr(FLEXSPI_Type *base, uint8_t regAddr, uint32_t *mrVal)
74 {
75 flexspi_transfer_t flashXfer;
76 status_t status;
77
78 /* Read data */
79 flashXfer.deviceAddress = regAddr;
80 flashXfer.port = kFLEXSPI_PortA1;
81 flashXfer.cmdType = kFLEXSPI_Read;
82 flashXfer.SeqNumber = 1;
83 flashXfer.seqIndex = 2;
84 flashXfer.data = mrVal;
85 flashXfer.dataSize = 2;
86
87 status = FLEXSPI_TransferBlocking(base, &flashXfer);
88
89 return status;
90 }
91
flexspi_hyper_ram_reset(FLEXSPI_Type * base)92 static status_t flexspi_hyper_ram_reset(FLEXSPI_Type *base)
93 {
94 flexspi_transfer_t flashXfer;
95 status_t status;
96
97 /* Write data */
98 flashXfer.deviceAddress = 0x0U;
99 flashXfer.port = kFLEXSPI_PortA1;
100 flashXfer.cmdType = kFLEXSPI_Command;
101 flashXfer.SeqNumber = 1;
102 flashXfer.seqIndex = 4;
103
104 status = FLEXSPI_TransferBlocking(base, &flashXfer);
105
106 if (status == kStatus_Success)
107 {
108 /* for loop of 50000 is about 1ms (@200 MHz CPU) */
109 for (uint32_t i = 2000000U; i > 0; i--)
110 {
111 __NOP();
112 }
113 }
114 return status;
115 }
116
117 /* Initialize psram. */
BOARD_InitPsRam(void)118 status_t BOARD_InitPsRam(void)
119 {
120 flexspi_device_config_t deviceconfig = {
121 .flexspiRootClk = 396000000, /* 396MHZ SPI serial clock, DDR serial clock 198M */
122 .isSck2Enabled = false,
123 .flashSize = 0x8000, /*64Mb/KByte*/
124 .CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle,
125 .CSInterval = 5,
126 .CSHoldTime = 3,
127 .CSSetupTime = 3,
128 .dataValidTime = 1,
129 .columnspace = 0,
130 .enableWordAddress = false,
131 .AWRSeqIndex = 1,
132 .AWRSeqNumber = 1,
133 .ARDSeqIndex = 0,
134 .ARDSeqNumber = 1,
135 .AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
136 .AHBWriteWaitInterval = 0,
137 .enableWriteMask = true,
138 };
139
140 uint32_t customLUT[64] = {
141 /* Read Data */
142 [0] =
143 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20),
144 [1] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x07, kFLEXSPI_Command_READ_DDR,
145 kFLEXSPI_8PAD, 0x04),
146
147 /* Write Data */
148 [4] =
149 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20),
150 [5] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x07, kFLEXSPI_Command_WRITE_DDR,
151 kFLEXSPI_8PAD, 0x04),
152
153 /* Read Register */
154 [8] =
155 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x40, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20),
156 [9] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x07, kFLEXSPI_Command_READ_DDR,
157 kFLEXSPI_8PAD, 0x04),
158
159 /* Write Register */
160 [12] =
161 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0xC0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20),
162 [13] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x08, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD,
163 0x00),
164
165 /* reset */
166 [16] =
167 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0xFF, kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_8PAD, 0x03),
168
169 };
170
171 uint32_t mr0mr1[1];
172 uint32_t mr4mr8[1];
173 uint32_t mr0Val[1];
174 uint32_t mr4Val[1];
175 uint32_t mr8Val[1];
176 flexspi_config_t config;
177 cache64_config_t cacheCfg;
178 status_t status = kStatus_Success;
179
180 POWER_DisablePD(kPDRUNCFG_APD_FLEXSPI_SRAM);
181 POWER_DisablePD(kPDRUNCFG_PPD_FLEXSPI_SRAM);
182 POWER_ApplyPD();
183
184 CLOCK_AttachClk(kAUX0_PLL_to_FLEXSPI_CLK);
185 CLOCK_SetClkDiv(kCLOCK_DivFlexspiClk, 1);
186
187 RESET_PeripheralReset(kFLEXSPI_RST_SHIFT_RSTn);
188 /* Explicitly enable FlexSPI clock for PSRAM loader case which need to set FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL. */
189 CLOCK_EnableClock(kCLOCK_Flexspi);
190
191 /* As cache depends on FlexSPI power and clock, cache must be initialized after FlexSPI power/clock is set */
192 CACHE64_GetDefaultConfig(&cacheCfg);
193 CACHE64_Init(CACHE64_POLSEL, &cacheCfg);
194 #if BOARD_ENABLE_PSRAM_CACHE
195 CACHE64_EnableCache(CACHE64);
196 #endif
197
198 /* Get FLEXSPI default settings and configure the flexspi. */
199 FLEXSPI_GetDefaultConfig(&config);
200
201 /* Init FLEXSPI. */
202 config.rxSampleClock = kFLEXSPI_ReadSampleClkExternalInputFromDqsPad;
203 /*Set AHB buffer size for reading data through AHB bus. */
204 config.ahbConfig.enableAHBPrefetch = true;
205 config.ahbConfig.enableAHBBufferable = true;
206 config.ahbConfig.enableAHBCachable = true;
207 config.ahbConfig.enableReadAddressOpt = true;
208 for (uint8_t i = 1; i < FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 1; i++)
209 {
210 config.ahbConfig.buffer[i].bufferSize = 0;
211 }
212 /* FlexSPI has total 1KB RX buffer.
213 * Set DMA0 master to use AHB Rx Buffer0.
214 */
215 config.ahbConfig.buffer[0].masterIndex = 4; /* DMA0 */
216 config.ahbConfig.buffer[0].bufferSize = 512; /* Allocate 512B bytes for DMA0 */
217 config.ahbConfig.buffer[0].enablePrefetch = true;
218 config.ahbConfig.buffer[0].priority = 0;
219 /* All other masters use last buffer with 512B bytes. */
220 config.ahbConfig.buffer[FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 1].bufferSize = 512;
221 #if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN)
222 config.enableCombination = true;
223 #endif
224 FLEXSPI_Init(BOARD_FLEXSPI_PSRAM, &config);
225
226 /* Configure flash settings according to serial flash feature. */
227 FLEXSPI_SetFlashConfig(BOARD_FLEXSPI_PSRAM, &deviceconfig, kFLEXSPI_PortA1);
228
229 /* Update LUT table. */
230 FLEXSPI_UpdateLUT(BOARD_FLEXSPI_PSRAM, 0, customLUT, ARRAY_SIZE(customLUT));
231
232 /* Do software reset. */
233 FLEXSPI_SoftwareReset(BOARD_FLEXSPI_PSRAM);
234
235 /* Reset hyper ram. */
236 status = flexspi_hyper_ram_reset(BOARD_FLEXSPI_PSRAM);
237 if (status != kStatus_Success)
238 {
239 return status;
240 }
241
242 status = flexspi_hyper_ram_get_mcr(BOARD_FLEXSPI_PSRAM, 0x0, mr0mr1);
243 if (status != kStatus_Success)
244 {
245 return status;
246 }
247
248 status = flexspi_hyper_ram_get_mcr(BOARD_FLEXSPI_PSRAM, 0x4, mr4mr8);
249 if (status != kStatus_Success)
250 {
251 return status;
252 }
253
254 /* Enable RBX, burst length set to 1K. - MR8 */
255 mr8Val[0] = (mr4mr8[0] & 0xFF00U) >> 8U;
256 mr8Val[0] = mr8Val[0] | 0x0F;
257 status = flexspi_hyper_ram_write_mcr(BOARD_FLEXSPI_PSRAM, 0x8, mr8Val);
258 if (status != kStatus_Success)
259 {
260 return status;
261 }
262
263 /* Set LC code to 0x04(LC=7, maximum frequency 200M) - MR0. */
264 mr0Val[0] = mr0mr1[0] & 0x00FFU;
265 mr0Val[0] = (mr0Val[0] & ~0x3C) | (4 << 2U);
266 status = flexspi_hyper_ram_write_mcr(BOARD_FLEXSPI_PSRAM, 0x0, mr0Val);
267 if (status != kStatus_Success)
268 {
269 return status;
270 }
271
272 /* Set WLC code to 0x01(WLC=7, maximum frequency 200M) - MR4. */
273 mr4Val[0] = mr4mr8[0] & 0x00FFU;
274 mr4Val[0] = (mr4Val[0] & ~0xE0) | (1 << 5U);
275 status = flexspi_hyper_ram_write_mcr(BOARD_FLEXSPI_PSRAM, 0x4, mr4Val);
276 if (status != kStatus_Success)
277 {
278 return status;
279 }
280
281 return status;
282 }
283
BOARD_DeinitXip(FLEXSPI_Type * base)284 void BOARD_DeinitXip(FLEXSPI_Type *base)
285 {
286 /* Wait until FLEXSPI is not busy */
287 while (!((base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK)))
288 {
289 }
290 /* Disable module during the reset procedure */
291 base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK;
292 }
293
BOARD_InitXip(FLEXSPI_Type * base)294 void BOARD_InitXip(FLEXSPI_Type *base)
295 {
296 uint32_t status;
297 uint32_t lastStatus;
298 uint32_t retry;
299 uint32_t mask = 0;
300
301 /* Enable FLEXSPI module */
302 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
303
304 base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
305 while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK)
306 {
307 }
308
309 /* Need to wait DLL locked if DLL enabled */
310 if (0U != (base->DLLCR[0] & FLEXSPI_DLLCR_DLLEN_MASK))
311 {
312 lastStatus = base->STS2;
313 retry = BOARD_FLEXSPI_DLL_LOCK_RETRY;
314 /* Flash on port A */
315 if ((base->FLSHCR0[0] & FLEXSPI_FLSHCR0_FLSHSZ_MASK) > 0 ||
316 (base->FLSHCR0[1] & FLEXSPI_FLSHCR0_FLSHSZ_MASK) > 0)
317 {
318 mask |= FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK;
319 }
320 /* Flash on port B */
321 if ((base->FLSHCR0[2] & FLEXSPI_FLSHCR0_FLSHSZ_MASK) > 0 ||
322 (base->FLSHCR0[3] & FLEXSPI_FLSHCR0_FLSHSZ_MASK) > 0)
323 {
324 mask |= FLEXSPI_STS2_BREFLOCK_MASK | FLEXSPI_STS2_BSLVLOCK_MASK;
325 }
326 /* Wait slave delay line locked and slave reference delay line locked. */
327 do
328 {
329 status = base->STS2;
330 if ((status & mask) == mask)
331 {
332 /* Locked */
333 retry = 100;
334 break;
335 }
336 else if (status == lastStatus)
337 {
338 /* Same delay cell number in calibration */
339 retry--;
340 }
341 else
342 {
343 retry = BOARD_FLEXSPI_DLL_LOCK_RETRY;
344 lastStatus = status;
345 }
346 } while (retry > 0);
347 /* According to ERR011377, need to delay at least 100 NOPs to ensure the DLL is locked. */
348 for (; retry > 0U; retry--)
349 {
350 __NOP();
351 }
352 }
353 }
354
355 /* BOARD_SetFlexspiClock run in RAM used to configure FlexSPI clock source and divider when XIP. */
BOARD_SetFlexspiClock(uint32_t src,uint32_t divider)356 void BOARD_SetFlexspiClock(uint32_t src, uint32_t divider)
357 {
358 if (CLKCTL0->FLEXSPIFCLKSEL != CLKCTL0_FLEXSPIFCLKSEL_SEL(src) ||
359 (CLKCTL0->FLEXSPIFCLKDIV & CLKCTL0_FLEXSPIFCLKDIV_DIV_MASK) != (divider - 1))
360 {
361 if (BOARD_IS_XIP_FLEXSPI())
362 {
363 BOARD_DeinitXip(FLEXSPI);
364 }
365 /* Disable clock before changing clock source */
366 CLKCTL0->PSCCTL0_CLR = CLKCTL0_PSCCTL0_CLR_FLEXSPI_OTFAD_CLK_MASK;
367 /* Update flexspi clock. */
368 CLKCTL0->FLEXSPIFCLKSEL = CLKCTL0_FLEXSPIFCLKSEL_SEL(src);
369 CLKCTL0->FLEXSPIFCLKDIV |= CLKCTL0_FLEXSPIFCLKDIV_RESET_MASK; /* Reset the divider counter */
370 CLKCTL0->FLEXSPIFCLKDIV = CLKCTL0_FLEXSPIFCLKDIV_DIV(divider - 1);
371 while ((CLKCTL0->FLEXSPIFCLKDIV) & CLKCTL0_FLEXSPIFCLKDIV_REQFLAG_MASK)
372 {
373 }
374 /* Enable FLEXSPI clock again */
375 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI_OTFAD_CLK_MASK;
376 if (BOARD_IS_XIP_FLEXSPI())
377 {
378 BOARD_InitXip(FLEXSPI);
379 }
380 }
381 }
382
383 /* This function is used to change FlexSPI clock to a stable source before clock sources(Such as PLL and Main clock)
384 * updating in case XIP(execute code on FLEXSPI memory.) */
BOARD_FlexspiClockSafeConfig(void)385 void BOARD_FlexspiClockSafeConfig(void)
386 {
387 /* Move FLEXSPI clock source from main clock to FFRO to avoid instruction/data fetch issue in XIP when
388 * updating PLL and main clock.
389 */
390 BOARD_SetFlexspiClock(3U, 1);
391 }
392
393 #if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
BOARD_I2C_Init(I2C_Type * base,uint32_t clkSrc_Hz)394 void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz)
395 {
396 i2c_master_config_t i2cConfig = {0};
397
398 I2C_MasterGetDefaultConfig(&i2cConfig);
399 I2C_MasterInit(base, &i2cConfig, clkSrc_Hz);
400 }
401
BOARD_I2C_Send(I2C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subaddressSize,uint8_t * txBuff,uint8_t txBuffSize)402 status_t BOARD_I2C_Send(I2C_Type *base,
403 uint8_t deviceAddress,
404 uint32_t subAddress,
405 uint8_t subaddressSize,
406 uint8_t *txBuff,
407 uint8_t txBuffSize)
408 {
409 i2c_master_transfer_t masterXfer;
410
411 /* Prepare transfer structure. */
412 masterXfer.slaveAddress = deviceAddress;
413 masterXfer.direction = kI2C_Write;
414 masterXfer.subaddress = subAddress;
415 masterXfer.subaddressSize = subaddressSize;
416 masterXfer.data = txBuff;
417 masterXfer.dataSize = txBuffSize;
418 masterXfer.flags = kI2C_TransferDefaultFlag;
419
420 return I2C_MasterTransferBlocking(base, &masterXfer);
421 }
422
BOARD_I2C_Receive(I2C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subaddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)423 status_t BOARD_I2C_Receive(I2C_Type *base,
424 uint8_t deviceAddress,
425 uint32_t subAddress,
426 uint8_t subaddressSize,
427 uint8_t *rxBuff,
428 uint8_t rxBuffSize)
429 {
430 i2c_master_transfer_t masterXfer;
431
432 /* Prepare transfer structure. */
433 masterXfer.slaveAddress = deviceAddress;
434 masterXfer.subaddress = subAddress;
435 masterXfer.subaddressSize = subaddressSize;
436 masterXfer.data = rxBuff;
437 masterXfer.dataSize = rxBuffSize;
438 masterXfer.direction = kI2C_Read;
439 masterXfer.flags = kI2C_TransferDefaultFlag;
440
441 return I2C_MasterTransferBlocking(base, &masterXfer);
442 }
443 #endif
444
445 #if defined BOARD_USE_CODEC
BOARD_I3C_Init(I3C_Type * base,uint32_t clkSrc_Hz)446 void BOARD_I3C_Init(I3C_Type *base, uint32_t clkSrc_Hz)
447 {
448 i3c_master_config_t i3cConfig;
449
450 I3C_MasterGetDefaultConfig(&i3cConfig);
451 I3C_MasterInit(base, &i3cConfig, clkSrc_Hz);
452 }
453
BOARD_I3C_Send(I3C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subaddressSize,uint8_t * txBuff,uint8_t txBuffSize)454 status_t BOARD_I3C_Send(I3C_Type *base,
455 uint8_t deviceAddress,
456 uint32_t subAddress,
457 uint8_t subaddressSize,
458 uint8_t *txBuff,
459 uint8_t txBuffSize)
460 {
461 i3c_master_transfer_t masterXfer;
462
463 /* Prepare transfer structure. */
464 masterXfer.slaveAddress = deviceAddress;
465 masterXfer.direction = kI3C_Write;
466 masterXfer.busType = kI3C_TypeI2C;
467 masterXfer.subaddress = subAddress;
468 masterXfer.subaddressSize = subaddressSize;
469 masterXfer.data = txBuff;
470 masterXfer.dataSize = txBuffSize;
471 masterXfer.flags = kI3C_TransferDefaultFlag;
472
473 return I3C_MasterTransferBlocking(base, &masterXfer);
474 }
475
BOARD_I3C_Receive(I3C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subaddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)476 status_t BOARD_I3C_Receive(I3C_Type *base,
477 uint8_t deviceAddress,
478 uint32_t subAddress,
479 uint8_t subaddressSize,
480 uint8_t *rxBuff,
481 uint8_t rxBuffSize)
482 {
483 i3c_master_transfer_t masterXfer;
484
485 /* Prepare transfer structure. */
486 masterXfer.slaveAddress = deviceAddress;
487 masterXfer.subaddress = subAddress;
488 masterXfer.subaddressSize = subaddressSize;
489 masterXfer.data = rxBuff;
490 masterXfer.dataSize = rxBuffSize;
491 masterXfer.direction = kI3C_Read;
492 masterXfer.busType = kI3C_TypeI2C;
493 masterXfer.flags = kI3C_TransferDefaultFlag;
494
495 return I3C_MasterTransferBlocking(base, &masterXfer);
496 }
497
BOARD_Codec_I2C_Init(void)498 void BOARD_Codec_I2C_Init(void)
499 {
500 #if BOARD_I3C_CODEC
501 BOARD_I3C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
502 #else
503 BOARD_I2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
504 #endif
505 }
506
BOARD_Codec_I2C_Send(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,const uint8_t * txBuff,uint8_t txBuffSize)507 status_t BOARD_Codec_I2C_Send(
508 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
509 {
510 #if BOARD_I3C_CODEC
511 return BOARD_I3C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
512 #else
513 return BOARD_I2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
514 #endif
515 txBuffSize);
516 }
517
BOARD_Codec_I2C_Receive(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)518 status_t BOARD_Codec_I2C_Receive(
519 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
520 {
521 #if BOARD_I3C_CODEC
522 return BOARD_I3C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
523 #else
524 return BOARD_I2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
525 #endif
526 }
527 #endif
528
529 #if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
BOARD_PMIC_I2C_Init(void)530 void BOARD_PMIC_I2C_Init(void)
531 {
532 BOARD_I2C_Init(BOARD_PMIC_I2C_BASEADDR, BOARD_PMIC_I2C_CLOCK_FREQ);
533 }
534
BOARD_PMIC_I2C_Send(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,const uint8_t * txBuff,uint8_t txBuffSize)535 status_t BOARD_PMIC_I2C_Send(
536 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
537 {
538 return BOARD_I2C_Send(BOARD_PMIC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
539 txBuffSize);
540 }
541
BOARD_PMIC_I2C_Receive(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)542 status_t BOARD_PMIC_I2C_Receive(
543 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
544 {
545 return BOARD_I2C_Receive(BOARD_PMIC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
546 }
547
BOARD_Accel_I2C_Init(void)548 void BOARD_Accel_I2C_Init(void)
549 {
550 BOARD_I2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
551 }
552
BOARD_Accel_I2C_Send(uint8_t deviceAddress,uint32_t subAddress,uint8_t subaddressSize,uint32_t txBuff)553 status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
554 {
555 uint8_t data = (uint8_t)txBuff;
556
557 return BOARD_I2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
558 }
559
BOARD_Accel_I2C_Receive(uint8_t deviceAddress,uint32_t subAddress,uint8_t subaddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)560 status_t BOARD_Accel_I2C_Receive(
561 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
562 {
563 return BOARD_I2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
564 }
565
566 #endif /* SDK_I2C_BASED_COMPONENT_USED */
567
