1 /*
2  * Copyright 2018-2020 NXP
3  * All rights reserved.
4  *
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 
9 #include <stdint.h>
10 #include "fsl_common.h"
11 #include "fsl_debug_console.h"
12 #include "fsl_clock.h"
13 #include "fsl_flexspi.h"
14 #include "fsl_cache.h"
15 #include "fsl_power.h"
16 #include "clock_config.h"
17 #include "board.h"
18 #if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
19 #include "fsl_i2c.h"
20 #endif /* SDK_I2C_BASED_COMPONENT_USED */
21 #if defined BOARD_USE_CODEC
22 #include "fsl_i3c.h"
23 #endif
24 
25 /*******************************************************************************
26  * Definitions
27  ******************************************************************************/
28 #define BOARD_FLEXSPI_DLL_LOCK_RETRY (10)
29 #if (__ARM_FEATURE_CMSE & 0x2) && defined(__ARMCC_VERSION)
30 /* For the Trustzone examples built with ARM Compiler, the RAM targets will also run in flash(XIP) to do initialization
31  * copy. */
32 #define BOARD_IS_XIP_FLEXSPI0() (true)
33 #define BOARD_IS_XIP_FLEXSPI1() (true)
34 #else
35 #define BOARD_IS_XIP_FLEXSPI0()                                                                                 \
36     ((((uint32_t)BOARD_InitDebugConsole >= 0x08000000U) && ((uint32_t)BOARD_InitDebugConsole < 0x10000000U)) || \
37      (((uint32_t)BOARD_InitDebugConsole >= 0x18000000U) && ((uint32_t)BOARD_InitDebugConsole < 0x20000000U)))
38 #define BOARD_IS_XIP_FLEXSPI1()                                                                                 \
39     ((((uint32_t)BOARD_InitDebugConsole >= 0x28000000U) && ((uint32_t)BOARD_InitDebugConsole < 0x30000000U)) || \
40      (((uint32_t)BOARD_InitDebugConsole >= 0x38000000U) && ((uint32_t)BOARD_InitDebugConsole < 0x40000000U)))
41 #endif
42 /*******************************************************************************
43  * Variables
44  ******************************************************************************/
45 
46 /*******************************************************************************
47  * Prototypes
48  ******************************************************************************/
49 static status_t flexspi_hyper_ram_write_mcr(FLEXSPI_Type *base, uint8_t regAddr, uint32_t *mrVal);
50 static status_t flexspi_hyper_ram_get_mcr(FLEXSPI_Type *base, uint8_t regAddr, uint32_t *mrVal);
51 static status_t flexspi_hyper_ram_reset(FLEXSPI_Type *base);
52 /*******************************************************************************
53  * Code
54  ******************************************************************************/
55 /* Initialize debug console. */
BOARD_InitDebugConsole(void)56 void BOARD_InitDebugConsole(void)
57 {
58     uint32_t uartClkSrcFreq;
59 
60     /* attach FRG0 clock to FLEXCOMM0 (debug console) */
61     CLOCK_SetFRGClock(BOARD_DEBUG_UART_FRG_CLK);
62     CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
63 
64     uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
65 
66     DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
67 }
68 
flexspi_hyper_ram_write_mcr(FLEXSPI_Type * base,uint8_t regAddr,uint32_t * mrVal)69 static status_t flexspi_hyper_ram_write_mcr(FLEXSPI_Type *base, uint8_t regAddr, uint32_t *mrVal)
70 {
71     flexspi_transfer_t flashXfer;
72     status_t status;
73 
74     /* Write data */
75     flashXfer.deviceAddress = regAddr;
76     flashXfer.port          = kFLEXSPI_PortA1;
77     flashXfer.cmdType       = kFLEXSPI_Write;
78     flashXfer.SeqNumber     = 1;
79     flashXfer.seqIndex      = 3;
80     flashXfer.data          = mrVal;
81     flashXfer.dataSize      = 1;
82 
83     status = FLEXSPI_TransferBlocking(base, &flashXfer);
84 
85     return status;
86 }
87 
flexspi_hyper_ram_get_mcr(FLEXSPI_Type * base,uint8_t regAddr,uint32_t * mrVal)88 static status_t flexspi_hyper_ram_get_mcr(FLEXSPI_Type *base, uint8_t regAddr, uint32_t *mrVal)
89 {
90     flexspi_transfer_t flashXfer;
91     status_t status;
92 
93     /* Read data */
94     flashXfer.deviceAddress = regAddr;
95     flashXfer.port          = kFLEXSPI_PortA1;
96     flashXfer.cmdType       = kFLEXSPI_Read;
97     flashXfer.SeqNumber     = 1;
98     flashXfer.seqIndex      = 2;
99     flashXfer.data          = mrVal;
100     flashXfer.dataSize      = 2;
101 
102     status = FLEXSPI_TransferBlocking(base, &flashXfer);
103 
104     return status;
105 }
106 
flexspi_hyper_ram_reset(FLEXSPI_Type * base)107 static status_t flexspi_hyper_ram_reset(FLEXSPI_Type *base)
108 {
109     flexspi_transfer_t flashXfer;
110     status_t status;
111 
112     /* Write data */
113     flashXfer.deviceAddress = 0x0U;
114     flashXfer.port          = kFLEXSPI_PortA1;
115     flashXfer.cmdType       = kFLEXSPI_Command;
116     flashXfer.SeqNumber     = 1;
117     flashXfer.seqIndex      = 4;
118 
119     status = FLEXSPI_TransferBlocking(base, &flashXfer);
120 
121     if (status == kStatus_Success)
122     {
123         /* for loop of 50000 is about 1ms (@200 MHz CPU) */
124         for (uint32_t i = 2000000U; i > 0; i--)
125         {
126             __NOP();
127         }
128     }
129     return status;
130 }
131 
132 /* Initialize psram. */
BOARD_InitPsRam(void)133 status_t BOARD_InitPsRam(void)
134 {
135     flexspi_device_config_t deviceconfig = {
136         .flexspiRootClk       = 396000000, /* 396MHZ SPI serial clock, DDR serial clock 198M */
137         .isSck2Enabled        = false,
138         .flashSize            = 0x2000, /* 64Mb/KByte */
139         .CSIntervalUnit       = kFLEXSPI_CsIntervalUnit1SckCycle,
140         .CSInterval           = 5,
141         .CSHoldTime           = 3,
142         .CSSetupTime          = 3,
143         .dataValidTime        = 1,
144         .columnspace          = 0,
145         .enableWordAddress    = false,
146         .AWRSeqIndex          = 1,
147         .AWRSeqNumber         = 1,
148         .ARDSeqIndex          = 0,
149         .ARDSeqNumber         = 1,
150         .AHBWriteWaitUnit     = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
151         .AHBWriteWaitInterval = 0,
152         .enableWriteMask      = true,
153     };
154 
155     uint32_t customLUT[64] = {
156         /* Read Data */
157         [0] =
158             FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20),
159         [1] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x07, kFLEXSPI_Command_READ_DDR,
160                               kFLEXSPI_8PAD, 0x04),
161 
162         /* Write Data */
163         [4] =
164             FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20),
165         [5] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x07, kFLEXSPI_Command_WRITE_DDR,
166                               kFLEXSPI_8PAD, 0x04),
167 
168         /* Read Register */
169         [8] =
170             FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x40, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20),
171         [9] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x07, kFLEXSPI_Command_READ_DDR,
172                               kFLEXSPI_8PAD, 0x04),
173 
174         /* Write Register */
175         [12] =
176             FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0xC0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20),
177         [13] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x08, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD,
178                                0x00),
179 
180         /* reset */
181         [16] =
182             FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0xFF, kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_8PAD, 0x03),
183 
184     };
185 
186     uint32_t mr0mr1[1];
187     uint32_t mr4mr8[1];
188     uint32_t mr0Val[1];
189     uint32_t mr4Val[1];
190     uint32_t mr8Val[1];
191     flexspi_config_t config;
192     cache64_config_t cacheCfg;
193     status_t status = kStatus_Success;
194 
195     POWER_DisablePD(kPDRUNCFG_APD_FLEXSPI1_SRAM);
196     POWER_DisablePD(kPDRUNCFG_PPD_FLEXSPI1_SRAM);
197     POWER_ApplyPD();
198 
199     CLOCK_AttachClk(kAUX0_PLL_to_FLEXSPI1_CLK);
200     CLOCK_SetClkDiv(kCLOCK_DivFlexspi1Clk, 1);
201 
202     RESET_PeripheralReset(kFLEXSPI1_RST_SHIFT_RSTn);
203 #if (defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
204     /* Need to explicitly enable FlexSPI1 clock in mpi_loader_extram_loader case.
205      * In that case, FlexSPI driver need to be used before data sections copy. So
206      * global variables are forbidden with FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL=1.
207      */
208     CLOCK_EnableClock(kCLOCK_Flexspi1);
209 #endif
210 
211     /* As cache depends on FlexSPI power and clock, cache must be initialized after FlexSPI power/clock is set */
212     CACHE64_GetDefaultConfig(&cacheCfg);
213     CACHE64_Init(CACHE64_POLSEL1, &cacheCfg);
214 #if BOARD_ENABLE_PSRAM_CACHE
215     CACHE64_EnableWriteBuffer(CACHE64_CTRL1, true);
216     CACHE64_EnableCache(CACHE64_CTRL1);
217 #endif
218 
219     /* Get FLEXSPI default settings and configure the flexspi. */
220     FLEXSPI_GetDefaultConfig(&config);
221 
222     /* Init FLEXSPI. */
223     config.rxSampleClock = kFLEXSPI_ReadSampleClkExternalInputFromDqsPad;
224     /*Set AHB buffer size for reading data through AHB bus. */
225     config.ahbConfig.enableAHBPrefetch    = true;
226     config.ahbConfig.enableAHBBufferable  = true;
227     config.ahbConfig.enableAHBCachable    = true;
228     config.ahbConfig.enableReadAddressOpt = true;
229     for (uint8_t i = 1; i < FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 1; i++)
230     {
231         config.ahbConfig.buffer[i].bufferSize = 0;
232     }
233     /* FlexSPI1 has total 2KB RX buffer.
234      * Set GPU/Display master to use AHB Rx Buffer0.
235      */
236     config.ahbConfig.buffer[0].masterIndex    = 11;   /* GPU/Display */
237     config.ahbConfig.buffer[0].bufferSize     = 1024; /* Allocate 1KB bytes for GPU/Display */
238     config.ahbConfig.buffer[0].enablePrefetch = true;
239     config.ahbConfig.buffer[0].priority       = 7; /* Set GPU/Display to highest priority. */
240     /* All other masters use last buffer with 1KB bytes. */
241     config.ahbConfig.buffer[FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 1].bufferSize = 1024;
242 #if !(defined(FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN) && FSL_FEATURE_FLEXSPI_HAS_NO_MCR0_COMBINATIONEN)
243     config.enableCombination = true;
244 #endif
245     FLEXSPI_Init(BOARD_FLEXSPI_PSRAM, &config);
246 
247     /* Configure flash settings according to serial flash feature. */
248     FLEXSPI_SetFlashConfig(BOARD_FLEXSPI_PSRAM, &deviceconfig, kFLEXSPI_PortA1);
249 
250     /* Update LUT table. */
251     FLEXSPI_UpdateLUT(BOARD_FLEXSPI_PSRAM, 0, customLUT, ARRAY_SIZE(customLUT));
252 
253     /* Do software reset. */
254     FLEXSPI_SoftwareReset(BOARD_FLEXSPI_PSRAM);
255 
256     /* Reset hyper ram. */
257     status = flexspi_hyper_ram_reset(BOARD_FLEXSPI_PSRAM);
258     if (status != kStatus_Success)
259     {
260         return status;
261     }
262 
263     status = flexspi_hyper_ram_get_mcr(BOARD_FLEXSPI_PSRAM, 0x0, mr0mr1);
264     if (status != kStatus_Success)
265     {
266         return status;
267     }
268 
269     status = flexspi_hyper_ram_get_mcr(BOARD_FLEXSPI_PSRAM, 0x4, mr4mr8);
270     if (status != kStatus_Success)
271     {
272         return status;
273     }
274 
275     /* Enable RBX, burst length set to 1K. - MR8 */
276     mr8Val[0] = (mr4mr8[0] & 0xFF00U) >> 8U;
277     mr8Val[0] = mr8Val[0] | 0x0F;
278     status    = flexspi_hyper_ram_write_mcr(BOARD_FLEXSPI_PSRAM, 0x8, mr8Val);
279     if (status != kStatus_Success)
280     {
281         return status;
282     }
283 
284     /* Set LC code to 0x04(LC=7, maximum frequency 200M) - MR0. */
285     mr0Val[0] = mr0mr1[0] & 0x00FFU;
286     mr0Val[0] = (mr0Val[0] & ~0x3CU) | (4U << 2U);
287     status    = flexspi_hyper_ram_write_mcr(BOARD_FLEXSPI_PSRAM, 0x0, mr0Val);
288     if (status != kStatus_Success)
289     {
290         return status;
291     }
292 
293     /* Set WLC code to 0x01(WLC=7, maximum frequency 200M) - MR4. */
294     mr4Val[0] = mr4mr8[0] & 0x00FFU;
295     mr4Val[0] = (mr4Val[0] & ~0xE0U) | (1U << 5U);
296     status    = flexspi_hyper_ram_write_mcr(BOARD_FLEXSPI_PSRAM, 0x4, mr4Val);
297     if (status != kStatus_Success)
298     {
299         return status;
300     }
301 
302     return status;
303 }
304 
BOARD_DeinitXip(FLEXSPI_Type * base)305 void BOARD_DeinitXip(FLEXSPI_Type *base)
306 {
307     /* Wait until FLEXSPI is not busy */
308     while (!((base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK)))
309     {
310     }
311     /* Disable module during the reset procedure */
312     base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK;
313 }
314 
BOARD_InitXip(FLEXSPI_Type * base)315 void BOARD_InitXip(FLEXSPI_Type *base)
316 {
317     uint32_t status;
318     uint32_t lastStatus;
319     uint32_t retry;
320 
321     /* If serial root clock is >= 100 MHz, DLLEN set to 1, OVRDEN set to 0, then SLVDLYTARGET setting of 0x0 is
322      * recommended. */
323     base->DLLCR[0] = 0x1U;
324 
325     /* Enable FLEXSPI module */
326     base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
327 
328     base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
329     while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK)
330     {
331     }
332 
333     /* Need to wait DLL locked if DLL enabled */
334     if (0U != (base->DLLCR[0] & FLEXSPI_DLLCR_DLLEN_MASK))
335     {
336         lastStatus = base->STS2;
337         retry      = BOARD_FLEXSPI_DLL_LOCK_RETRY;
338         /* Wait slave delay line locked and slave reference delay line locked. */
339         do
340         {
341             status = base->STS2;
342             if ((status & (FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK)) ==
343                 (FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK))
344             {
345                 /* Locked */
346                 retry = 100;
347                 break;
348             }
349             else if (status == lastStatus)
350             {
351                 /* Same delay cell number in calibration */
352                 retry--;
353             }
354             else
355             {
356                 retry      = BOARD_FLEXSPI_DLL_LOCK_RETRY;
357                 lastStatus = status;
358             }
359         } while (retry > 0);
360         /* According to ERR011377, need to delay at least 100 NOPs to ensure the DLL is locked. */
361         for (; retry > 0U; retry--)
362         {
363             __NOP();
364         }
365     }
366 }
367 
368 /* BOARD_SetFlexspiClock run in RAM used to configure FlexSPI clock source and divider when XIP. */
BOARD_SetFlexspiClock(FLEXSPI_Type * base,uint32_t src,uint32_t divider)369 void BOARD_SetFlexspiClock(FLEXSPI_Type *base, uint32_t src, uint32_t divider)
370 {
371     if (base == FLEXSPI0)
372     {
373         if ((CLKCTL0->FLEXSPI0FCLKSEL != CLKCTL0_FLEXSPI0FCLKSEL_SEL(src)) ||
374             ((CLKCTL0->FLEXSPI0FCLKDIV & CLKCTL0_FLEXSPI0FCLKDIV_DIV_MASK) != (divider - 1)))
375         {
376             if (BOARD_IS_XIP_FLEXSPI0())
377             {
378                 BOARD_DeinitXip(base);
379             }
380             /* Disable clock before changing clock source */
381             CLKCTL0->PSCCTL0_CLR = CLKCTL0_PSCCTL0_CLR_FLEXSPI0_OTFAD_CLK_MASK;
382             /* Update flexspi clock. */
383             CLKCTL0->FLEXSPI0FCLKSEL = CLKCTL0_FLEXSPI0FCLKSEL_SEL(src);
384             CLKCTL0->FLEXSPI0FCLKDIV |= CLKCTL0_FLEXSPI0FCLKDIV_RESET_MASK; /* Reset the divider counter */
385             CLKCTL0->FLEXSPI0FCLKDIV = CLKCTL0_FLEXSPI0FCLKDIV_DIV(divider - 1);
386             while ((CLKCTL0->FLEXSPI0FCLKDIV) & CLKCTL0_FLEXSPI0FCLKDIV_REQFLAG_MASK)
387             {
388             }
389             /* Enable FLEXSPI clock again */
390             CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI0_OTFAD_CLK_MASK;
391             if (BOARD_IS_XIP_FLEXSPI0())
392             {
393                 BOARD_InitXip(base);
394             }
395         }
396     }
397     else if (base == FLEXSPI1)
398     {
399         if ((CLKCTL0->FLEXSPI1FCLKSEL != CLKCTL0_FLEXSPI1FCLKSEL_SEL(src)) ||
400             ((CLKCTL0->FLEXSPI1FCLKDIV & CLKCTL0_FLEXSPI1FCLKDIV_DIV_MASK) != (divider - 1)))
401         {
402             if (BOARD_IS_XIP_FLEXSPI1())
403             {
404                 BOARD_DeinitXip(base);
405             }
406             /* Disable clock before changing clock source */
407             CLKCTL0->PSCCTL0_CLR = CLKCTL0_PSCCTL0_CLR_FLEXSPI1_CLK_MASK;
408             /* Update flexspi clock. */
409             CLKCTL0->FLEXSPI1FCLKSEL = CLKCTL0_FLEXSPI1FCLKSEL_SEL(src);
410             CLKCTL0->FLEXSPI1FCLKDIV |= CLKCTL0_FLEXSPI1FCLKDIV_RESET_MASK; /* Reset the divider counter */
411             CLKCTL0->FLEXSPI1FCLKDIV = CLKCTL0_FLEXSPI1FCLKDIV_DIV(divider - 1);
412             while ((CLKCTL0->FLEXSPI1FCLKDIV) & CLKCTL0_FLEXSPI1FCLKDIV_REQFLAG_MASK)
413             {
414             }
415             /* Enable FLEXSPI clock again */
416             CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI1_CLK_MASK;
417             if (BOARD_IS_XIP_FLEXSPI1())
418             {
419                 BOARD_InitXip(base);
420             }
421         }
422     }
423     else
424     {
425         return;
426     }
427 }
428 
429 /* This function is used to change FlexSPI clock to a stable source before clock sources(Such as PLL and Main clock)
430  * updating in case XIP(execute code on FLEXSPI memory.) */
BOARD_FlexspiClockSafeConfig(void)431 void BOARD_FlexspiClockSafeConfig(void)
432 {
433     /* Move FLEXSPI clock source from main clock to FRO192M / 2 to avoid instruction/data fetch issue in XIP when
434      * updating PLL and main clock.
435      */
436     BOARD_SetFlexspiClock(FLEXSPI0, 3U, 2);
437 }
438 
439 #if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
BOARD_I2C_Init(I2C_Type * base,uint32_t clkSrc_Hz)440 void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz)
441 {
442     i2c_master_config_t i2cConfig = {0};
443 
444     I2C_MasterGetDefaultConfig(&i2cConfig);
445     I2C_MasterInit(base, &i2cConfig, clkSrc_Hz);
446 }
447 
BOARD_I2C_Send(I2C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subaddressSize,uint8_t * txBuff,uint8_t txBuffSize)448 status_t BOARD_I2C_Send(I2C_Type *base,
449                         uint8_t deviceAddress,
450                         uint32_t subAddress,
451                         uint8_t subaddressSize,
452                         uint8_t *txBuff,
453                         uint8_t txBuffSize)
454 {
455     i2c_master_transfer_t masterXfer;
456 
457     /* Prepare transfer structure. */
458     masterXfer.slaveAddress   = deviceAddress;
459     masterXfer.direction      = kI2C_Write;
460     masterXfer.subaddress     = subAddress;
461     masterXfer.subaddressSize = subaddressSize;
462     masterXfer.data           = txBuff;
463     masterXfer.dataSize       = txBuffSize;
464     masterXfer.flags          = kI2C_TransferDefaultFlag;
465 
466     return I2C_MasterTransferBlocking(base, &masterXfer);
467 }
468 
BOARD_I2C_Receive(I2C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subaddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)469 status_t BOARD_I2C_Receive(I2C_Type *base,
470                            uint8_t deviceAddress,
471                            uint32_t subAddress,
472                            uint8_t subaddressSize,
473                            uint8_t *rxBuff,
474                            uint8_t rxBuffSize)
475 {
476     i2c_master_transfer_t masterXfer;
477 
478     /* Prepare transfer structure. */
479     masterXfer.slaveAddress   = deviceAddress;
480     masterXfer.subaddress     = subAddress;
481     masterXfer.subaddressSize = subaddressSize;
482     masterXfer.data           = rxBuff;
483     masterXfer.dataSize       = rxBuffSize;
484     masterXfer.direction      = kI2C_Read;
485     masterXfer.flags          = kI2C_TransferDefaultFlag;
486 
487     return I2C_MasterTransferBlocking(base, &masterXfer);
488 }
489 #endif
490 
491 #if defined BOARD_USE_CODEC
BOARD_I3C_Init(I3C_Type * base,uint32_t clkSrc_Hz)492 void BOARD_I3C_Init(I3C_Type *base, uint32_t clkSrc_Hz)
493 {
494     i3c_master_config_t i3cConfig;
495 
496     I3C_MasterGetDefaultConfig(&i3cConfig);
497     I3C_MasterInit(base, &i3cConfig, clkSrc_Hz);
498 }
499 
BOARD_I3C_Send(I3C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subaddressSize,uint8_t * txBuff,uint8_t txBuffSize)500 status_t BOARD_I3C_Send(I3C_Type *base,
501                         uint8_t deviceAddress,
502                         uint32_t subAddress,
503                         uint8_t subaddressSize,
504                         uint8_t *txBuff,
505                         uint8_t txBuffSize)
506 {
507     i3c_master_transfer_t masterXfer;
508 
509     /* Prepare transfer structure. */
510     masterXfer.slaveAddress   = deviceAddress;
511     masterXfer.direction      = kI3C_Write;
512     masterXfer.busType        = kI3C_TypeI2C;
513     masterXfer.subaddress     = subAddress;
514     masterXfer.subaddressSize = subaddressSize;
515     masterXfer.data           = txBuff;
516     masterXfer.dataSize       = txBuffSize;
517     masterXfer.flags          = kI3C_TransferDefaultFlag;
518     masterXfer.busType        = kI3C_TypeI2C;
519 
520     return I3C_MasterTransferBlocking(base, &masterXfer);
521 }
522 
BOARD_I3C_Receive(I3C_Type * base,uint8_t deviceAddress,uint32_t subAddress,uint8_t subaddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)523 status_t BOARD_I3C_Receive(I3C_Type *base,
524                            uint8_t deviceAddress,
525                            uint32_t subAddress,
526                            uint8_t subaddressSize,
527                            uint8_t *rxBuff,
528                            uint8_t rxBuffSize)
529 {
530     i3c_master_transfer_t masterXfer;
531 
532     /* Prepare transfer structure. */
533     masterXfer.slaveAddress   = deviceAddress;
534     masterXfer.subaddress     = subAddress;
535     masterXfer.subaddressSize = subaddressSize;
536     masterXfer.data           = rxBuff;
537     masterXfer.dataSize       = rxBuffSize;
538     masterXfer.direction      = kI3C_Read;
539     masterXfer.busType        = kI3C_TypeI2C;
540     masterXfer.flags          = kI3C_TransferDefaultFlag;
541     masterXfer.busType        = kI3C_TypeI2C;
542 
543     return I3C_MasterTransferBlocking(base, &masterXfer);
544 }
545 
BOARD_Codec_I2C_Init(void)546 void BOARD_Codec_I2C_Init(void)
547 {
548 #if BOARD_I3C_CODEC
549     BOARD_I3C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
550 #else
551     BOARD_I2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
552 #endif
553 }
554 
BOARD_Codec_I2C_Send(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,const uint8_t * txBuff,uint8_t txBuffSize)555 status_t BOARD_Codec_I2C_Send(
556     uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
557 {
558 #if BOARD_I3C_CODEC
559     return BOARD_I3C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
560 #else
561     return BOARD_I2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
562 #endif
563                           txBuffSize);
564 }
565 
BOARD_Codec_I2C_Receive(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)566 status_t BOARD_Codec_I2C_Receive(
567     uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
568 {
569 #if BOARD_I3C_CODEC
570     return BOARD_I3C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
571 #else
572     return BOARD_I2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
573 #endif
574 }
575 #endif
576 
577 #if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
BOARD_PMIC_I2C_Init(void)578 void BOARD_PMIC_I2C_Init(void)
579 {
580     BOARD_I2C_Init(BOARD_PMIC_I2C_BASEADDR, BOARD_PMIC_I2C_CLOCK_FREQ);
581 }
582 
BOARD_PMIC_I2C_Send(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,const uint8_t * txBuff,uint8_t txBuffSize)583 status_t BOARD_PMIC_I2C_Send(
584     uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
585 {
586     return BOARD_I2C_Send(BOARD_PMIC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
587                           txBuffSize);
588 }
589 
BOARD_PMIC_I2C_Receive(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)590 status_t BOARD_PMIC_I2C_Receive(
591     uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
592 {
593     return BOARD_I2C_Receive(BOARD_PMIC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
594 }
595 
BOARD_MIPIPanelTouch_I2C_Init(void)596 void BOARD_MIPIPanelTouch_I2C_Init(void)
597 {
598     BOARD_I2C_Init(BOARD_MIPI_PANEL_TOUCH_I2C_BASEADDR, BOARD_MIPI_PANEL_TOUCH_I2C_CLOCK_FREQ);
599 }
600 
BOARD_MIPIPanelTouch_I2C_Send(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,const uint8_t * txBuff,uint8_t txBuffSize)601 status_t BOARD_MIPIPanelTouch_I2C_Send(
602     uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
603 {
604     return BOARD_I2C_Send(BOARD_MIPI_PANEL_TOUCH_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize,
605                           (uint8_t *)txBuff, txBuffSize);
606 }
607 
BOARD_MIPIPanelTouch_I2C_Receive(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)608 status_t BOARD_MIPIPanelTouch_I2C_Receive(
609     uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
610 {
611     return BOARD_I2C_Receive(BOARD_MIPI_PANEL_TOUCH_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
612                              rxBuffSize);
613 }
614 
BOARD_Accel_I2C_Init(void)615 void BOARD_Accel_I2C_Init(void)
616 {
617     BOARD_I2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
618 }
619 
BOARD_Accel_I2C_Send(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint32_t txBuff)620 status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint32_t txBuff)
621 {
622     uint8_t data = (uint8_t)txBuff;
623     return BOARD_I2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, &data, 1);
624 }
625 
BOARD_Accel_I2C_Receive(uint8_t deviceAddress,uint32_t subAddress,uint8_t subAddressSize,uint8_t * rxBuff,uint8_t rxBuffSize)626 status_t BOARD_Accel_I2C_Receive(
627     uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
628 {
629     return BOARD_I2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
630 }
631 #endif /* SDK_I2C_BASED_COMPONENT_USED */
632