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Searched refs:IP_RTU0__MC_CGM (Results 1 – 3 of 3) sorted by relevance

/hal_nxp-3.5.0/s32/drivers/s32ze/BaseNXP/header/
DS32Z2_RTU_MC_CGM.h104 #define IP_RTU0__MC_CGM ((RTU_MC_CGM_Type *)IP_RTU0__MC_CGM_BASE) macro
112 #define IP_RTU_MC_CGM_BASE_PTRS { IP_RTU0__MC_CGM, IP_RTU1__MC_CGM }
/hal_nxp-3.5.0/s32/drivers/s32ze/Mcu/src/
DClock_Ip_Frequency.c2202 …Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_RTU0__MC_CGM->MUX_0_CSS & RTU_MC_CGM_MUX_0_CSS_SELST… in Clock_Ip_Get_RTU0_CORE_CLK_Frequency()
2203 …Frequency &= Clock_Ip_au32EnableDivider[((IP_RTU0__MC_CGM->MUX_0_DC_0 & RTU_MC_CGM_MUX_0_DC_0_DE_M… in Clock_Ip_Get_RTU0_CORE_CLK_Frequency()
2204 …Frequency /= (((IP_RTU0__MC_CGM->MUX_0_DC_0 & RTU_MC_CGM_MUX_0_DC_0_DIV_MASK) >> RTU_MC_CGM_MUX_0_… in Clock_Ip_Get_RTU0_CORE_CLK_Frequency()
3796 …Frequency = Clock_Ip_apfFreqTableClkSrc[((IP_RTU0__MC_CGM->MUX_1_CSS & RTU_MC_CGM_MUX_1_CSS_SELST… in Clock_Ip_Get_RTU0_REG_INTF_CLK_Frequency()
3797 …Frequency &= Clock_Ip_au32EnableDivider[((IP_RTU0__MC_CGM->MUX_1_DC_0 & RTU_MC_CGM_MUX_1_DC_0_DE_M… in Clock_Ip_Get_RTU0_REG_INTF_CLK_Frequency()
3798 …Frequency /= (((IP_RTU0__MC_CGM->MUX_1_DC_0 & RTU_MC_CGM_MUX_1_DC_0_DIV_MASK) >> RTU_MC_CGM_MUX_1_… in Clock_Ip_Get_RTU0_REG_INTF_CLK_Frequency()
DClock_Ip_Data.c495 #if defined(IP_RTU0__MC_CGM)
496 #define CLOCK_IP_RTU0__MC_CGM IP_RTU0__MC_CGM