Searched refs:IP_PERIPH_PLL (Results 1 – 4 of 4) sorted by relevance
251 … if ((IP_PERIPH_PLL->PLLCR & PLLDIG_PLLCR_PLLPD_MASK) != 0U) /* if PERIPH_PLL is not enabled */ in Clock_Ip_SpecificPlatformInitClock()253 …IP_PERIPH_PLL->PLLCLKMUX = 0U; /* FIRC input ref… in Clock_Ip_SpecificPlatformInitClock()254 … IP_PERIPH_PLL->PLLDV = (PLLDIG_PLLDV_RDIV(1U) | PLLDIG_PLLDV_MFI(30U)); /* /1 * 30 */ in Clock_Ip_SpecificPlatformInitClock()255 …IP_PERIPH_PLL->PLLFD &= ~(PLLDIG_PLLFD_MFN_MASK | PLLDIG_PLLFD_SDMEN_MASK); /* Disable modula… in Clock_Ip_SpecificPlatformInitClock()256 …IP_PERIPH_PLL->PLLCR &= ~PLLDIG_PLLCR_PLLPD_MASK; /* Start PERIPH_P… in Clock_Ip_SpecificPlatformInitClock()301 … if ((IP_PERIPH_PLL->PLLCR & PLLDIG_PLLCR_PLLPD_MASK) != 0U) /* if PERIPH_PLL is not enabled */ in Clock_Ip_SpecificPlatformInitClock()303 …IP_PERIPH_PLL->PLLCLKMUX = 0U; /* FIRC input ref… in Clock_Ip_SpecificPlatformInitClock()304 … IP_PERIPH_PLL->PLLDV = (PLLDIG_PLLDV_RDIV(1U) | PLLDIG_PLLDV_MFI(30U)); /* /1 * 30 */ in Clock_Ip_SpecificPlatformInitClock()305 …IP_PERIPH_PLL->PLLFD &= ~(PLLDIG_PLLFD_MFN_MASK | PLLDIG_PLLFD_SDMEN_MASK); /* Disable modula… in Clock_Ip_SpecificPlatformInitClock()306 …IP_PERIPH_PLL->PLLCR &= ~PLLDIG_PLLCR_PLLPD_MASK; /* Start PERIPH_P… in Clock_Ip_SpecificPlatformInitClock()
1393 …if (Clock_Ip_u32PeriphPllChecksum != (IP_PERIPH_PLL->PLLCLKMUX ^ IP_PERIPH_PLL->PLLDV ^ IP_PERIPH_… in Clock_Ip_Get_PERIPHPLL_CLK_Frequency()1395 …Clock_Ip_u32PeriphPllChecksum = (IP_PERIPH_PLL->PLLCLKMUX ^ IP_PERIPH_PLL->PLLDV ^ IP_PERIPH_PLL->… in Clock_Ip_Get_PERIPHPLL_CLK_Frequency()1396 Clock_Ip_u32PeriphPllFreq = PLL_VCO(IP_PERIPH_PLL); in Clock_Ip_Get_PERIPHPLL_CLK_Frequency()1398 …return (((IP_PERIPH_PLL->PLLSR & PLLDIG_PLLSR_LOCK_MASK) >> PLLDIG_PLLSR_LOCK_SHIFT) != 0U) ? Cloc… in Clock_Ip_Get_PERIPHPLL_CLK_Frequency()1483 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DE_MASK) >> … in Clock_Ip_Get_PERIPHPLL_PHI0_Frequency()1484 …Frequency /= (((IP_PERIPH_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT)… in Clock_Ip_Get_PERIPHPLL_PHI0_Frequency()1492 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[1U] & PLLDIG_PLLODIV_DE_MASK) >> … in Clock_Ip_Get_PERIPHPLL_PHI1_Frequency()1493 …Frequency /= (((IP_PERIPH_PLL->PLLODIV[1U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT)… in Clock_Ip_Get_PERIPHPLL_PHI1_Frequency()1500 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[2U] & PLLDIG_PLLODIV_DE_MASK) >> … in Clock_Ip_Get_PERIPHPLL_PHI2_Frequency()1501 …Frequency /= (((IP_PERIPH_PLL->PLLODIV[2U] & PLLDIG_PLLODIV_DIV_MASK) >> PLLDIG_PLLODIV_DIV_SHIFT)… in Clock_Ip_Get_PERIPHPLL_PHI2_Frequency()[all …]
2887 IP_PERIPH_PLL,
102 #define IP_PERIPH_PLL ((PLLDIG_Type *)IP_PERIPH_PLL_BASE) macro106 #define IP_PLLDIG_BASE_PTRS { IP_CORE_PLL, IP_DDR_PLL, IP_PERIPH_PLL }
