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Searched refs:GPC_IMR_IMR4_MASK (Results 1 – 13 of 13) sorted by relevance

/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/gpc_2/
Dfsl_gpc.h38 #define GPC_IMR_IMR4_MASK GPC_IMR_M4_IMR4_M4_MASK macro
71 #define GPC_IMR_IMR4_MASK GPC_IMR_M7_IMR4_M7_MASK macro
Dfsl_gpc.c43 base->GPC_IMR[3U] = GPC_IMR_IMR4_MASK; in GPC_Init()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h17221 #define GPC_IMR_IMR4_MASK (0xFFFFFFFFU) macro
17223 … (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h14646 #define GPC_IMR_IMR4_MASK (0xFFFFFFFFU) macro
14648 … (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h20683 #define GPC_IMR_IMR4_MASK (0xFFFFFFFFU) macro
20685 … (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h20667 #define GPC_IMR_IMR4_MASK (0xFFFFFFFFU) macro
20669 … (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h22984 #define GPC_IMR_IMR4_MASK (0xFFFFFFFFU) macro
22986 … (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h21613 #define GPC_IMR_IMR4_MASK (0xFFFFFFFFU) macro
21615 … (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h22398 #define GPC_IMR_IMR4_MASK (0xFFFFFFFFU) macro
22400 … (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h23363 #define GPC_IMR_IMR4_MASK (0xFFFFFFFFU) macro
23365 … (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h22986 #define GPC_IMR_IMR4_MASK (0xFFFFFFFFU) macro
22988 … (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h24149 #define GPC_IMR_IMR4_MASK (0xFFFFFFFFU) macro
24151 … (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h24212 #define GPC_IMR_IMR4_MASK (0xFFFFFFFFU) macro
24214 … (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR4_SHIFT)) & GPC_IMR_IMR4_MASK)