1 /*
2 * Copyright 2017-2020, NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include "fsl_gpc.h"
10
11 /*******************************************************************************
12 * Definitions
13 ******************************************************************************/
14
15 /* Component ID definition, used by tools. */
16 #ifndef FSL_COMPONENT_ID
17 #define FSL_COMPONENT_ID "platform.drivers.gpc_2"
18 #endif
19
20 /*******************************************************************************
21 * Variables
22 ******************************************************************************/
23
24 /*******************************************************************************
25 * Code
26 ******************************************************************************/
27 /*!
28 * brief GPC init function.
29 *
30 * param base GPC peripheral base address.
31 * param powerUpSlot power up slot number.
32 * param powerDownSlot power down slot number.
33 */
GPC_Init(GPC_Type * base,uint32_t powerUpSlot,uint32_t powerDownSlot)34 void GPC_Init(GPC_Type *base, uint32_t powerUpSlot, uint32_t powerDownSlot)
35 {
36 assert(powerUpSlot < GPC_PCG_TIME_SLOT_TOTAL_NUMBER);
37 assert(powerDownSlot < GPC_PCG_TIME_SLOT_TOTAL_NUMBER);
38
39 /* Disable all interrupt */
40 base->GPC_IMR[0U] = GPC_IMR_IMR1_MASK;
41 base->GPC_IMR[1U] = GPC_IMR_IMR2_MASK;
42 base->GPC_IMR[2U] = GPC_IMR_IMR3_MASK;
43 base->GPC_IMR[3U] = GPC_IMR_IMR4_MASK;
44 #if (defined(GPC_IMR_M7_COUNT) && (GPC_IMR_M7_COUNT == 5U))
45 base->GPC_IMR[4U] = GPC_IMR_IMR5_MASK;
46 #endif /* GPC_IMR_M7_COUNT */
47
48 /* Not mask power down request */
49 base->MISC |= GPC_MISC_PDN_REQ_MASK_MASK;
50 /* Select virtual PGC ack */
51 base->GPC_PGC_ACK_SEL |= (uint32_t)kGPC_VirtualPGCPowerUpAck | (uint32_t)kGPC_VirtualPGCPowerDownAck;
52 /* Slot configurations */
53 #if !(defined(GPC_SLT_CFG_PU1_COUNT) && GPC_SLT_CFG_PU1_COUNT)
54 base->SLT_CFG_PU[powerDownSlot] |= GPC_SLT_CFG_PU_PDN_SLOT_CONTROL_MASK;
55 base->SLT_CFG_PU[powerUpSlot] |= GPC_SLT_CFG_PU_PUP_SLOT_CONTROL_MASK;
56 #else
57 base->SLTn_CFG_PU[powerDownSlot].SLT_CFG_PU1 |= GPC_SLT_CFG_PU_PDN_SLOT_CONTROL_MASK;
58 base->SLTn_CFG_PU[powerUpSlot].SLT_CFG_PU1 |= GPC_SLT_CFG_PU_PUP_SLOT_CONTROL_MASK;
59 #endif /* GPC_SLT_CFG_PU1_COUNT */
60
61 #if defined(FSL_FEATURE_GPC_HAS_PGC_MF) && FSL_FEATURE_GPC_HAS_PGC_MF
62 base->SLT_CFG_PU[powerDownSlot] |= GPC_SLT_CFG_PU_MF_PDN_SLOT_CONTROL_MASK;
63 base->SLT_CFG_PU[powerUpSlot] |= GPC_SLT_CFG_PU_MF_PUP_SLOT_CONTROL_MASK;
64 /* Mapping PGC power up/down slot to fastmix/megamix PGC power up/down slow */
65 base->PGC_CPU_0_1_MAPPING = GPC_PGC_CPU_0_1_MAPPING_MF_DOMAIN_MASK;
66 #endif /* FSL_FEATURE_GPC_HAS_PGC_MF */
67 }
68
69 /*!
70 * brief Enable the IRQ.
71 *
72 * param base GPC peripheral base address.
73 * param irqId ID number of IRQ to be enabled, available range is 0-127,reference SOC headerfile IRQn_Type.
74 */
GPC_EnableIRQ(GPC_Type * base,uint32_t irqId)75 void GPC_EnableIRQ(GPC_Type *base, uint32_t irqId)
76 {
77 uint32_t irqRegNum = irqId / 32U;
78 uint32_t irqRegShiftNum = irqId % 32U;
79
80 assert(irqRegNum < GPC_IMR_COUNT);
81
82 base->GPC_IMR[irqRegNum] &= ~(1UL << irqRegShiftNum);
83 }
84
85 /*!
86 * brief Disable the IRQ.
87 *
88 * param base GPC peripheral base address.
89 * param irqId ID number of IRQ to be disabled, available range is 0-127,reference SOC headerfile IRQn_Type.
90 */
GPC_DisableIRQ(GPC_Type * base,uint32_t irqId)91 void GPC_DisableIRQ(GPC_Type *base, uint32_t irqId)
92 {
93 uint32_t irqRegNum = irqId / 32U;
94 uint32_t irqRegShiftNum = irqId % 32U;
95
96 assert(irqRegNum < GPC_IMR_COUNT);
97
98 base->GPC_IMR[irqRegNum] |= (1UL << irqRegShiftNum);
99 }
100
101 /*!
102 * brief Get the IRQ/Event flag.
103 *
104 * param base GPC peripheral base address.
105 * param irqId ID number of IRQ to be enabled, available range is 0-127,reference SOC headerfile IRQn_Type.
106 * return Indicated IRQ/Event is asserted or not.
107 */
GPC_GetIRQStatusFlag(GPC_Type * base,uint32_t irqId)108 bool GPC_GetIRQStatusFlag(GPC_Type *base, uint32_t irqId)
109 {
110 uint32_t isrRegNum = irqId / 32U;
111 uint32_t isrRegShiftNum = irqId % 32U;
112 uint32_t ret;
113
114 assert(isrRegNum < GPC_IMR_COUNT);
115
116 ret = base->GPC_ISR[isrRegNum] & (1UL << isrRegShiftNum);
117
118 return (1UL << isrRegShiftNum) == ret;
119 }
120
121 /*!
122 * brief Enter WAIT mode.
123 *
124 * param base GPC peripheral base address.
125 * param config lpm mode configurations.
126 */
GPC_EnterWaitMode(GPC_Type * base,gpc_lpm_config_t * config)127 void GPC_EnterWaitMode(GPC_Type *base, gpc_lpm_config_t *config)
128 {
129 uint32_t lpcr = (base->GPC_LPCR) & (~GPC_LPCR_LPM0_MASK);
130 uint32_t slpcr = base->SLPCR;
131
132 if (config != NULL)
133 {
134 lpcr &= ~(GPC_LPCR_CPU_CLK_ON_LPM_MASK | GPC_LPCR_EN_PUP_MASK | GPC_LPCR_EN_PDN_MASK);
135 lpcr |= (config->enCpuClk ? (uint32_t)GPC_LPCR_CPU_CLK_ON_LPM_MASK : 0UL) |
136 (config->enVirtualPGCPowerup ? (uint32_t)GPC_LPCR_EN_PUP_MASK : 0UL) |
137 (config->enVirtualPGCPowerdown ? (uint32_t)GPC_LPCR_EN_PDN_MASK : 0UL) |
138 (config->enWfiMask ? (uint32_t)GPC_LPCR_MASK_WFI_MASK : 0UL) |
139 (config->enDsmMask ? (uint32_t)GPC_LPCR_MASK_DSM_TRIGGER_MASK : 0UL);
140 slpcr &= ~GPC_SLPCR_EN_FASTWUP_WAIT_MODE_MASK;
141 slpcr |= config->enFastWakeUp ? GPC_SLPCR_EN_FASTWUP_WAIT_MODE_MASK : 0U;
142 }
143
144 base->SLPCR = slpcr;
145 /* WAIT mode */
146 base->GPC_LPCR = lpcr | (uint32_t)kGPC_WaitMode;
147 }
148
149 /*!
150 * brief Enter STOP mode.
151 *
152 * param base GPC peripheral base address.
153 * param config lpm mode configurations.
154 */
GPC_EnterStopMode(GPC_Type * base,gpc_lpm_config_t * config)155 void GPC_EnterStopMode(GPC_Type *base, gpc_lpm_config_t *config)
156 {
157 uint32_t lpcr = (base->GPC_LPCR) & (~GPC_LPCR_LPM0_MASK);
158 uint32_t slpcr = base->SLPCR;
159
160 if (config != NULL)
161 {
162 lpcr &= ~(GPC_LPCR_CPU_CLK_ON_LPM_MASK | GPC_LPCR_EN_PUP_MASK | GPC_LPCR_EN_PDN_MASK);
163 lpcr |= (config->enCpuClk ? (uint32_t)GPC_LPCR_CPU_CLK_ON_LPM_MASK : 0UL) |
164 (config->enVirtualPGCPowerup ? (uint32_t)GPC_LPCR_EN_PUP_MASK : 0UL) |
165 (config->enVirtualPGCPowerdown ? (uint32_t)GPC_LPCR_EN_PDN_MASK : 0UL) |
166 (config->enWfiMask ? (uint32_t)GPC_LPCR_MASK_WFI_MASK : 0UL) |
167 (config->enDsmMask ? (uint32_t)GPC_LPCR_MASK_DSM_TRIGGER_MASK : 0UL);
168 slpcr &= ~GPC_SLPCR_EN_FASTWUP_STOP_MODE_MASK;
169 slpcr |= config->enFastWakeUp ? GPC_SLPCR_EN_FASTWUP_STOP_MODE_MASK : 0U;
170 }
171
172 base->SLPCR = slpcr;
173 /* STOP mode */
174 base->GPC_LPCR = lpcr | (uint32_t)kGPC_StopMode;
175 }
176
