1 /*
2 * Copyright 2017-2020, NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef _FSL_GPC_H_
10 #define _FSL_GPC_H_
11
12 #include "fsl_common.h"
13
14 /*!
15 * @addtogroup gpc
16 * @{
17 */
18
19 /*******************************************************************************
20 * Definitions
21 ******************************************************************************/
22
23 /*! @name Driver version */
24 /*@{*/
25 /*! @brief GPC driver version 2.2.0. */
26 #define FSL_GPC_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
27 /*@}*/
28
29 /* Re-map the register and bitfields name for different ARM cortex M cores. */
30 #if defined __CORTEX_M && (__CORTEX_M == 4U)
31 #define GPC_PGC_CPU_0_1_MAPPING_MF_DOMAIN_MASK GPC_PGC_CPU_0_1_MAPPING_MF_M4_DOMAIN_MASK
32
33 #define GPC_IMR IMR_M4
34 #define GPC_IMR_COUNT GPC_IMR_M4_COUNT
35 #define GPC_IMR_IMR1_MASK GPC_IMR_M4_IMR1_M4_MASK
36 #define GPC_IMR_IMR2_MASK GPC_IMR_M4_IMR2_M4_MASK
37 #define GPC_IMR_IMR3_MASK GPC_IMR_M4_IMR3_M4_MASK
38 #define GPC_IMR_IMR4_MASK GPC_IMR_M4_IMR4_M4_MASK
39
40 #define GPC_ISR ISR_M4
41
42 #define GPC_LPCR LPCR_M4
43 #define GPC_LPCR_CPU_CLK_ON_LPM_MASK GPC_LPCR_M4_CPU_CLK_ON_LPM_MASK
44 #define GPC_LPCR_EN_PDN_MASK GPC_LPCR_M4_EN_M4_PDN_MASK
45 #define GPC_LPCR_EN_PUP_MASK GPC_LPCR_M4_EN_M4_PUP_MASK
46 #define GPC_LPCR_LPM0_MASK GPC_LPCR_M4_LPM0_MASK
47 #define GPC_LPCR_MASK_DSM_TRIGGER_MASK GPC_LPCR_M4_MASK_DSM_TRIGGER_MASK
48 #define GPC_LPCR_MASK_WFI_MASK GPC_LPCR_M4_MASK_M4_WFI_MASK
49
50 #define GPC_MISC_PDN_REQ_MASK_MASK GPC_MISC_M4_PDN_REQ_MASK_MASK
51
52 #define GPC_PGC_ACK_SEL PGC_ACK_SEL_M4
53 #define GPC_PGC_ACK_SEL_DUMMY_PGC_PUP_ACK_MASK GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PUP_ACK_MASK
54 #define GPC_PGC_ACK_SEL_VIRTUAL_PGC_PUP_ACK_MASK GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PUP_ACK_MASK
55 #define GPC_PGC_ACK_SEL_DUMMY_PGC_PDN_ACK_MASK GPC_PGC_ACK_SEL_M4_M4_DUMMY_PGC_PDN_ACK_MASK
56 #define GPC_PGC_ACK_SEL_VIRTUAL_PGC_PDN_ACK_MASK GPC_PGC_ACK_SEL_M4_M4_VIRTUAL_PGC_PDN_ACK_MASK
57 #define GPC_PGC_ACK_SEL_NOC_PGC_PUP_ACK GPC_PGC_ACK_SEL_M4_NOC_PGC_PUP_ACK_MASK
58 #define GPC_PGC_ACK_SEL_NOC_PGC_PDN_ACK GPC_PGC_ACK_SEL_M4_NOC_PGC_PDN_ACK_MASK
59
60 #define GPC_SLPCR_EN_FASTWUP_WAIT_MODE_MASK GPC_SLPCR_EN_M4_FASTWUP_WAIT_MODE_MASK
61 #define GPC_SLPCR_EN_FASTWUP_STOP_MODE_MASK GPC_SLPCR_EN_M4_FASTWUP_STOP_MODE_MASK
62
63 #define GPC_SLT_CFG_PU_PDN_SLOT_CONTROL_MASK GPC_SLT_CFG_PU_M4_PDN_SLOT_CONTROL_MASK
64 #define GPC_SLT_CFG_PU_PUP_SLOT_CONTROL_MASK GPC_SLT_CFG_PU_M4_PUP_SLOT_CONTROL_MASK
65 #elif defined __CORTEX_M && (__CORTEX_M == 7U)
66 #define GPC_IMR IMR_M7
67 #define GPC_IMR_COUNT GPC_IMR_M7_COUNT
68 #define GPC_IMR_IMR1_MASK GPC_IMR_M7_IMR1_M7_MASK
69 #define GPC_IMR_IMR2_MASK GPC_IMR_M7_IMR2_M7_MASK
70 #define GPC_IMR_IMR3_MASK GPC_IMR_M7_IMR3_M7_MASK
71 #define GPC_IMR_IMR4_MASK GPC_IMR_M7_IMR4_M7_MASK
72 #if (defined(GPC_IMR_M7_COUNT) && (GPC_IMR_M7_COUNT == 5U))
73 #define GPC_IMR_IMR5_MASK GPC_IMR_M7_IMR5_M7_MASK
74 #endif
75
76 #define GPC_ISR ISR_M7
77
78 #define GPC_LPCR LPCR_M7
79 #define GPC_LPCR_CPU_CLK_ON_LPM_MASK GPC_LPCR_M7_CPU_CLK_ON_LPM_MASK
80 #define GPC_LPCR_EN_PDN_MASK GPC_LPCR_M7_EN_M7_PDN_MASK
81 #define GPC_LPCR_EN_PUP_MASK GPC_LPCR_M7_EN_M7_PUP_MASK
82 #define GPC_LPCR_LPM0_MASK GPC_LPCR_M7_LPM0_MASK
83 #define GPC_LPCR_MASK_DSM_TRIGGER_MASK GPC_LPCR_M7_MASK_DSM_TRIGGER_MASK
84 #define GPC_LPCR_MASK_WFI_MASK GPC_LPCR_M7_MASK_M7_WFI_MASK
85
86 #define GPC_MISC_PDN_REQ_MASK_MASK GPC_MISC_M7_PDN_REQ_MASK_MASK
87
88 #define GPC_PGC_ACK_SEL PGC_ACK_SEL_M7
89 #define GPC_PGC_ACK_SEL_DUMMY_PGC_PUP_ACK_MASK GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PUP_ACK_MASK
90 #define GPC_PGC_ACK_SEL_VIRTUAL_PGC_PUP_ACK_MASK GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PUP_ACK_MASK
91 #define GPC_PGC_ACK_SEL_DUMMY_PGC_PDN_ACK_MASK GPC_PGC_ACK_SEL_M7_M7_DUMMY_PGC_PDN_ACK_MASK
92 #define GPC_PGC_ACK_SEL_VIRTUAL_PGC_PDN_ACK_MASK GPC_PGC_ACK_SEL_M7_M7_VIRTUAL_PGC_PDN_ACK_MASK
93 #define GPC_PGC_ACK_SEL_NOC_PGC_PUP_ACK GPC_PGC_ACK_SEL_M7_NOC_PGC_PUP_ACK_MASK
94 #define GPC_PGC_ACK_SEL_NOC_PGC_PDN_ACK GPC_PGC_ACK_SEL_M7_NOC_PGC_PDN_ACK_MASK
95
96 #define GPC_SLPCR_EN_FASTWUP_WAIT_MODE_MASK GPC_SLPCR_EN_M7_FASTWUP_WAIT_MODE_MASK
97 #define GPC_SLPCR_EN_FASTWUP_STOP_MODE_MASK GPC_SLPCR_EN_M7_FASTWUP_STOP_MODE_MASK
98
99 #if !(defined(GPC_SLT_CFG_PU1_COUNT) && GPC_SLT_CFG_PU1_COUNT)
100 #define GPC_SLT_CFG_PU_PDN_SLOT_CONTROL_MASK GPC_SLT_CFG_PU_M7_PDN_SLOT_CONTROL_MASK
101 #define GPC_SLT_CFG_PU_PUP_SLOT_CONTROL_MASK GPC_SLT_CFG_PU_M7_PUP_SLOT_CONTROL_MASK
102 #else
103 #define GPC_SLT_CFG_PU_PDN_SLOT_CONTROL_MASK GPC_SLT_CFG_PU1_M7_PDN_SLOT_CONTROL_MASK
104 #define GPC_SLT_CFG_PU_PUP_SLOT_CONTROL_MASK GPC_SLT_CFG_PU1_M7_PUP_SLOT_CONTROL_MASK
105 #endif /* GPC_SLT_CFG_PU1_COUNT */
106 #endif
107
108 /*! @brief Total number of the timeslot */
109 #define GPC_PCG_TIME_SLOT_TOTAL_NUMBER GPC_SLT_CFG_PU_COUNT
110
111 /*! @brief GPC LPM mode definition */
112 enum _gpc_lpm_mode
113 {
114 kGPC_RunMode = 0U, /*!< run mode */
115 kGPC_WaitMode = 1U, /*!< wait mode */
116 kGPC_StopMode = 2U, /*!< stop mode */
117 };
118
119 /*! @brief PGC ack signal selection */
120 enum _gpc_pgc_ack_sel
121 {
122 kGPC_DummyPGCPowerUpAck = GPC_PGC_ACK_SEL_DUMMY_PGC_PUP_ACK_MASK, /*!< dummy power up ack signal */
123 kGPC_VirtualPGCPowerUpAck = GPC_PGC_ACK_SEL_VIRTUAL_PGC_PUP_ACK_MASK, /*!< virtual pgc power up ack signal */
124 kGPC_DummyPGCPowerDownAck = GPC_PGC_ACK_SEL_DUMMY_PGC_PDN_ACK_MASK, /*!< dummy power down ack signal */
125 kGPC_VirtualPGCPowerDownAck = GPC_PGC_ACK_SEL_VIRTUAL_PGC_PDN_ACK_MASK, /*!< virtual pgc power down ack signal */
126 kGPC_NocPGCPowerUpAck = GPC_PGC_ACK_SEL_NOC_PGC_PUP_ACK, /*!< NOC power up ack signal */
127 kGPC_NocPGCPowerDownAck = GPC_PGC_ACK_SEL_NOC_PGC_PDN_ACK, /*!< NOC power */
128 };
129
130 /*! @brief Standby counter which GPC will wait between PMIC_STBY_REQ negation and assertion of PMIC_READY */
131 enum _gpc_standby_count
132 {
133 kGPC_StandbyCounter4CkilClk = 0U, /*!< 4 ckil clocks */
134 kGPC_StandbyCounter8CkilClk = 1U, /*!< 8 ckil clocks */
135 kGPC_StandbyCounter16CkilClk = 2U, /*!< 16 ckil clocks */
136 kGPC_StandbyCounter32CkilClk = 3U, /*!< 32 ckil clocks */
137 kGPC_StandbyCounter64CkilClk = 4U, /*!< 64 ckil clocks */
138 kGPC_StandbyCounter128CkilClk = 5U, /*!< 128 ckil clocks */
139 kGPC_StandbyCounter256CkilClk = 6U, /*!< 256 ckil clocks */
140 kGPC_StandbyCounter512CkilClk = 7U, /*!< 512 ckil clocks */
141 };
142
143 /*!< configuration for enter LPM mode */
144 typedef struct _gpc_lpm_config
145 {
146 bool enFastWakeUp; /*!< enable fast wake up from lpm mode */
147 bool enCpuClk; /*!< enable CPU clock when LPM enter */
148 bool enVirtualPGCPowerup; /*!< enable virtual PGC power up with LPM enter */
149 bool enVirtualPGCPowerdown; /*!< enable virtual PGC power down with LPM enter */
150 bool enWfiMask; /*!< enable WFI Mask */
151 bool enDsmMask; /*!< enable DSM Mask */
152 } gpc_lpm_config_t;
153
154 /*!< configuration for enter DSM mode */
155 typedef struct _gpc_dsm_config
156 {
157 bool disableRamLpctl; /*!< Memory can be defined to go to retention mode or not */
158
159 bool enPMICStandBy; /*!< PMIC can be defined to be stand-by mode or not */
160 uint8_t pmicStandByCounter; /*!< PMIC standby counter, reference _gpc_standby_count */
161 uint8_t regBypassCounter; /*!< if PMIC standby is request, regulator bypass should be enable, and the counter can be
162 defined */
163
164 } gpc_dsm_config_t;
165
166 #if defined(__cplusplus)
167 extern "C" {
168 #endif
169
170 /*******************************************************************************
171 * API
172 ******************************************************************************/
173
174 /*!
175 * @brief Allow all the IRQ/Events within the charge of GPC.
176 *
177 * @param base GPC peripheral base address.
178 */
GPC_AllowIRQs(GPC_Type * base)179 static inline void GPC_AllowIRQs(GPC_Type *base)
180 {
181 base->MISC &= ~GPC_MISC_GPC_IRQ_MASK_MASK; /* Events would not be masked. */
182 }
183
184 /*!
185 * @brief Disallow all the IRQ/Events within the charge of GPC.
186 *
187 * @param base GPC peripheral base address.
188 */
GPC_DisallowIRQs(GPC_Type * base)189 static inline void GPC_DisallowIRQs(GPC_Type *base)
190 {
191 base->MISC |= GPC_MISC_GPC_IRQ_MASK_MASK; /* Mask all the events. */
192 }
193
194 /*!
195 * @brief Get current LPM mode.
196 *
197 * @param base GPC peripheral base address.
198 * @retval lpm mode, reference _gpc_lpm_mode
199 */
GPC_GetLpmMode(GPC_Type * base)200 static inline uint32_t GPC_GetLpmMode(GPC_Type *base)
201 {
202 return base->GPC_LPCR & GPC_LPCR_LPM0_MASK;
203 }
204
205 /*!
206 * @brief Enable the IRQ.
207 *
208 * @param base GPC peripheral base address.
209 * @param irqId ID number of IRQ to be enabled, available range is 0-127,reference SOC headerfile IRQn_Type.
210 */
211 void GPC_EnableIRQ(GPC_Type *base, uint32_t irqId);
212
213 /*!
214 * @brief Disable the IRQ.
215 *
216 * @param base GPC peripheral base address.
217 * @param irqId ID number of IRQ to be disabled, available range is 0-127,reference SOC headerfile IRQn_Type.
218 */
219 void GPC_DisableIRQ(GPC_Type *base, uint32_t irqId);
220
221 /*!
222 * @brief Get the IRQ/Event flag.
223 *
224 * @param base GPC peripheral base address.
225 * @param irqId ID number of IRQ to be enabled, available range is 0-127,reference SOC headerfile IRQn_Type.
226 * @return Indicated IRQ/Event is asserted or not.
227 */
228 bool GPC_GetIRQStatusFlag(GPC_Type *base, uint32_t irqId);
229
230 /*!
231 * @brief Mask the DSM trigger.
232 *
233 * @param base GPC peripheral base address.
234 * @param enable true to enable mask, false to disable mask.
235 */
GPC_DsmTriggerMask(GPC_Type * base,bool enable)236 static inline void GPC_DsmTriggerMask(GPC_Type *base, bool enable)
237 {
238 if (enable)
239 {
240 base->GPC_LPCR |= GPC_LPCR_MASK_DSM_TRIGGER_MASK;
241 }
242 else
243 {
244 base->GPC_LPCR &= ~GPC_LPCR_MASK_DSM_TRIGGER_MASK;
245 }
246 }
247
248 /*!
249 * @brief Mask the WFI.
250 *
251 * @param base GPC peripheral base address.
252 * @param enable true to enable mask, false to disable mask.
253 */
GPC_WFIMask(GPC_Type * base,bool enable)254 static inline void GPC_WFIMask(GPC_Type *base, bool enable)
255 {
256 if (enable)
257 {
258 base->GPC_LPCR |= GPC_LPCR_MASK_WFI_MASK;
259 }
260 else
261 {
262 base->GPC_LPCR &= ~GPC_LPCR_MASK_WFI_MASK;
263 }
264 }
265
266 /*!
267 * @brief Select the PGC ACK signal.
268 *
269 * @param base GPC peripheral base address.
270 * @param mask reference _gpc_pgc_ack_sel.
271 */
GPC_SelectPGCAckSignal(GPC_Type * base,uint32_t mask)272 static inline void GPC_SelectPGCAckSignal(GPC_Type *base, uint32_t mask)
273 {
274 base->GPC_PGC_ACK_SEL |= mask;
275 }
276
277 /*!
278 * @brief Power down request to virtual PGC mask or not.
279 *
280 * @param base GPC peripheral base address.
281 * @param enable true to mask, false to not mask.
282 */
GPC_PowerDownRequestMask(GPC_Type * base,bool enable)283 static inline void GPC_PowerDownRequestMask(GPC_Type *base, bool enable)
284 {
285 if (enable)
286 {
287 base->MISC &= ~GPC_MISC_PDN_REQ_MASK_MASK;
288 }
289 else
290 {
291 base->MISC |= GPC_MISC_PDN_REQ_MASK_MASK;
292 }
293 }
294
295 /*!
296 * @brief PGC CPU Mapping.
297 *
298 * @param base GPC peripheral base address.
299 * @param mask mask value reference PGC CPU mapping definition.
300 */
GPC_PGCMapping(GPC_Type * base,uint32_t mask)301 static inline void GPC_PGCMapping(GPC_Type *base, uint32_t mask)
302 {
303 #if !(defined(GPC_PGC_CPU_M7_MAPPING_MIX0_SUPERMIXM7_DOMAIN_MASK) && GPC_PGC_CPU_M7_MAPPING_MIX0_SUPERMIXM7_DOMAIN_MASK)
304 base->PGC_CPU_0_1_MAPPING |= mask & 0xFFFD0000U;
305 #else
306 base->PGC_CPU_M7_MAPPING |= mask & 0x3FFFFFUL;
307 #endif /* GPC_PGC_CPU_M7_MAPPING_MIX0_SUPERMIXM7_DOMAIN_MASK */
308 }
309
310 /*!
311 * @brief Time slot configure.
312 *
313 * @param base GPC peripheral base address.
314 * @param slotIndex time slot index.
315 * @param value value to be configured
316 */
GPC_TimeSlotConfigureForPUS(GPC_Type * base,uint8_t slotIndex,uint32_t value)317 static inline void GPC_TimeSlotConfigureForPUS(GPC_Type *base, uint8_t slotIndex, uint32_t value)
318 {
319 assert(slotIndex < GPC_PCG_TIME_SLOT_TOTAL_NUMBER);
320
321 #if !(defined(GPC_SLT_CFG_PU1_COUNT) && GPC_SLT_CFG_PU1_COUNT)
322 base->SLT_CFG_PU[slotIndex] |= value;
323 #else
324 base->SLTn_CFG_PU[slotIndex].SLT_CFG_PU = value;
325 #endif /* GPC_SLT_CFG_PU1_COUNT */
326 }
327
328 #if defined(GPC_SLT_CFG_PU1_COUNT) && GPC_SLT_CFG_PU1_COUNT
329 /*!
330 * @brief Time slot configure of extended PUs
331 *
332 * @param base GPC peripheral base address.
333 * @param slotIndex Time slot index.
334 * @param value The value of extended PUs, please refer to the reference manual for details.
335 */
GPC_TimeSlotConfigureForExtendedPUS(GPC_Type * base,uint8_t slotIndex,uint32_t value)336 static inline void GPC_TimeSlotConfigureForExtendedPUS(GPC_Type *base, uint8_t slotIndex, uint32_t value)
337 {
338 assert(slotIndex < GPC_PCG_TIME_SLOT_TOTAL_NUMBER);
339
340 base->SLTn_CFG_PU[slotIndex].SLT_CFG_PU1 = value;
341 }
342 #endif /* GPC_SLT_CFG_PU1_COUNT */
343
344 /*!
345 * @brief Enter WAIT mode.
346 *
347 * @param base GPC peripheral base address.
348 * @param config lpm mode configurations.
349 */
350 void GPC_EnterWaitMode(GPC_Type *base, gpc_lpm_config_t *config);
351
352 /*!
353 * @brief Enter STOP mode.
354 *
355 * @param base GPC peripheral base address.
356 * @param config lpm mode configurations.
357 */
358 void GPC_EnterStopMode(GPC_Type *base, gpc_lpm_config_t *config);
359
360 /*!
361 * @brief GPC init function.
362 *
363 * @param base GPC peripheral base address.
364 * @param powerUpSlot power up slot number.
365 * @param powerDownSlot power down slot number.
366 */
367 void GPC_Init(GPC_Type *base, uint32_t powerUpSlot, uint32_t powerDownSlot);
368
369 #if defined(__cplusplus)
370 }
371 #endif
372 /*!
373 * @}
374 */
375 #endif /* _FSL_GPC_H_ */
376
