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Searched refs:GPC_IMR_IMR1_MASK (Results 1 – 13 of 13) sorted by relevance

/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/gpc_2/
Dfsl_gpc.h35 #define GPC_IMR_IMR1_MASK GPC_IMR_M4_IMR1_M4_MASK macro
68 #define GPC_IMR_IMR1_MASK GPC_IMR_M7_IMR1_M7_MASK macro
Dfsl_gpc.c40 base->GPC_IMR[0U] = GPC_IMR_IMR1_MASK; in GPC_Init()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1015/
DMIMXRT1015.h17209 #define GPC_IMR_IMR1_MASK (0xFFFFFFFFU) macro
17211 … (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1011/
DMIMXRT1011.h14634 #define GPC_IMR_IMR1_MASK (0xFFFFFFFFU) macro
14636 … (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1021/
DMIMXRT1021.h20671 #define GPC_IMR_IMR1_MASK (0xFFFFFFFFU) macro
20673 … (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1024/
DMIMXRT1024.h20655 #define GPC_IMR_IMR1_MASK (0xFFFFFFFFU) macro
20657 … (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1041/
DMIMXRT1041.h22972 #define GPC_IMR_IMR1_MASK (0xFFFFFFFFU) macro
22974 … (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1051/
DMIMXRT1051.h21601 #define GPC_IMR_IMR1_MASK (0xFFFFFFFFU) macro
21603 … (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1052/
DMIMXRT1052.h22386 #define GPC_IMR_IMR1_MASK (0xFFFFFFFFU) macro
22388 … (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1061/
DMIMXRT1061.h23351 #define GPC_IMR_IMR1_MASK (0xFFFFFFFFU) macro
23353 … (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1042/
DMIMXRT1042.h22974 #define GPC_IMR_IMR1_MASK (0xFFFFFFFFU) macro
22976 … (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1062/
DMIMXRT1062.h24137 #define GPC_IMR_IMR1_MASK (0xFFFFFFFFU) macro
24139 … (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK)
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MIMXRT1064/
DMIMXRT1064.h24200 #define GPC_IMR_IMR1_MASK (0xFFFFFFFFU) macro
24202 … (((uint32_t)(((uint32_t)(x)) << GPC_IMR_IMR1_SHIFT)) & GPC_IMR_IMR1_MASK)