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Searched refs:GPC_IMR (Results 1 – 2 of 2) sorted by relevance

/hal_nxp-3.5.0/mcux/mcux-sdk/drivers/gpc_2/
Dfsl_gpc.c40 base->GPC_IMR[0U] = GPC_IMR_IMR1_MASK; in GPC_Init()
41 base->GPC_IMR[1U] = GPC_IMR_IMR2_MASK; in GPC_Init()
42 base->GPC_IMR[2U] = GPC_IMR_IMR3_MASK; in GPC_Init()
43 base->GPC_IMR[3U] = GPC_IMR_IMR4_MASK; in GPC_Init()
45 base->GPC_IMR[4U] = GPC_IMR_IMR5_MASK; in GPC_Init()
82 base->GPC_IMR[irqRegNum] &= ~(1UL << irqRegShiftNum); in GPC_EnableIRQ()
98 base->GPC_IMR[irqRegNum] |= (1UL << irqRegShiftNum); in GPC_DisableIRQ()
Dfsl_gpc.h33 #define GPC_IMR IMR_M4 macro
66 #define GPC_IMR IMR_M7 macro