Searched refs:Fin (Results 1 – 2 of 2) sorted by relevance
170 static uint32 DFS_OUTPUT(const DFS_Type *Base, uint32 Channel, uint32 Fin);3992 uint32 Fin; in PLL_VCO() local4002 …Fin = (((Base->PLLCLKMUX & PLLDIG_PLLCLKMUX_REFCLKSEL_MASK) >> PLLDIG_PLLCLKMUX_REFCLKSEL_SHIFT) … in PLL_VCO()4011 …Var4 = Fin / Var3; /* Fin divide by (Rdiv multiplied by 18432… in PLL_VCO()4012 …Var5 = Fin - (Var4 * Var3); /* Fin minus Var4 multiplied by (Rdiv mu… in PLL_VCO()4014 Fout = Var1 * Fin; /* Var1 multipied by Fin */ in PLL_VCO()4015 …Fout += Fin / Rdiv * Var2; /* Fin divided by Rdiv and multiplied by V… in PLL_VCO()4025 uint32 Fin; in LFAST_PLL_VCO() local4033 Fin = Clock_Ip_Get_P1_LFAST0_REF_CLK_Frequency(); in LFAST_PLL_VCO()4036 Fin = Clock_Ip_Get_P1_LFAST1_REF_CLK_Frequency(); in LFAST_PLL_VCO()[all …]
3990 uint32 Fin; in Clock_Ip_PLL_VCO() local4002 Fin = Clock_Ip_Get_FXOSC_CLK_Frequency(); /* input freq */ in Clock_Ip_PLL_VCO()4021 …Var4 = Fin / Var3; /* Fin divide by (Rdiv multiplied by 18432… in Clock_Ip_PLL_VCO()4022 …Var5 = Fin - (Var4 * Var3); /* Fin minus Var4 multiplied by (Rdiv mu… in Clock_Ip_PLL_VCO()4024 if (0U != Fin) in Clock_Ip_PLL_VCO()4026 if (Var1 == ((uint32)(Var1 * Fin) / Fin)) in Clock_Ip_PLL_VCO()4028 Fout = Var1 * Fin; /* Var1 multipied by Fin */ in Clock_Ip_PLL_VCO()4035 if ((Var2 == ((uint32)(Fin * Var2) / Fin)) && (CLOCK_IP_PLL_VCO_MAX_FREQ >= Fout)) in Clock_Ip_PLL_VCO()4037 …Fout += Fin / Rdiv * Var2; /* Fin divided by Rdiv and multiplied by V… in Clock_Ip_PLL_VCO()
