Searched refs:Clock_Ip_au32EnableDivider (Results 1 – 2 of 2) sorted by relevance
471 static const uint32 Clock_Ip_au32EnableDivider[2U] = {CLOCK_IP_DISABLED,CLOCK_IP_ENABLED}; variable1414 …Frequency &= Clock_Ip_au32EnableDivider[((IP_CORE_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DE_MASK) >> PL… in Clock_Ip_Get_COREPLL_PHI0_Frequency()1483 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DE_MASK) >> … in Clock_Ip_Get_PERIPHPLL_PHI0_Frequency()1492 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[1U] & PLLDIG_PLLODIV_DE_MASK) >> … in Clock_Ip_Get_PERIPHPLL_PHI1_Frequency()1500 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[2U] & PLLDIG_PLLODIV_DE_MASK) >> … in Clock_Ip_Get_PERIPHPLL_PHI2_Frequency()1508 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[3U] & PLLDIG_PLLODIV_DE_MASK) >> … in Clock_Ip_Get_PERIPHPLL_PHI3_Frequency()1516 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[4U] & PLLDIG_PLLODIV_DE_MASK) >> … in Clock_Ip_Get_PERIPHPLL_PHI4_Frequency()1524 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[5U] & PLLDIG_PLLODIV_DE_MASK) >> … in Clock_Ip_Get_PERIPHPLL_PHI5_Frequency()1532 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PERIPH_PLL->PLLODIV[6U] & PLLDIG_PLLODIV_DE_MASK) >> … in Clock_Ip_Get_PERIPHPLL_PHI6_Frequency()1601 …Frequency &= Clock_Ip_au32EnableDivider[((IP_DDR_PLL->PLLODIV[0U] & PLLDIG_PLLODIV_DE_MASK) >> PLL… in Clock_Ip_Get_DDRPLL_PHI0_Frequency()[all …]
1644 static const uint32 Clock_Ip_au32EnableDivider[2U] = {CLOCK_IP_DISABLED,CLOCK_IP_ENABLED}; variable1850 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PLL->PLLODIV[0U] & PLL_PLLODIV_DE_MASK) >> PLL_PLLODI… in Clock_Ip_Get_PLL_PHI0_Frequency()1857 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PLL->PLLODIV[1U] & PLL_PLLODIV_DE_MASK) >> PLL_PLLODI… in Clock_Ip_Get_PLL_PHI1_Frequency()1865 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PLL_AUX->PLLODIV[0U] & PLL_PLLODIV_DE_MASK) >> PLL_PL… in Clock_Ip_Get_PLLAUX_PHI0_Frequency()1874 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PLL_AUX->PLLODIV[1U] & PLL_PLLODIV_DE_MASK) >> PLL_PL… in Clock_Ip_Get_PLLAUX_PHI1_Frequency()1883 …Frequency &= Clock_Ip_au32EnableDivider[((IP_PLL_AUX->PLLODIV[2U] & PLL_PLLODIV_DE_MASK) >> PLL_PL… in Clock_Ip_Get_PLLAUX_PHI2_Frequency()1942 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_0_DC_0 & MC_CGM_MUX_0_DC_0_DE_MASK) >> MC… in Clock_Ip_Get_CORE_CLK_Frequency()1949 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_0_DC_1 & MC_CGM_MUX_0_DC_1_DE_MASK) >> MC… in Clock_Ip_Get_AIPS_PLAT_CLK_Frequency()1956 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_0_DC_2 & MC_CGM_MUX_0_DC_2_DE_MASK) >> MC… in Clock_Ip_Get_AIPS_SLOW_CLK_Frequency()1963 …Frequency &= Clock_Ip_au32EnableDivider[((IP_MC_CGM->MUX_0_DC_3 & MC_CGM_MUX_0_DC_3_DE_MASK) >> MC… in Clock_Ip_Get_HSE_CLK_Frequency()[all …]
