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Searched refs:R0 (Results 1 – 3 of 3) sorted by relevance

/hal_nuvoton-latest/m48x/StdDriver/src/
Dretarget.c254 MOV R0, LR in HardFault_Handler() local
255 LSLS R0, #29 /*; Check bit 2 */ in HardFault_Handler() local
257 MRS R0, MSP /*; previous stack is MSP, read MSP */ in HardFault_Handler() local
260 MRS R0, PSP /*; Read PSP */ in HardFault_Handler() local
263 LDR R1, [R0, #24] /*; Get previous PC */ in HardFault_Handler()
270 STR R1, [R0, #24] /*; Save previous PC */ in HardFault_Handler()
280 MRS R0, PSP ;stack use PSP /*; stack use PSP, read PSP */ in HardFault_Handler() local
283 MRS R0, MSP ; stack use MSP /*; read MSP */ in HardFault_Handler() local
312 MOVS R0, #0 /*; Set return value to 0 */ in SH_DoCommand()
319 STR R0, [R2] /*; Save the return value to *pn32Out_R0 */ in SH_DoCommand()
[all …]
/hal_nuvoton-latest/m48x/Devices/M480/Source/IAR/
Dstartup_M480.s174 LDR R0, =0x40000100
176 STR R1, [R0]
178 STR R1, [R0]
180 STR R1, [R0]
183 LDR R0, =0x40000200 ; R0 = Clock Controller Register Base Address
184 LDR R1, [R0,#0x4] ; R1 = 0x40000204 (AHBCLK)
186 STR R1, [R0,#0x4] ; CLK->AHBCLK |= CLK_AHBCLK_SPIMCKEN_Msk;
188 LDR R0, =0x40007000 ; R0 = SPIM Register Base Address
189 LDR R1, [R0,#4] ; R1 = SPIM->CTL1
191 STR R1, [R0,#4] ; _SPIM_DISABLE_CACHE()
[all …]
/hal_nuvoton-latest/m48x/Devices/M480/Source/ARM/
Dstartup_M480.s196 LDR R0, =0x40000100
198 STR R1, [R0]
200 STR R1, [R0]
202 STR R1, [R0]
205 LDR R0, =0x40000200 ; R0 = Clock Controller Register Base Address
206 LDR R1, [R0,#0x4] ; R1 = 0x40000204 (AHBCLK)
208 STR R1, [R0,#0x4] ; CLK->AHBCLK |= CLK_AHBCLK_SPIMCKEN_Msk;
210 LDR R0, =0x40007000 ; R0 = SPIM Register Base Address
211 LDR R1, [R0,#4] ; R1 = SPIM->CTL1
213 STR R1, [R0,#4] ; _SPIM_DISABLE_CACHE()
[all …]