Lines Matching refs:R0
196 LDR R0, =0x40000100
198 STR R1, [R0]
200 STR R1, [R0]
202 STR R1, [R0]
205 LDR R0, =0x40000200 ; R0 = Clock Controller Register Base Address
206 LDR R1, [R0,#0x4] ; R1 = 0x40000204 (AHBCLK)
208 STR R1, [R0,#0x4] ; CLK->AHBCLK |= CLK_AHBCLK_SPIMCKEN_Msk;
210 LDR R0, =0x40007000 ; R0 = SPIM Register Base Address
211 LDR R1, [R0,#4] ; R1 = SPIM->CTL1
213 STR R1, [R0,#4] ; _SPIM_DISABLE_CACHE()
214 LDR R1, [R0,#4] ; R1 = SPIM->CTL1
216 STR R1, [R0,#4] ; _SPIM_ENABLE_CCM()
219 LDR R0, =SystemInit
220 BLX R0
228 LDR R0, =0x40000100
230 STR R1, [R0]
232 LDR R0, =__main
233 BX R0
502 LDR R0, = Heap_Mem