Lines Matching refs:R0
174 LDR R0, =0x40000100
176 STR R1, [R0]
178 STR R1, [R0]
180 STR R1, [R0]
183 LDR R0, =0x40000200 ; R0 = Clock Controller Register Base Address
184 LDR R1, [R0,#0x4] ; R1 = 0x40000204 (AHBCLK)
186 STR R1, [R0,#0x4] ; CLK->AHBCLK |= CLK_AHBCLK_SPIMCKEN_Msk;
188 LDR R0, =0x40007000 ; R0 = SPIM Register Base Address
189 LDR R1, [R0,#4] ; R1 = SPIM->CTL1
191 STR R1, [R0,#4] ; _SPIM_DISABLE_CACHE()
192 LDR R1, [R0,#4] ; R1 = SPIM->CTL1
194 STR R1, [R0,#4] ; _SPIM_ENABLE_CCM()
197 LDR R0, =SystemInit
198 BLX R0
206 LDR R0, =0x40000100
208 STR R1, [R0]
210 LDR R0, =__iar_program_start
211 BX R0