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Searched refs:LDR (Results 1 – 3 of 3) sorted by relevance

/hal_nuvoton-latest/m48x/Devices/M480/Source/ARM/
Dstartup_M480.s196 LDR R0, =0x40000100
197 LDR R1, =0x59
199 LDR R1, =0x16
201 LDR R1, =0x88
205 LDR R0, =0x40000200 ; R0 = Clock Controller Register Base Address
206 LDR R1, [R0,#0x4] ; R1 = 0x40000204 (AHBCLK)
210 LDR R0, =0x40007000 ; R0 = SPIM Register Base Address
211 LDR R1, [R0,#4] ; R1 = SPIM->CTL1
214 LDR R1, [R0,#4] ; R1 = SPIM->CTL1
219 LDR R0, =SystemInit
[all …]
/hal_nuvoton-latest/m48x/Devices/M480/Source/IAR/
Dstartup_M480.s174 LDR R0, =0x40000100
175 LDR R1, =0x59
177 LDR R1, =0x16
179 LDR R1, =0x88
183 LDR R0, =0x40000200 ; R0 = Clock Controller Register Base Address
184 LDR R1, [R0,#0x4] ; R1 = 0x40000204 (AHBCLK)
188 LDR R0, =0x40007000 ; R0 = SPIM Register Base Address
189 LDR R1, [R0,#4] ; R1 = SPIM->CTL1
192 LDR R1, [R0,#4] ; R1 = SPIM->CTL1
197 LDR R0, =SystemInit
[all …]
/hal_nuvoton-latest/m48x/StdDriver/src/
Dretarget.c263 LDR R1, [R0, #24] /*; Get previous PC */ in HardFault_Handler() local
265 LDR R2, =0xBEAB /*; The special BKPT instruction */ in HardFault_Handler()
286 LDR R2,=__cpp(Hard_Fault_Handler) /*; branch to Hard_Fault_Handler */ in HardFault_Handler()
423 LDR R2,=__cpp(Hard_Fault_Handler) /*; branch to Hard_Fault_Handler */ in HardFault_Handler()