Lines Matching refs:LDR
174 LDR R0, =0x40000100
175 LDR R1, =0x59
177 LDR R1, =0x16
179 LDR R1, =0x88
183 LDR R0, =0x40000200 ; R0 = Clock Controller Register Base Address
184 LDR R1, [R0,#0x4] ; R1 = 0x40000204 (AHBCLK)
188 LDR R0, =0x40007000 ; R0 = SPIM Register Base Address
189 LDR R1, [R0,#4] ; R1 = SPIM->CTL1
192 LDR R1, [R0,#4] ; R1 = SPIM->CTL1
197 LDR R0, =SystemInit
201 ; LDR R2, =0x40000024
202 ; LDR R1, =0x00005AA5
206 LDR R0, =0x40000100
210 LDR R0, =__iar_program_start