Lines Matching refs:LDR
196 LDR R0, =0x40000100
197 LDR R1, =0x59
199 LDR R1, =0x16
201 LDR R1, =0x88
205 LDR R0, =0x40000200 ; R0 = Clock Controller Register Base Address
206 LDR R1, [R0,#0x4] ; R1 = 0x40000204 (AHBCLK)
210 LDR R0, =0x40007000 ; R0 = SPIM Register Base Address
211 LDR R1, [R0,#4] ; R1 = SPIM->CTL1
214 LDR R1, [R0,#4] ; R1 = SPIM->CTL1
219 LDR R0, =SystemInit
223 ; LDR R2, =0x40000024
224 ; LDR R1, =0x00005AA5
228 LDR R0, =0x40000100
229 LDR R1, =0
232 LDR R0, =__main
502 LDR R0, = Heap_Mem
503 LDR R1, =(Stack_Mem + Stack_Size)
504 LDR R2, = (Heap_Mem + Heap_Size)
505 LDR R3, = Stack_Mem