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Searched refs:CLK_CLKSEL1_UART1SEL_Pos (Results 1 – 8 of 8) sorted by relevance

/hal_nuvoton-latest/m48x/StdDriver/src/
Duart.c209 u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos; in UART_Open()
365 u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos; in UART_SetLineConfig()
480 u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos; in UART_SelectIrDAMode()
/hal_nuvoton-latest/m46x/StdDriver/src/
Duart.c213 … u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos; in UART_Open()
371 … u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos; in UART_SetLineConfig()
486 … u32UartClkSrcSel = (CLK->CLKSEL1 & CLK_CLKSEL1_UART1SEL_Msk) >> CLK_CLKSEL1_UART1SEL_Pos; in UART_SelectIrDAMode()
/hal_nuvoton-latest/m48x/StdDriver/inc/
Dclk.h129 #define CLK_CLKSEL1_UART1SEL_HXT (0x0UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UAR…
130 #define CLK_CLKSEL1_UART1SEL_LXT (0x2UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UAR…
131 #define CLK_CLKSEL1_UART1SEL_PLL (0x1UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UAR…
132 #define CLK_CLKSEL1_UART1SEL_HIRC (0x3UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UAR…
/hal_nuvoton-latest/m48x/Devices/M480/Include/
Dclk_reg.h1305 #define CLK_CLKSEL1_UART1SEL_Pos (26) /*!< CLK… macro
1306 #define CLK_CLKSEL1_UART1SEL_Msk (0x3ul << CLK_CLKSEL1_UART1SEL_Pos) /*!< CLK…
/hal_nuvoton-latest/m46x/Devices/M460/Include/
Dclk_reg.h1876 #define CLK_CLKSEL1_UART1SEL_Pos (26) /*!< CLK… macro
1877 #define CLK_CLKSEL1_UART1SEL_Msk (0x3ul << CLK_CLKSEL1_UART1SEL_Pos) /*!< CLK…
/hal_nuvoton-latest/dts/m46x/
Dclk_reg.h1877 #define CLK_CLKSEL1_UART1SEL_Pos (26) /*!< CLK… macro
1878 #define CLK_CLKSEL1_UART1SEL_Msk (0x3ul << CLK_CLKSEL1_UART1SEL_Pos) /*!< CLK…
Dclk.h161 #define CLK_CLKSEL1_UART1SEL_HXT (0x0UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UAR…
162 #define CLK_CLKSEL1_UART1SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UAR…
163 #define CLK_CLKSEL1_UART1SEL_LXT (0x2UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UAR…
164 #define CLK_CLKSEL1_UART1SEL_HIRC (0x3UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UAR…
/hal_nuvoton-latest/m46x/StdDriver/inc/
Dclk.h161 #define CLK_CLKSEL1_UART1SEL_HXT (0x0UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UAR…
162 #define CLK_CLKSEL1_UART1SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UAR…
163 #define CLK_CLKSEL1_UART1SEL_LXT (0x2UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UAR…
164 #define CLK_CLKSEL1_UART1SEL_HIRC (0x3UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UAR…