1 /**************************************************************************//** 2 * @file clk_reg.h 3 * @version V3.00 4 * @brief CLK register definition header file 5 * 6 * @copyright SPDX-License-Identifier: Apache-2.0 7 * @copyright (C) 2021 Nuvoton Technology Corp. All rights reserved. 8 *****************************************************************************/ 9 #ifndef __CLK_REG_H__ 10 #define __CLK_REG_H__ 11 12 #if defined ( __CC_ARM ) 13 #pragma anon_unions 14 #endif 15 16 /******************************************************************************/ 17 /* Device Specific Peripheral registers structures */ 18 /******************************************************************************/ 19 20 /** @addtogroup REGISTER Control Register 21 22 @{ 23 24 */ 25 26 27 28 /*---------------------- System Clock Controller -------------------------*/ 29 /** 30 @addtogroup CLK System Clock Controller (CLK) 31 Memory Mapped Structure for CLK Controller 32 @{ */ 33 34 typedef struct 35 { 36 37 38 /** 39 * @var CLK_T::PWRCTL 40 * Offset: 0x00 System Power-down Control Register 41 * --------------------------------------------------------------------------------------------------- 42 * |Bits |Field |Descriptions 43 * | :----: | :----: | :---- | 44 * |[0] |HXTEN |HXT Enable Bit (Write Protect) 45 * | | |0 = 4~24 MHz external high speed crystal (HXT) Disabled. 46 * | | |1 = 4~24 MHz external high speed crystal (HXT) Enabled. 47 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 48 * |[1] |LXTEN |LXT Enable Bit (Write Protect) 49 * | | |0 = 32.768 kHz external low speed crystal (LXT) Disabled. 50 * | | |1 = 32.768 kHz external low speed crystal (LXT) Enabled. 51 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 52 * |[2] |HIRCEN |HIRC Enable Bit (Write Protect) 53 * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) Disabled. 54 * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) Enabled. 55 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 56 * |[3] |LIRCEN |LIRC Enable Bit (Write Protect) 57 * | | |0 = 10 kHz internal low speed RC oscillator (LIRC) Disabled. 58 * | | |1 = 10 kHz internal low speed RC oscillator (LIRC) Enabled. 59 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 60 * |[4] |PDWKDLY |Enable the Wake-up Delay Counter (Write Protect) 61 * | | |When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable. 62 * | | |The delayed clock cycle is 4096 clock cycles when chip works at 4~24 MHz external high speed crystal oscillator (HXT), and 64 or 24 clock cycles when chip works at 12 MHz internal high speed RC oscillator (HIRC). 63 * | | |0 = Clock cycles delay Disabled. 64 * | | |1 = Clock cycles delay Enabled. 65 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 66 * |[5] |PDWKIEN |Power-down Mode Wake-up Interrupt Enable Bit (Write Protect) 67 * | | |0 = Power-down mode wake-up interrupt Disabled. 68 * | | |1 = Power-down mode wake-up interrupt Enabled. 69 * | | |Note 1: The interrupt will occur when both PDWKIF and PDWKIEN are high. 70 * | | |Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. 71 * |[6] |PDWKIF |Power-down Mode Wake-up Interrupt Status 72 * | | |Set by Power-down wake-up event, it indicates that resume from Power-down mode. 73 * | | |The flag is set if any wake-up source ccurred. 74 * | | |Note 1: Write 1 to clear the bit to 0. 75 * | | |Note 2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. 76 * |[7] |PDEN |System Power-down Enable (Write Protect) 77 * | | |When this bit is set to 1, Power-down mode is enabled and chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode. 78 * | | |When chip wakes up from Power-down mode, this bit is auto cleared 79 * | | |Users need to set this bit again for next Power-down. 80 * | | |In Power-down mode, HXT and the HIRC will be disabled in this mode, but LXT and LIRC are not controlled by Power-down mode. 81 * | | |In Power-down mode, the PLL, PLLFN and system clock are disabled, and ignored the clock source selection. 82 * | | |The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from LXT or LIRC. 83 * | | |0 = Chip will not enter Power-down mode after CPU sleep command WFI. 84 * | | |1 = Chip enters Power-down mode after CPU sleep command WFI. 85 * | | |Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. 86 * | | |Note 2: System tick interrupt TICKINT(SYS_CTRL[1]) has to be disabled before entering to Power-down mode, to avoid system tick interrupt may influence system not entering power-down mode and keep operation. 87 * |[11:10] |HXTGAIN |HXT Gain Control Bit (Write Protect) 88 * | | |Gain control is used to enlarge the gain of crystal to make sure crystal work normally. 89 * | | |00 = HXT frequency is lower than from 8 MHz. 90 * | | |01 = HXT frequency is from 8 MHz to 12 MHz. 91 * | | |10 = HXT frequency is from 12 MHz to 16 MHz. 92 * | | |11 = HXT frequency is higher than 16 MHz. 93 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 94 * |[12] |HXTSELTYP |HXT Crystal Type Select Bit (Write Protect) 95 * | | |0 = Select INV type. 96 * | | |1 = Select GM type. 97 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 98 * |[17:16] |HIRCSTBS |HIRC Stable Count Select (Write Protect) 99 * | | |00 = HIRC stable count is 64 clocks. 100 * | | |01 = HIRC stable count is 24 clocks. 101 * | | |Others = Reserved 102 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 103 * |[18] |HIRC48MEN |HIRC48M Enable Bit (Write Protect) 104 * | | |0 = 48 MHz internal high speed RC oscillator (HIRC48M) Disabled. 105 * | | |1 = 48 MHz internal high speed RC oscillator (HIRC48M) Enabled. 106 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 107 * |[31] |HXTMD |HXT Bypass Mode (Write Protect) 108 * | | |0 = HXT work as crystal mode. PF.2 and PF.3 are configured as external high speed crystal (HXT) pins. 109 * | | |1 = HXT works as external clock mode. PF.3 is configured as external clock input pin. 110 * | | |Note: This bit is write protected. Refer to the SYS_REGCTL register. 111 * @var CLK_T::AHBCLK0 112 * Offset: 0x04 AHB Devices Clock Enable Control Register 0 113 * --------------------------------------------------------------------------------------------------- 114 * |Bits |Field |Descriptions 115 * | :----: | :----: | :---- | 116 * |[1] |PDMA0CKEN |PDMA0 Controller Clock Enable Bit 117 * | | |0 = PDMA0 peripheral clock Disabled. 118 * | | |1 = PDMA0 peripheral clock Enabled. 119 * |[2] |ISPCKEN |Flash ISP Controller Clock Enable Bit 120 * | | |0 = Flash ISP peripheral clock Disabled. 121 * | | |1 = Flash ISP peripheral clock Enabled. 122 * |[3] |EBICKEN |EBI Controller Clock Enable Bit 123 * | | |0 = EBI peripheral clock Disabled. 124 * | | |1 = EBI peripheral clock Enabled. 125 * |[4] |STCKEN |System Tick Clock Enable Bit 126 * | | |0 = System tick clock Disabled. 127 * | | |1 = System tick clock Enabled. 128 * |[5] |EMAC0CKEN |EMAC0 Controller Clock Enable Bit 129 * | | |0 = EMAC0 controller clock Disabled. 130 * | | |1 = EMAC0 controller clock Enabled. 131 * |[6] |SDH0CKEN |SDH0 Controller Clock Enable Bit 132 * | | |0 = SDH0 clock Disabled. 133 * | | |1 = SDH0 clock Enabled. 134 * |[7] |CRCCKEN |CRC Generator Controller Clock Enable Bit 135 * | | |0 = CRC peripheral clock Disabled. 136 * | | |1 = CRC peripheral clock Enabled. 137 * |[8] |CCAPCKEN |Camera Capture Interface Controller Clock Enable Bit 138 * | | |0 = CCAP controller clock Disabled. 139 * | | |1 = CCAP controller clock Enabled. 140 * |[9] |SENCKEN |CCAP Sensor Clock Enable Bit 141 * | | |0 = CCAP Sensor clock Disabled. 142 * | | |1 = CCAP Sensor clock Enabled. 143 * |[10] |HSUSBDCKEN|HSUSB Device Clock Enable Bit 144 * | | |0 = HSUSB device controller clock Disabled. 145 * | | |1 = HSUSB device controller clock Enabled. 146 * |[11] |HBICKEN |Hyper Bus Interface Clock Enable Bit 147 * | | |0 = HBI clock Disabled. 148 * | | |1 = HBI clock Enabled. 149 * |[12] |CRPTCKEN |Cryptographic Accelerator Clock Enable Bit 150 * | | |0 = Cryptographic Accelerator clock Disabled. 151 * | | |1 = Cryptographic Accelerator clock Enabled. 152 * |[13] |KSCKEN |Key Stroe Clock Enable Bit 153 * | | |0 = Key Store clock Disabled. 154 * | | |1 = Key Store clock Enabled. 155 * |[14] |SPIMCKEN |SPIM Controller Clock Enable Bit 156 * | | |0 = SPIM controller clock Disabled. 157 * | | |1 = SPIM controller clock Enabled. 158 * |[15] |FMCIDLE |Flash Memory Controller Clock Enable Bit in IDLE Mode 159 * | | |0 = FMC clock Disabled when chip is under IDLE mode. 160 * | | |1 = FMC clock Enabled when chip is under IDLE mode. 161 * |[16] |USBHCKEN |USB HOST Controller Clock Enable Bit 162 * | | |0 = USB HOST peripheral clock Disabled. 163 * | | |1 = USB HOST peripheral clock Enabled. 164 * |[17] |SDH1CKEN |SDH1 Controller Clock Enable Bit 165 * | | |0 = SDH1 clock Disabled. 166 * | | |1 = SDH1 clock Enabled. 167 * |[18] |PDMA1CKEN |PDMA1 Clock Enable Bit 168 * | | |0 = PDMA1 clock Disabled. 169 * | | |1 = PDMA1 clock Enabled. 170 * |[19] |TRACECKEN |TRACE Clock Enable Bit 171 * | | |0 = TRACE clock Disabled. 172 * | | |1 = TRACE clock Enabled. 173 * |[24] |GPACKEN |GPIOA Clock Enable Bit 174 * | | |0 = GPIOA clock Disabled. 175 * | | |1 = GPIOA clock Enabled. 176 * |[25] |GPBCKEN |GPIOB Clock Enable Bit 177 * | | |0 = GPIOB clock Disabled. 178 * | | |1 = GPIOB clock Enabled. 179 * |[26] |GPCCKEN |GPIOC Clock Enable Bit 180 * | | |0 = GPIOC clock Disabled. 181 * | | |1 = GPIOC clock Enabled. 182 * |[27] |GPDCKEN |GPIOD Clock Enable Bit 183 * | | |0 = GPIOD clock Disabled. 184 * | | |1 = GPIOD clock Enabled. 185 * |[28] |GPECKEN |GPIOE Clock Enable Bit 186 * | | |0 = GPIOE clock Disabled. 187 * | | |1 = GPIOE clock Enabled. 188 * |[29] |GPFCKEN |GPIOF Clock Enable Bit 189 * | | |0 = GPIOF clock Disabled. 190 * | | |1 = GPIOF clock Enabled. 191 * |[30] |GPGCKEN |GPIOG Clock Enable Bit 192 * | | |0 = GPIOG clock Disabled. 193 * | | |1 = GPIOG clock Enabled. 194 * |[31] |GPHCKEN |GPIOH Clock Enable Bit 195 * | | |0 = GPIOH clock Disabled. 196 * | | |1 = GPIOH clock Enabled. 197 * @var CLK_T::APBCLK0 198 * Offset: 0x08 APB Devices Clock Enable Control Register 0 199 * --------------------------------------------------------------------------------------------------- 200 * |Bits |Field |Descriptions 201 * | :----: | :----: | :---- | 202 * |[0] |WDTCKEN |Watchdog Timer Clock Enable Bit (Write Protect) 203 * | | |0 = Watchdog timer clock Disabled. 204 * | | |1 = Watchdog timer clock Enabled. 205 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 206 * |[1] |RTCCKEN |Real-time-clock APB Interface Clock Enable Bit 207 * | | |This bit is used to control the RTC APB clock only. 208 * | | |The RTC peripheral clock source is selected from RTCCKSEL(RTC_LXTCTL[7]). 209 * | | |It can be selected to 32.768 kHz external low speed crystal (LXT) or 10 kHz internal low speed RC oscillator (LIRC). 210 * | | |0 = RTC clock Disabled. 211 * | | |1 = RTC clock Enabled. 212 * |[2] |TMR0CKEN |Timer0 Clock Enable Bit 213 * | | |0 = Timer0 clock Disabled. 214 * | | |1 = Timer0 clock Enabled. 215 * |[3] |TMR1CKEN |Timer1 Clock Enable Bit 216 * | | |0 = Timer1 clock Disabled. 217 * | | |1 = Timer1 clock Enabled. 218 * |[4] |TMR2CKEN |Timer2 Clock Enable Bit 219 * | | |0 = Timer2 clock Disabled. 220 * | | |1 = Timer2 clock Enabled. 221 * |[5] |TMR3CKEN |Timer3 Clock Enable Bit 222 * | | |0 = Timer3 clock Disabled. 223 * | | |1 = Timer3 clock Enabled. 224 * |[6] |CLKOCKEN |CLKO Clock Enable Bit 225 * | | |0 = CLKO clock Disabled. 226 * | | |1 = CLKO clock Enabled. 227 * |[7] |ACMP01CKEN|Analog Comparator 0/1 Clock Enable Bit 228 * | | |0 = Analog comparator 0/1 clock Disabled. 229 * | | |1 = Analog comparator 0/1 clock Enabled. 230 * |[8] |I2C0CKEN |I2C0 Clock Enable Bit 231 * | | |0 = I2C0 clock Disabled. 232 * | | |1 = I2C0 clock Enabled. 233 * |[9] |I2C1CKEN |I2C1 Clock Enable Bit 234 * | | |0 = I2C1 clock Disabled. 235 * | | |1 = I2C1 clock Enabled. 236 * |[10] |I2C2CKEN |I2C2 Clock Enable Bit 237 * | | |0 = I2C2 clock Disabled. 238 * | | |1 = I2C2 clock Enabled. 239 * |[11] |I2C3CKEN |I2C3 Clock Enable Bit 240 * | | |0 = I2C3 clock Disabled. 241 * | | |1 = I2C3 clock Enabled. 242 * |[12] |QSPI0CKEN |QSPI0 Clock Enable Bit 243 * | | |0 = QSPI0 clock Disabled. 244 * | | |1 = QSPI0 clock Enabled. 245 * |[13] |SPI0CKEN |SPI0 Clock Enable Bit 246 * | | |0 = SPI0 clock Disabled. 247 * | | |1 = SPI0 clock Enabled. 248 * |[14] |SPI1CKEN |SPI1 Clock Enable Bit 249 * | | |0 = SPI1 clock Disabled. 250 * | | |1 = SPI1 clock Enabled. 251 * |[15] |SPI2CKEN |SPI2 Clock Enable Bit 252 * | | |0 = SPI2 clock Disabled. 253 * | | |1 = SPI2 clock Enabled. 254 * |[16] |UART0CKEN |UART0 Clock Enable Bit 255 * | | |0 = UART0 clock Disabled. 256 * | | |1 = UART0 clock Enabled. 257 * |[17] |UART1CKEN |UART1 Clock Enable Bit 258 * | | |0 = UART1 clock Disabled. 259 * | | |1 = UART1 clock Enabled. 260 * |[18] |UART2CKEN |UART2 Clock Enable Bit 261 * | | |0 = UART2 clock Disabled. 262 * | | |1 = UART2 clock Enabled. 263 * |[19] |UART3CKEN |UART3 Clock Enable Bit 264 * | | |0 = UART3 clock Disabled. 265 * | | |1 = UART3 clock Enabled. 266 * |[20] |UART4CKEN |UART4 Clock Enable Bit 267 * | | |0 = UART4 clock Disabled. 268 * | | |1 = UART4 clock Enabled. 269 * |[21] |UART5CKEN |UART5 Clock Enable Bit 270 * | | |0 = UART5 clock Disabled. 271 * | | |1 = UART5 clock Enabled. 272 * |[22] |UART6CKEN |UART6 Clock Enable Bit 273 * | | |0 = UART6 clock Disabled. 274 * | | |1 = UART6 clock Enabled. 275 * |[23] |UART7CKEN |UART7 Clock Enable Bit 276 * | | |0 = UART7 clock Disabled. 277 * | | |1 = UART7 clock Enabled. 278 * |[26] |OTGCKEN |USB OTG Clock Enable Bit 279 * | | |0 = USB OTG clock Disabled. 280 * | | |1 = USB OTG clock Enabled. 281 * |[27] |USBDCKEN |USB Device Clock Enable Bit 282 * | | |0 = USB device clock Disabled. 283 * | | |1 = USB device clock Enabled. 284 * |[28] |EADC0CKEN |EADC0 Clock Enable Bit 285 * | | |0 = EADC0 clock Disabled. 286 * | | |1 = EADC0 clock Enabled. 287 * |[29] |I2S0CKEN |I2S0 Clock Enable Bit 288 * | | |0 = I2S0 clock Disabled. 289 * | | |1 = I2S0 clock Enabled. 290 * |[30] |HSOTGCKEN |HSUSB OTG Clock Enable Bit 291 * | | |0 = HSUSB OTG clock Disabled. 292 * | | |1 = HSUSB OTG clock Enabled. 293 * @var CLK_T::APBCLK1 294 * Offset: 0x0C APB Devices Clock Enable Control Register 1 295 * --------------------------------------------------------------------------------------------------- 296 * |Bits |Field |Descriptions 297 * | :----: | :----: | :---- | 298 * |[0] |SC0CKEN |SC0 Clock Enable Bit 299 * | | |0 = SC0 clock Disabled. 300 * | | |1 = SC0 clock Enabled. 301 * |[1] |SC1CKEN |SC1 Clock Enable Bit 302 * | | |0 = SC1 clock Disabled. 303 * | | |1 = SC1 clock Enabled. 304 * |[2] |SC2CKEN |SC2 Clock Enable Bit 305 * | | |0 = SC2 clock Disabled. 306 * | | |1 = SC2 clock Enabled. 307 * |[3] |I2C4CKEN |I2C4 Clock Enable Bit 308 * | | |0 = I2C4 clock Disabled. 309 * | | |1 = I2C4 clock Enabled. 310 * |[4] |QSPI1CKEN |QSPI1 Clock Enable Bit 311 * | | |0 = QSPI1 clock Disabled. 312 * | | |1 = QSPI1 clock Enabled. 313 * |[6] |SPI3CKEN |SPI3 Clock Enable Bit 314 * | | |0 = SPI3 clock Disabled. 315 * | | |1 = SPI3 clock Enabled. 316 * |[7] |SPI4CKEN |SPI4 Clock Enable Bit 317 * | | |0 = SPI4 clock Disabled. 318 * | | |1 = SPI4 clock Enabled. 319 * |[8] |USCI0CKEN |USCI0 Clock Enable Bit 320 * | | |0 = USCI0 clock Disabled. 321 * | | |1 = USCI0 clock Enabled. 322 * |[10] |PSIOCKEN |PSIO Clock Enable Bit 323 * | | |0 = PSIO clock Disabled. 324 * | | |1 = PSIO clock Enabled. 325 * |[12] |DACCKEN |DAC Clock Enable Bit 326 * | | |0 = DAC clock Disabled. 327 * | | |1 = DAC clock Enabled. 328 * |[13] |ECAP2CKEN |ECAP2 Clock Enable Bit 329 * | | |0 = ECAP2 clock Disabled. 330 * | | |1 = ECAP2 clock Enabled. 331 * |[14] |ECAP3CKEN |ECAP3 Clock Enable Bit 332 * | | |0 = ECAP3 clock Disabled. 333 * | | |1 = ECAP3 clock Enabled. 334 * |[16] |EPWM0CKEN |EPWM0 Clock Enable Bit 335 * | | |0 = EPWM0 clock Disabled. 336 * | | |1 = EPWM0 clock Enabled. 337 * |[17] |EPWM1CKEN |EPWM1 Clock Enable Bit 338 * | | |0 = EPWM1 clock Disabled. 339 * | | |1 = EPWM1 clock Enabled. 340 * |[18] |BPWM0CKEN |BPWM0 Clock Enable Bit 341 * | | |0 = BPWM0 clock Disabled. 342 * | | |1 = BPWM0 clock Enabled. 343 * |[19] |BPWM1CKEN |BPWM1 Clock Enable Bit 344 * | | |0 = BPWM1 clock Disabled. 345 * | | |1 = BPWM1 clock Enabled. 346 * |[20] |EQEI2CKEN |EQEI2 Clock Enable Bit 347 * | | |0 = EQEI2 clock Disabled. 348 * | | |1 = EQEI2 clock Enabled. 349 * |[21] |EQEI3CKEN |EQEI3 Clock Enable Bit 350 * | | |0 = EQEI3 clock Disabled. 351 * | | |1 = EQEI3 clock Enabled. 352 * |[22] |EQEI0CKEN |EQEI0 Clock Enable Bit 353 * | | |0 = EQEI0 clock Disabled. 354 * | | |1 = EQEI0 clock Enabled. 355 * |[23] |EQEI1CKEN |EQEI1 Clock Enable Bit 356 * | | |0 = EQEI1 clock Disabled. 357 * | | |1 = EQEI1 clock Enabled. 358 * |[25] |TRNGCKEN |TRNG Clock Enable Bit 359 * | | |0 = TRNG clock Disabled. 360 * | | |1 = TRNG clock Enabled. 361 * |[26] |ECAP0CKEN |ECAP0 Clock Enable Bit 362 * | | |0 = ECAP0 clock Disabled. 363 * | | |1 = ECAP0 clock Enabled. 364 * |[27] |ECAP1CKEN |ECAP1 Clock Enable Bit 365 * | | |0 = ECAP1 clock Disabled. 366 * | | |1 = ECAP1 clock Enabled. 367 * |[29] |I2S1CKEN |I2S1 Clock Enable Bit 368 * | | |0 = I2S1 clock Disabled. 369 * | | |1 = I2S1 clock Enabled. 370 * |[31] |EADC1CKEN |EADC1 Clock Enable Bit 371 * | | |0 = EADC1 clock Disabled. 372 * | | |1 = EADC1 clock Enabled. 373 * @var CLK_T::CLKSEL0 374 * Offset: 0x10 Clock Source Select Control Register 0 375 * --------------------------------------------------------------------------------------------------- 376 * |Bits |Field |Descriptions 377 * | :----: | :----: | :---- | 378 * |[2:0] |HCLKSEL |HCLK Clock Source Selection (Write Protect) 379 * | | |Before clock switching, the related clock sources (both pre-select and new-select) must be turned on. 380 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 381 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 382 * | | |010 = Clock source from PLL 383 * | | |011 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 384 * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 385 * | | |Others = Reserved. 386 * | | |Note: Theses bits are write protected. Refer to the SYS_REGLCTL register. 387 * |[5:3] |STCLKSEL |Cortex-M4 SysTick Clock Source Selection (Write Protect) 388 * | | |If SYST_CTRL[2]=0, SysTick uses listed clock source below. 389 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 390 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 391 * | | |010 = Clock source from HXT/2. 392 * | | |011 = Clock source from HCLK/2. 393 * | | |111 = Clock source from HIRC/2. 394 * | | |Note 1: If SysTick clock source is not from HCLK (i.e. SYST_CTRL[2] = 0), SysTick needs to enable STCKEN(CLK_AHBCLK0[4]). 395 * | | |SysTick clock source must less than or equal to HCLK/2. 396 * | | |Note 2: These bits are write protected. Refer to the SYS_REGLCTL register. 397 * |[8] |USBSEL |USB Clock Source Selection (Write Protect) 398 * | | |0 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). 399 * | | |1 = Clock source from PLL/2. 400 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 401 * |[11:10] |EADC0SEL |EADC0 Clock Source Selection (Write Protect) 402 * | | |00 = Clock source from PLLFN/2. 403 * | | |01 = Clock source from PLL/2. 404 * | | |10 = Clock source from HCLK. 405 * | | |11 = Reserved. 406 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 407 * |[13:12] |EADC1SEL |EADC1 Clock Source Selection (Write Protect) 408 * | | |00 = Clock source from PLLFN/2. 409 * | | |01 = Clock source from PLL/2. 410 * | | |10 = Clock source from HCLK. 411 * | | |11 = Reserved. 412 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 413 * |[15:14] |EADC2SEL |EADC2 Clock Source Selection (Write Protect) 414 * | | |00 = Clock source from PLLFN/2. 415 * | | |01 = Clock source from PLL/2. 416 * | | |10 = Clock source from HCLK. 417 * | | |11 = Reserved. 418 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 419 * |[17:16] |CCAPSEL |CCAP Sensor Clock Source Selection (Write Protect) 420 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 421 * | | |01 = Clock source from PLL/2. 422 * | | |10 = Clock source from HCLK. 423 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 424 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 425 * |[21:20] |SDH0SEL |SDH0 Clock Source Selection (Write Protect) 426 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 427 * | | |01 = Clock source from PLL/2 clock. 428 * | | |10 = Clock source from HCLK. 429 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 430 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 431 * |[23:22] |SDH1SEL |SDH1 Clock Source Selection (Write Protect) 432 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 433 * | | |01 = Clock source from PLL/2 clock. 434 * | | |10 = Clock source from HCLK. 435 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 436 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 437 * |[25:24] |CANFD0SEL |CANFD0 Clock Source Selection (Write Protect) 438 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 439 * | | |01 = Clock source from PLL/2 clock. 440 * | | |10 = Clock source from HCLK. 441 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 442 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 443 * |[27:26] |CANFD1SEL |CANFD1 Clock Source Selection (Write Protect) 444 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 445 * | | |01 = Clock source from PLL/2 clock. 446 * | | |10 = Clock source from HCLK. 447 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 448 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 449 * |[29:28] |CANFD2SEL |CANFD2 Clock Source Selection (Write Protect) 450 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 451 * | | |01 = Clock source from PLL/2 clock. 452 * | | |10 = Clock source from HCLK. 453 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 454 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 455 * |[31:30] |CANFD3SEL |CANFD3 Clock Source Selection (Write Protect) 456 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 457 * | | |01 = Clock source from PLL/2 clock. 458 * | | |10 = Clock source from HCLK. 459 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 460 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 461 * @var CLK_T::CLKSEL1 462 * Offset: 0x14 Clock Source Select Control Register 1 463 * --------------------------------------------------------------------------------------------------- 464 * |Bits |Field |Descriptions 465 * | :----: | :----: | :---- | 466 * |[1:0] |WDTSEL |Watchdog Timer Clock Source Selection (Write Protect) 467 * | | |00 = Reserved. 468 * | | |01 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 469 * | | |10 = Clock source from HCLK/2048. 470 * | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 471 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 472 * |[6:4] |CLKOSEL |Clock Output Clock Source Selection 473 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 474 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 475 * | | |010 = Clock source from HCLK. 476 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 477 * | | |100 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 478 * | | |101 = Clock source from PLLFN/2. 479 * | | |110 = Clock source from PLL/2. 480 * | | |111 = Reserved. 481 * |[10:8] |TMR0SEL |TIMER0 Clock Source Selection 482 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 483 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 484 * | | |010 = Clock source from PCLK0. 485 * | | |011 = Clock source from external clock TM0 pin. 486 * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 487 * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 488 * | | |Others = Reserved. 489 * |[14:12] |TMR1SEL |TIMER1 Clock Source Selection 490 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 491 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 492 * | | |010 = Clock source from PCLK0. 493 * | | |011 = Clock source from external clock TM1 pin. 494 * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 495 * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 496 * | | |Others = Reserved. 497 * |[18:16] |TMR2SEL |TIMER2 Clock Source Selection 498 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 499 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 500 * | | |010 = Clock source from PCLK1. 501 * | | |011 = Clock source from external clock TM2 pin. 502 * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 503 * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 504 * | | |Others = Reserved. 505 * |[22:20] |TMR3SEL |TIMER3 Clock Source Selection 506 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 507 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 508 * | | |010 = Clock source from PCLK1. 509 * | | |011 = Clock source from external clock TM3 pin. 510 * | | |101 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 511 * | | |111 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 512 * | | |Others = Reserved. 513 * |[25:24] |UART0SEL |UART0 Clock Source Selection 514 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 515 * | | |01 = Clock source from PLL/2. 516 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 517 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 518 * |[27:26] |UART1SEL |UART1 Clock Source Selection 519 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 520 * | | |01 = Clock source from PLL/2. 521 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 522 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 523 * |[31:30] |WWDTSEL |Window Watchdog Timer Clock Source Selection 524 * | | |10 = Clock source from HCLK/2048. 525 * | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 526 * | | |Others = Reserved. 527 * @var CLK_T::CLKSEL2 528 * Offset: 0x18 Clock Source Select Control Register 2 529 * --------------------------------------------------------------------------------------------------- 530 * |Bits |Field |Descriptions 531 * | :----: | :----: | :---- | 532 * |[0] |EPWM0SEL |EPWM0 Clock Source Selection 533 * | | |The peripheral clock source of EPWM0 is defined by EPWM0SEL. 534 * | | |0 = Clock source from HCLK. 535 * | | |1 = Clock source from PCLK0. 536 * |[1] |EPWM1SEL |EPWM1 Clock Source Selection 537 * | | |The peripheral clock source of EPWM1 is defined by EPWM1SEL. 538 * | | |0 = Clock source from HCLK. 539 * | | |1 = Clock source from PCLK1. 540 * |[3:2] |QSPI0SEL |QSPI0 Clock Source Selection 541 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 542 * | | |01 = Clock source from PLL/2. 543 * | | |10 = Clock source from PCLK0. 544 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 545 * |[6:4] |SPI0SEL |SPI0 Clock Source Selection 546 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 547 * | | |001 = Clock source from PLL/2. 548 * | | |010 = Clock source from PCLK1. 549 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 550 * | | |100 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). 551 * | | |101 = Clock source from PLLFN/2. 552 * | | |Others = Reserved. 553 * |[8] |BPWM0SEL |BPWM0 Clock Source Selection 554 * | | |The peripheral clock source of BPWM0 is defined by BPWM0SEL. 555 * | | |0 = Clock source from HCLK. 556 * | | |1 = Clock source from PCLK0. 557 * |[9] |BPWM1SEL |BPWM1 Clock Source Selection 558 * | | |The peripheral clock source of BPWM1 is defined by BPWM1SEL. 559 * | | |0 = Clock source from HCLK. 560 * | | |1 = Clock source from PCLK1. 561 * |[11:10] |QSPI1SEL |QSPI1 Clock Source Selection 562 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 563 * | | |01 = Clock source from PLL/2. 564 * | | |10 = Clock source from PCLK1. 565 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 566 * |[14:12] |SPI1SEL |SPI1 Clock Source Selection 567 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 568 * | | |001 = Clock source from PLL/2. 569 * | | |010 = Clock source from PCLK0. 570 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 571 * | | |100 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). 572 * | | |101 = Clock source from PLLFN/2. 573 * | | |Others = Reserved. 574 * |[18:16] |I2S1SEL |I2S1 Clock Source Selection 575 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 576 * | | |001 = Clock source from PLL/2. 577 * | | |010 = Clock source from PCLK1. 578 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 579 * | | |100 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). 580 * | | |101 = Clock source from PLLFN/2. 581 * | | |Others = Reserved. 582 * |[21:20] |UART8SEL |UART8 Clock Source Selection 583 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 584 * | | |01 = Clock source from PLL/2. 585 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 586 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 587 * |[23:22] |UART9SEL |UART9 Clock Source Selection 588 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 589 * | | |01 = Clock source from PLL/2. 590 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 591 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 592 * |[27] |TRNGSEL |TRNG Clock Source Selection 593 * | | |0 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 594 * | | |1 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 595 * |[30:28] |PSIOSEL |PSIO Clock Source Selection 596 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 597 * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 598 * | | |010 = Clock source from PCLK1. 599 * | | |011 = Clock source from PLL/2. 600 * | | |100 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 601 * | | |101 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 602 * | | |Others = Reserved. 603 * @var CLK_T::CLKSEL3 604 * Offset: 0x1C Clock Source Select Control Register 3 605 * --------------------------------------------------------------------------------------------------- 606 * |Bits |Field |Descriptions 607 * | :----: | :----: | :---- | 608 * |[1:0] |SC0SEL |SC0 Clock Source Selection 609 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 610 * | | |01 = Clock source from PLL/2. 611 * | | |10 = Clock source from PCLK0. 612 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 613 * |[3:2] |SC1SEL |SC0 Clock Source Selection 614 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 615 * | | |01 = Clock source from PLL/2. 616 * | | |10 = Clock source from PCLK1. 617 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 618 * |[5:4] |SC2SEL |SC2 Clock Source Selection 619 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 620 * | | |01 = Clock source from PLL/2. 621 * | | |10 = Clock source from PCLK0. 622 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 623 * |[7:6] |KPISEL |KPI Clock Source Selection 624 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 625 * | | |01 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). 626 * | | |10 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 627 * | | |11 = Reserved. 628 * |[11:9] |SPI2SEL |SPI2 Clock Source Selection 629 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 630 * | | |001 = Clock source from PLL/2. 631 * | | |010 = Clock source from PCLK1. 632 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 633 * | | |100 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). 634 * | | |101 = Clock source from PLLFN/2. 635 * | | |Others = Reserved. 636 * |[14:12] |SPI3SEL |SPI3 Clock Source Selection 637 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 638 * | | |001 = Clock source from PLL/2. 639 * | | |010 = Clock source from PCLK0. 640 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 641 * | | |100 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). 642 * | | |101 = Clock source from PLLFN/2. 643 * | | |Others = Reserved. 644 * |[18:16] |I2S0SEL |I2S0 Clock Source Selection 645 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 646 * | | |001 = Clock source from PLL/2. 647 * | | |010 = Clock source from PCLK0. 648 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 649 * | | |100 = Clock source from 48 MHz internal high speed RC oscillator (HIRC48M). 650 * | | |101 = Clock source from PLLFN/2. 651 * | | |Others = Reserved. 652 * |[21:20] |UART6SEL |UART6 Clock Source Selection 653 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 654 * | | |01 = Clock source from PLL/2. 655 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 656 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 657 * |[23:22] |UART7SEL |UART7 Clock Source Selection 658 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 659 * | | |01 = Clock source from PLL/2. 660 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 661 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 662 * |[25:24] |UART2SEL |UART2 Clock Source Selection 663 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 664 * | | |01 = Clock source from PLL/2. 665 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 666 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 667 * |[27:26] |UART3SEL |UART3 Clock Source Selection 668 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 669 * | | |01 = Clock source from PLL/2. 670 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 671 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 672 * |[29:28] |UART4SEL |UART4 Clock Source Selection 673 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 674 * | | |01 = Clock source from PLL/2. 675 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 676 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 677 * |[31:30] |UART5SEL |UART5 Clock Source Selection 678 * | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 679 * | | |01 = Clock source from PLL/2. 680 * | | |10 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). 681 * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 682 * @var CLK_T::CLKDIV0 683 * Offset: 0x20 Clock Divider Number Register 0 684 * --------------------------------------------------------------------------------------------------- 685 * |Bits |Field |Descriptions 686 * | :----: | :----: | :---- | 687 * |[3:0] |HCLKDIV |HCLK Clock Divide Number from HCLK Clock Source 688 * | | |HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1). 689 * |[7:4] |USBDIV |USB Clock Divide Number from PLL/2 Clock 690 * | | |USB clock frequency = ((PLL frequency)/2) / (USBDIV + 1). 691 * |[11:8] |UART0DIV |UART0 Clock Divide Number from UART0 Clock Source 692 * | | |UART0 clock frequency = (UART0 clock source frequency) / (UART0DIV + 1). 693 * |[15:12] |UART1DIV |UART1 Clock Divide Number from UART1 Clock Source 694 * | | |UART1 clock frequency = (UART1 clock source frequency) / (UART1DIV + 1). 695 * |[23:16] |EADC0DIV |EADC0 Clock Divide Number from EADC0 Clock Source 696 * | | |EADC0 clock frequency = (EADC0 clock source frequency) / (EADC0DIV + 1). 697 * |[31:24] |SDH0DIV |SDH0 Clock Divide Number from SDH0 Clock Source 698 * | | |SDH0 clock frequency = (SDH0 clock source frequency) / (SDH0DIV + 1). 699 * @var CLK_T::CLKDIV1 700 * Offset: 0x24 Clock Divider Number Register 1 701 * --------------------------------------------------------------------------------------------------- 702 * |Bits |Field |Descriptions 703 * | :----: | :----: | :---- | 704 * |[7:0] |SC0DIV |SC0 Clock Divide Number from SC0 Clock Source 705 * | | |SC0 clock frequency = (SC0 clock source frequency) / (SC0DIV + 1). 706 * |[15:8] |SC1DIV |SC1 Clock Divide Number from SC1 Clock Source 707 * | | |SC1 clock frequency = (SC1 clock source frequency) / (SC1DIV + 1). 708 * |[23:16] |SC2DIV |SC2 Clock Divide Number from SC2 Clock Source 709 * | | |SC2 clock frequency = (SC2 clock source frequency) / (SC2DIV + 1). 710 * |[31:24] |PSIODIV |PSIO Clock Divide Number from PSIO Clock Source 711 * | | |PSIO clock frequency = (PSIO clock source frequency) / (PSIODIV + 1). 712 * @var CLK_T::CLKDIV2 713 * Offset: 0x28 Clock Divider Number Register 2 714 * --------------------------------------------------------------------------------------------------- 715 * |Bits |Field |Descriptions 716 * | :----: | :----: | :---- | 717 * |[3:0] |I2S0DIV |I2S0 Clock Divide Number from I2S0 Clock Source 718 * | | |I2S0 clock frequency = (I2S0 clock source frequency) / (I2S0DIV + 1). 719 * |[7:4] |I2S1DIV |I2S1 Clock Divide Number from I2S1 Clock Source 720 * | | |I2S1 clock frequency = (I2S1 clock source frequency) / (I2S1DIV + 1). 721 * |[15:8] |KPIDIV |KPI Clock Divide Number from KPI Clock Source 722 * | | |KPI clock frequency = (KPI clock source frequency) / (KPIDIV + 1). 723 * |[31:24] |EADC1DIV |EADC1 Clock Divide Number from EADC1 Clock Source 724 * | | |EADC1 clock frequency = (EADC1 clock source frequency) / (EADC1DIV + 1). 725 * @var CLK_T::CLKDIV3 726 * Offset: 0x2C Clock Divider Number Register 3 727 * --------------------------------------------------------------------------------------------------- 728 * |Bits |Field |Descriptions 729 * | :----: | :----: | :---- | 730 * |[15:8] |VSENSEDIV |Video Pixel Clock Divide Number from CCAP Sensor Clock Source 731 * | | |Video pixel clock frequency = (CCAP sensor clock source frequency) / (VSENSEDIV + 1). 732 * |[31:24] |SDH1DIV |SDH1 Clock Divide Number from SDH1 Clock Source 733 * | | |SDH1 clock frequency = (SDH1 clock source frequency) / (SDH1DIV + 1). 734 * @var CLK_T::CLKDIV4 735 * Offset: 0x30 Clock Divider Number Register 4 736 * --------------------------------------------------------------------------------------------------- 737 * |Bits |Field |Descriptions 738 * | :----: | :----: | :---- | 739 * |[3:0] |UART2DIV |UART2 Clock Divide Number from UART2 Clock Source 740 * | | |UART2 clock frequency = (UART2 clock source frequency) / (UART2DIV + 1). 741 * |[7:4] |UART3DIV |UART3 Clock Divide Number from UART3 Clock Source 742 * | | |UART3 clock frequency = (UART3 clock source frequency) / (UART3DIV + 1). 743 * |[11:8] |UART4DIV |UART4 Clock Divide Number from UART4 Clock Source 744 * | | |UART4 clock frequency = (UART4 clock source frequency) / (UART4DIV + 1). 745 * |[15:12] |UART5DIV |UART5 Clock Divide Number from UART5 Clock Source 746 * | | |UART5 clock frequency = (UART5 clock source frequency) / (UART5DIV + 1). 747 * |[19:16] |UART6DIV |UART6 Clock Divide Number from UART6 Clock Source 748 * | | |UART6 clock frequency = (UART6 clock source frequency) / (UART6DIV + 1). 749 * |[23:20] |UART7DIV |UART7 Clock Divide Number from UART7 Clock Source 750 * | | |UART7 clock frequency = (UART7 clock source frequency) / (UART7DIV + 1). 751 * @var CLK_T::PCLKDIV 752 * Offset: 0x34 APB Clock Divider Register 753 * --------------------------------------------------------------------------------------------------- 754 * |Bits |Field |Descriptions 755 * | :----: | :----: | :---- | 756 * |[2:0] |APB0DIV |APB0 Clock Divider 757 * | | |APB0 clock can be divided from HCLK. 758 * | | |000 = PCLK0 frequency is HCLK. 759 * | | |001 = PCLK0 frequency is HCLK/2. 760 * | | |010 = PCLK0 frequency is HCLK/4. 761 * | | |011 = PCLK0 frequency is HCLK/8. 762 * | | |100 = PCLK0 frequency is HCLK/16. 763 * | | |Others = Reserved. 764 * |[6:4] |APB1DIV |APB1 Clock Divider 765 * | | |APB1 clock can be divided from HCLK. 766 * | | |000 = PCLK1 frequency is HCLK. 767 * | | |001 = PCLK1 frequency is HCLK/2. 768 * | | |010 = PCLK1 frequency is HCLK/4. 769 * | | |011 = PCLK1 frequency is HCLK/8. 770 * | | |100 = PCLK1 frequency is HCLK/16. 771 * | | |Others = Reserved. 772 * @var CLK_T::APBCLK2 773 * Offset: 0x38 APB Devices Clock Enable Control Register 2 774 * --------------------------------------------------------------------------------------------------- 775 * |Bits |Field |Descriptions 776 * | :----: | :----: | :---- | 777 * |[0] |KPICKEN |KPI Clock Enable Bit 778 * | | |0 = KPI clock Disabled. 779 * | | |1 = KPI clock Enabled. 780 * |[6] |EADC2CKEN |EADC2 Clock Enable Bit 781 * | | |0 = EADC2 clock Disabled. 782 * | | |1 = EADC2 clock Enabled. 783 * |[7] |ACMP23CKEN|Analog Comparator 2/3 Clock Enable Bit 784 * | | |0 = Analog Comparator 2/3 clock Disabled. 785 * | | |1 = Analog Comparator 2/3 clock Enabled. 786 * |[8] |SPI5CKEN |SPI5 Clock Enable Bit 787 * | | |0 = SPI5 clock Disabled. 788 * | | |1 = SPI5 clock Enabled. 789 * |[9] |SPI6CKEN |SPI6 Clock Enable Bit 790 * | | |0 = SPI6 clock Disabled. 791 * | | |1 = SPI6 clock Enabled. 792 * |[10] |SPI7CKEN |SPI7 Clock Enable Bit 793 * | | |0 = SPI7 clock Disabled. 794 * | | |1 = SPI7 clock Enabled. 795 * |[11] |SPI8CKEN |SPI8 Clock Enable Bit 796 * | | |0 = SPI8 clock Disabled. 797 * | | |1 = SPI8 clock Enabled. 798 * |[12] |SPI9CKEN |SPI9 Clock Enable Bit 799 * | | |0 = SPI9 clock Disabled. 800 * | | |1 = SPI9 clock Enabled. 801 * |[13] |SPI10CKEN |SPI10 Clock Enable Bit 802 * | | |0 = SPI10 clock Disabled. 803 * | | |1 = SPI10 clock Enabled. 804 * |[16] |UART8CKEN |UART8 Clock Enable Bit 805 * | | |0 = UART8 clock Disabled. 806 * | | |1 = UART8 clock Enabled. 807 * |[17] |UART9CKEN |UART9 Clock Enable Bit 808 * | | |0 = UART9 clock Disabled. 809 * | | |1 = UART9 clock Enabled. 810 * @var CLK_T::CLKDIV5 811 * Offset: 0x3C Clock Divider Number Register 5 812 * --------------------------------------------------------------------------------------------------- 813 * |Bits |Field |Descriptions 814 * | :----: | :----: | :---- | 815 * |[3:0] |CANFD0DIV |CANFD0 Clock Divide Number from CANFD0 Clock Source 816 * | | |CANFD0 clock frequency = (CANFD0 clock source frequency) / (CANFD0DIV + 1). 817 * |[7:4] |CANFD1DIV |CANFD1 Clock Divide Number from CANFD1 Clock Source 818 * | | |CANFD1 clock frequency = (CANFD1 clock source frequency) / (CANFD1DIV + 1). 819 * |[11:8] |CANFD2DIV |CANFD2 Clock Divide Number from CANFD2 Clock Source 820 * | | |CANFD2 clock frequency = (CANFD2 clock source frequency) / (CANFD2DIV + 1). 821 * |[15:12] |CANFD3DIV |CANFD3 Clock Divide Number from CANFD3 Clock Source 822 * | | |CANFD3 clock frequency = (CANFD3 clock source frequency) / (CANFD3DIV + 1). 823 * |[19:16] |UART8DIV |UART6 Clock Divide Number from UART8 Clock Source 824 * | | |UART6 clock frequency = (UART8 clock source frequency) / (UART8DIV + 1). 825 * |[23:20] |UART9DIV |UART7 Clock Divide Number from UART9 Clock Source 826 * | | |UART7 clock frequency = (UART9 clock source frequency) / (UART9DIV + 1). 827 * |[31:24] |EADC2DIV |EADC2 Clock Divide Number from EADC2 Clock Source 828 * | | |EADC2 clock frequency = (EADC2 clock source frequency) / (EADC2DIV + 1). 829 * @var CLK_T::PLLCTL 830 * Offset: 0x40 PLL Control Register 831 * --------------------------------------------------------------------------------------------------- 832 * |Bits |Field |Descriptions 833 * | :----: | :----: | :---- | 834 * |[8:0] |FBDIV |PLL Feedback Divider Control (Write Protect) 835 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 836 * |[13:9] |INDIV |PLL Input Divider Control (Write Protect) 837 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 838 * |[15:14] |OUTDIV |PLL Output Divider Control (Write Protect) 839 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 840 * |[16] |PD |Power-down Mode (Write Protect) 841 * | | |If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too. 842 * | | |0 = PLL is in normal mode. 843 * | | |1 = PLL is in Power-down mode (default). 844 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 845 * |[17] |BP |PLL Bypass Control (Write Protect) 846 * | | |0 = PLL is in normal mode (default). 847 * | | |1 = PLL clock output is same as PLL input clock FIN. 848 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 849 * |[18] |OE |PLL FOUT Enable Control (Write Protect) 850 * | | |0 = PLL FOUT Enabled. 851 * | | |1 = PLL FOUT is fixed low. 852 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 853 * |[19] |PLLSRC |PLL Source Clock Selection (Write Protect) 854 * | | |0 = PLL source clock from 4~24 MHz external high-speed crystal oscillator (HXT). 855 * | | |1 = PLL source clock from 12 MHz internal high-speed oscillator (HIRC). 856 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 857 * |[23] |STBSEL |PLL Stable Counter Selection (Write Protect) 858 * | | |0 = PLL stable time is 1200 PLL source clock (suitable for source clock equal to or less than 12 MHz). 859 * | | |1 = PLL stable time is 2400 PLL source clock (suitable for source clock larger than 12 MHz). 860 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 861 * @var CLK_T::PLLFNCTL0 862 * Offset: 0x48 PLLFN Control Register 0 863 * --------------------------------------------------------------------------------------------------- 864 * |Bits |Field |Descriptions 865 * | :----: | :----: | :---- | 866 * |[8:0] |FBDIV |PLL Feedback Divider Control (Write Protect) 867 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 868 * |[13:9] |INDIV |PLL Input Divider Control (Write Protect) 869 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 870 * |[15:14] |OUTDIV |PLL Output Divider Control (Write Protect) 871 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 872 * |[27:16] |FRDIV |PLL Fractional Divider Control (Write Protect) 873 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 874 * @var CLK_T::PLLFNCTL1 875 * Offset: 0x4C PLLFN Control Register 1 876 * --------------------------------------------------------------------------------------------------- 877 * |Bits |Field |Descriptions 878 * | :----: | :----: | :---- | 879 * |[27] |STBSEL |PLL Stable Counter Selection (Write Protect) 880 * | | |0 = PLL stable time is 1200 PLL source clock (suitable for source clock equal to or less than 12 MHz). 881 * | | |1 = PLL stable time is 2400 PLL source clock (suitable for source clock larger than 12 MHz). 882 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 883 * |[28] |PD |Power-down Mode (Write Protect) 884 * | | |If set the PDEN bit to 1 in CLK_PWRCTL register, the PLL will enter Power-down mode, too. 885 * | | |0 = PLL is in normal mode. 886 * | | |1 = PLL is in Power-down mode (default). 887 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 888 * |[29] |BP |PLL Bypass Control (Write Protect) 889 * | | |0 = PLL is in normal mode (default). 890 * | | |1 = PLL clock output is same as PLL input clock FIN. 891 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 892 * |[30] |OE |PLL FOUT Enable Control (Write Protect) 893 * | | |0 = PLL FOUT Enabled. 894 * | | |1 = PLL FOUT is fixed low. 895 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 896 * |[31] |PLLSRC |PLL Source Clock Selection (Write Protect) 897 * | | |0 = PLL source clock from 4~32 MHz external high-speed crystal oscillator (HXT). 898 * | | |1 = PLL source clock from 12 MHz internal high-speed oscillator (HIRC). 899 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 900 * @var CLK_T::STATUS 901 * Offset: 0x50 Clock Status Monitor Register 902 * --------------------------------------------------------------------------------------------------- 903 * |Bits |Field |Descriptions 904 * | :----: | :----: | :---- | 905 * |[0] |HXTSTB |HXT Clock Source Stable Flag (Read Only) 906 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled. 907 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled. 908 * |[1] |LXTSTB |LXT Clock Source Stable Flag (Read Only) 909 * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled. 910 * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled. 911 * |[2] |PLLSTB |Internal PLL Clock Source Stable Flag (Read Only) 912 * | | |0 = Internal PLL clock is not stable or disabled. 913 * | | |1 = Internal PLL clock is stable and enabled. 914 * |[3] |LIRCSTB |LIRC Clock Source Stable Flag (Read Only) 915 * | | |0 = 10 kHz internal low speed RC oscillator (LIRC) clock is not stable or disabled. 916 * | | |1 = 10 kHz internal low speed RC oscillator (LIRC) clock is stable and enabled. 917 * |[4] |HIRCSTB |HIRC Clock Source Stable Flag (Read Only) 918 * | | |0 = 12 MHz internal high speed RC oscillator (HIRC) clock is not stable or disabled. 919 * | | |1 = 12 MHz internal high speed RC oscillator (HIRC) clock is stable and enabled. 920 * |[6] |HIRC48MSTB|HIRC48M Clock Source Stable Flag (Read Only) 921 * | | |0 = 48 MHz internal high speed RC oscillator (HIRC48M) clock is not stable or disabled. 922 * | | |1 = 48 MHz internal high speed RC oscillator (HIRC48M) clock is stable and enabled. 923 * |[7] |CLKSFAIL |Clock Switching Fail Flag (Read Only) 924 * | | |This bit is updated when software switches system clock source 925 * | | |If switch target clock is stable, this bit will be set to 0 926 * | | |If switch target clock is not stable, this bit will be set to 1. 927 * | | |0 = Clock switching success. 928 * | | |1 = Clock switching failure. 929 * | | |Note: This bit is read only. 930 * | | |After selected clock source is stable, hardware will switch system clock to selected clock automatically, and CLKSFAIL will be cleared automatically by hardware. 931 * |[10] |PLLFNSTB |Internal PLLFN Clock Source Stable Flag 932 * | | |0 = Internal PLLFN clock is not stable or disabled. 933 * | | |1 = Internal PLLFN clock is stable. 934 * | | |Note: This bit is read only. 935 * @var CLK_T::AHBCLK1 936 * Offset: 0x58 AHB Devices Clock Enable Control Register 1 937 * --------------------------------------------------------------------------------------------------- 938 * |Bits |Field |Descriptions 939 * | :----: | :----: | :---- | 940 * |[20] |CANFD0CKEN|CANFD0 Clock Enable Bit 941 * | | |0 = CANFD0 clock Disabled. 942 * | | |1 = CANFD0 clock Enabled. 943 * |[21] |CANFD1CKEN|CANFD1 Clock Enable Bit 944 * | | |0 = CANFD1 clock Disabled. 945 * | | |1 = CANFD1 clock Enabled. 946 * |[22] |CANFD2CKEN|CANFD2 Clock Enable Bit 947 * | | |0 = CANFD2 clock Disabled. 948 * | | |1 = CANFD2 clock Enabled. 949 * |[23] |CANFD3CKEN|CANFD3 Clock Enable Bit 950 * | | |0 = CANFD3 clock Disabled. 951 * | | |1 = CANFD3 clock Enabled. 952 * |[24] |GPICKEN |GPIOI Clock Enable Bit 953 * | | |0 = GPIOI clock Disabled. 954 * | | |1 = GPIOI clock Enabled. 955 * |[25] |GPJCKEN |GPIOJ Clock Enable Bit 956 * | | |0 = GPIOJ clock Disabled. 957 * | | |1 = GPIOJ clock Enabled. 958 * |[28] |BMCCKEN |BMC Clock Enable Bit 959 * | | |0 = BMC clock Disabled. 960 * | | |1 = BMC clock Enabled. 961 * @var CLK_T::CLKSEL4 962 * Offset: 0x5C Clock Source Select Control Register 4 963 * --------------------------------------------------------------------------------------------------- 964 * |Bits |Field |Descriptions 965 * | :----: | :----: | :---- | 966 * |[2:0] |SPI4SEL |SPI4 Clock Source Selection 967 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 968 * | | |001 = Clock source from PLL/2. 969 * | | |010 = Clock source from PCLK1. 970 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 971 * | | |Others = Reserved. 972 * |[6:4] |SPI5SEL |SPI5 Clock Source Selection 973 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 974 * | | |001 = Clock source from PLL/2. 975 * | | |010 = Clock source from PCLK0. 976 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 977 * | | |Others = Reserved. 978 * |[10:8] |SPI6SEL |SPI6 Clock Source Selection 979 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 980 * | | |001 = Clock source from PLL/2. 981 * | | |010 = Clock source from PCLK1. 982 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 983 * | | |Others = Reserved. 984 * |[14:12] |SPI7SEL |SPI7 Clock Source Selection 985 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 986 * | | |001 = Clock source from PLL/2. 987 * | | |010 = Clock source from PCLK1. 988 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 989 * | | |Others = Reserved. 990 * |[18:16] |SPI8SEL |SPI8 Clock Source Selection 991 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 992 * | | |001 = Clock source from PLL/2. 993 * | | |010 = Clock source from PCLK0. 994 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 995 * | | |Others = Reserved. 996 * |[22:20] |SPI9SEL |SPI9 Clock Source Selection 997 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 998 * | | |001 = Clock source from PLL/2. 999 * | | |010 = Clock source from PCLK1. 1000 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 1001 * | | |Others = Reserved. 1002 * |[26:24] |SPI10SEL |SPI10 Clock Source Selection 1003 * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). 1004 * | | |001 = Clock source from PLL/2. 1005 * | | |010 = Clock source from PCLK1. 1006 * | | |011 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). 1007 * | | |Others = Reserved. 1008 * @var CLK_T::CLKOCTL 1009 * Offset: 0x60 Clock Output Control Register 1010 * --------------------------------------------------------------------------------------------------- 1011 * |Bits |Field |Descriptions 1012 * | :----: | :----: | :---- | 1013 * |[3:0] |FREQSEL |Clock Output Frequency Selection 1014 * | | |The formula of output frequency is Fout = Fin/2^(N+1). 1015 * | | |Fin is the input clock frequency. 1016 * | | |Fout is the frequency of divider output clock. 1017 * | | |N is the 4-bit value of FREQSEL[3:0]. 1018 * |[4] |CLKOEN |Clock Output Enable Bit 1019 * | | |0 = Clock Output function Disabled. 1020 * | | |1 = Clock Output function Enabled. 1021 * |[5] |DIV1EN |Clock Output Divide One Enable Bit 1022 * | | |0 = Clock Output will output clock with source frequency divided by FREQSEL. 1023 * | | |1 = Clock Output will output clock with source frequency. 1024 * |[6] |CLK1HZEN |Clock Output 1Hz Enable Bit 1025 * | | |0 = 1 Hz clock output for 32.768 kHz frequency compensation Disabled. 1026 * | | |1 = 1 Hz clock output for 32.768 kHz frequency compensation Enabled. 1027 * @var CLK_T::CLKDCTL 1028 * Offset: 0x70 Clock Fail Detector Control Register 1029 * --------------------------------------------------------------------------------------------------- 1030 * |Bits |Field |Descriptions 1031 * | :----: | :----: | :---- | 1032 * |[4] |HXTFDEN |HXT Clock Fail Detector Enable Bit 1033 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Disabled. 1034 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail detector Enabled. 1035 * |[5] |HXTFIEN |HXT Clock Fail Interrupt Enable Bit 1036 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Disabled. 1037 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock fail interrupt Enabled. 1038 * |[12] |LXTFDEN |LXT Clock Fail Detector Enable Bit 1039 * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Disabled. 1040 * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail detector Enabled. 1041 * |[13] |LXTFIEN |LXT Clock Fail Interrupt Enable Bit 1042 * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Disabled. 1043 * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock fail interrupt Enabled. 1044 * |[16] |HXTFQDEN |HXT Clock Frequency Range Detector Enable Bit 1045 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector Disabled. 1046 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector Enabled. 1047 * |[17] |HXTFQIEN |HXT Clock Frequency Range Detector Interrupt Enable Bit 1048 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Disabled. 1049 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail interrupt Enabled. 1050 * |[18] |HXTFQASW |HXT Clock Frequency Range Detector Event Auto Switch Enable Bit 1051 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail event happened and HCLK will not switch to HIRC automatically. 1052 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency range detector fail event happened and HCLK will switch to HIRC automatically. 1053 * | | |Note: This bit should be set before HXTFQDEN(CLK_CLKDCTL[16]). 1054 * @var CLK_T::CLKDSTS 1055 * Offset: 0x74 Clock Fail Detector Status Register 1056 * --------------------------------------------------------------------------------------------------- 1057 * |Bits |Field |Descriptions 1058 * | :----: | :----: | :---- | 1059 * |[0] |HXTFIF |HXT Clock Fail Interrupt Flag (Write Protect) 1060 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is normal. 1061 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock stops. 1062 * | | |Note 1: Write 1 to clear the bit to 0. 1063 * | | |Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. 1064 * |[1] |LXTFIF |LXT Clock Fail Interrupt Flag (Write Protect) 1065 * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is normal. 1066 * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) stops. 1067 * | | |Note 1: Write 1 to clear the bit to 0. 1068 * | | |Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. 1069 * |[8] |HXTFQIF |HXT Clock Frequency Range Detector Interrupt Flag (Write Protect) 1070 * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is normal. 1071 * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock frequency is abnormal. 1072 * | | |Note 1: Write 1 to clear the bit to 0. 1073 * | | |Note 2: This bit is write protected. Refer to the SYS_REGLCTL register. 1074 * @var CLK_T::CDUPB 1075 * Offset: 0x78 Clock Frequency Range Detector Upper Boundary Register 1076 * --------------------------------------------------------------------------------------------------- 1077 * |Bits |Field |Descriptions 1078 * | :----: | :----: | :---- | 1079 * |[9:0] |UPERBD |HXT Clock Frequency Range Detector Upper Boundary Value 1080 * | | |The bits define the maximum value of frequency range detector window. 1081 * | | |When HXT frequency higher than this maximum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1. 1082 * @var CLK_T::CDLOWB 1083 * Offset: 0x7C Clock Frequency Range Detector Lower Boundary Register 1084 * --------------------------------------------------------------------------------------------------- 1085 * |Bits |Field |Descriptions 1086 * | :----: | :----: | :---- | 1087 * |[9:0] |LOWERBD |HXT Clock Frequency Range Detector Lower Boundary Value 1088 * | | |The bits define the minimum value of frequency range detector window. 1089 * | | |When HXT frequency lower than this minimum frequency value, the HXT Clock Frequency Range Detector Interrupt Flag will set to 1. 1090 * @var CLK_T::STOPREQ 1091 * Offset: 0x80 Clock Stop Request Register 1092 * --------------------------------------------------------------------------------------------------- 1093 * |Bits |Field |Descriptions 1094 * | :----: | :----: | :---- | 1095 * |[0] |CANFD0STR |CANFD0 Clock Stop Request 1096 * | | |This bit is used to stop CANFD0 clock. 1097 * | | |0 = CANFD0 clock is not stoped by this bit. (default) 1098 * | | |1 = Set this bit and check the CANFD0STA(CLK_STOPACK[0]) is 1, then CANFD0 clock stop. 1099 * |[1] |CANFD1STR |CANFD1 Clock Stop Request 1100 * | | |This bit is used to stop CANFD1 clock. 1101 * | | |0 = CANFD1 clock is not stoped by this bit. (default) 1102 * | | |1 = Set this bit and check the CANFD1STA(CLK_STOPACK[1]) is 1, then CANFD1 clock stop. 1103 * |[2] |CANFD2STR |CANFD2 Clock Stop Request 1104 * | | |This bit is used to stop CANFD2 clock. 1105 * | | |0 = CANFD2 clock is not stoped by this bit. (default) 1106 * | | |1 = Set this bit and check the CANFD2STA(CLK_STOPACK[2]) is 1, then CANFD2 clock stop. 1107 * |[3] |CANFD3STR |CANFD3 Clock Stop Request 1108 * | | |This bit is used to stop CANFD3 clock. 1109 * | | |0 = CANFD3 clock is not stoped by this bit. (default) 1110 * | | |1 = Set this bit and check the CANFD3STA(CLK_STOPACK[3]) is 1, then CANFD3 clock stop. 1111 * @var CLK_T::STOPACK 1112 * Offset: 0x84 Clock Stop Acknowledge Register 1113 * --------------------------------------------------------------------------------------------------- 1114 * |Bits |Field |Descriptions 1115 * | :----: | :----: | :---- | 1116 * |[0] |CANFD0STA |CANFD0 Clock Stop Acknowledge (Read Only) 1117 * | | |This bit is used to check CANFD0 clock stop by setting CANFD0STR(CLK_STOPREQ[0]). 1118 * | | |0 = CANFD0 clock not stoped. 1119 * | | |1 = CANFD0 clock stoped. 1120 * |[1] |CANFD1STA |CANFD1 Clock Stop Acknowledge (Read Only) 1121 * | | |This bit is used to check CANFD1 clock stop by setting CANFD1STR(CLK_STOPREQ[1]). 1122 * | | |0 = CANFD1 clock not stoped. 1123 * | | |1 = CANFD1 clock stoped. 1124 * |[2] |CANFD2STA |CANFD2 Clock Stop Acknowledge (Read Only) 1125 * | | |This bit is used to check CANFD2 clock stop by setting CANFD2STR(CLK_STOPREQ[2]). 1126 * | | |0 = CANFD2 clock not stoped. 1127 * | | |1 = CANFD2 clock stoped. 1128 * |[3] |CAN3STACK |CANFD3 Clock Stop Acknowledge (Read Only) 1129 * | | |This bit is used to check CANFD3 clock stop by setting CANFD3STR(CLK_STOPREQ[3]). 1130 * | | |0 = CANFD3 clock not stoped. 1131 * | | |1 = CANFD3 clock stoped. 1132 * @var CLK_T::PMUCTL 1133 * Offset: 0x90 Power Manager Control Register 1134 * --------------------------------------------------------------------------------------------------- 1135 * |Bits |Field |Descriptions 1136 * | :----: | :----: | :---- | 1137 * |[2:0] |PDMSEL |Power-down Mode Selection (Write Protect) 1138 * | | |These bits control chip power-down mode grade selection when CPU execute WFI/WFE instruction. 1139 * | | |000 = Normal Power-down mode is selected (NPD). 1140 * | | |001 = Low leakage Power-down mode is selected (LLPD). 1141 * | | |010 = Fast wake-up Power-down mode is selected (FWPD). 1142 * | | |011 = Reserved. 1143 * | | |100 = Standby Power-down mode is selected (SPD). 1144 * | | |101 = Reserved. 1145 * | | |110 = Deep Power-down mode is selected (DPD). 1146 * | | |111 = Reserved. 1147 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 1148 * |[3] |DPDHOLDEN |Deep-Power-Down Mode GPIO Hold Enable Bit (Write Protect) 1149 * | | |0= When GPIO enters deep power-down mode, all I/O status are tri-state. 1150 * | | |1= When GPIO enters deep power-down mode, all I/O status are hold to keep normal operating status. 1151 * | | |After chip was woken up from deep power-down mode, the I/O are still keep hold status until user set CLK_IOPDCTL[0] to release I/O hold status. 1152 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1153 * |[6:4] |SRETSEL |SRAM Retention Range Select Bit (Write Protect) 1154 * | | |Select SRAM retention range when chip enter SPD mode. 1155 * | | |000 = No SRAM retention. 1156 * | | |001 = 16K SRAM retention when chip enter SPD mode. 1157 * | | |010 = 32K SRAM retention when chip enter SPD mode. 1158 * | | |011 = 64K SRAM retention when chip enter SPD mode. 1159 * | | |100 = 128K SRAM retention when chip enter SPD mode. (default) 1160 * | | |101 = 256K SRAM retention when chip enter SPD mode. 1161 * | | |Others = Reserved. 1162 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 1163 * |[8] |WKTMREN |Wake-up Timer Enable Bit (Write Protect) 1164 * | | |0 = Wake-up timer disabled at DPD/SPD mode. 1165 * | | |1 = Wake-up timer enabled at DPD/SPD mode. 1166 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1167 * |[12:9] |WKTMRIS |Wake-up Timer Time-out Interval Select (Write Protect) 1168 * | | |These bits control wake-up timer time-out interval when chip at DPD/SPD mode. 1169 * | | |0000 = Time-out interval is 128 LIRC clocks (12.8 ms). 1170 * | | |0001 = Time-out interval is 256 LIRC clocks (25.6 ms). 1171 * | | |0010 = Time-out interval is 512 LIRC clocks (51.2 ms). 1172 * | | |0011 = Time-out interval is 1024 LIRC clocks (102.4ms). 1173 * | | |0100 = Time-out interval is 4096 LIRC clocks (409.6ms). 1174 * | | |0101 = Time-out interval is 8192 LIRC clocks (819.2ms). 1175 * | | |0110 = Time-out interval is 16384 LIRC clocks (1638.4ms). 1176 * | | |0111 = Time-out interval is 65536 LIRC clocks (6553.6ms). 1177 * | | |1000 = Time-out interval is 131072 LIRC clocks (13107.2ms). 1178 * | | |1001 = Time-out interval is 262144 LIRC clocks (26214.4ms). 1179 * | | |1010 = Time-out interval is 524288 LIRC clocks (52428.8ms). 1180 * | | |1011 = Time-out interval is 1048576 LIRC clocks (104857.6ms). 1181 * | | |Others = Time-out interval is 128 LIRC clocks (12.8ms). 1182 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 1183 * |[17:16] |WKPINEN0 |Wake-up Pin0 Enable Bit (Write Protect) 1184 * | | |This is control register for GPC.0 to wake-up pin. 1185 * | | |00 = Wake-up pin disabled at Deep Power-down mode. 1186 * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. 1187 * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. 1188 * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. 1189 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 1190 * |[18] |ACMPSPWK |ACMP Standby Power-down Mode Wake-up Enable Bit (Write Protect) 1191 * | | |0 = ACMP wake-up disabled at Standby Power-down mode. 1192 * | | |1 = ACMP wake-up enabled at Standby Power-down mode. 1193 * | | |Note 1: This bit is write protected. Refer to the SYS_REGLCTL register. 1194 * | | |Note 2: Set FILTSEL(ACMP_CTLx[15:13]) for comparator output filter count selection, the filter clock is LIRC in ACMP SPD mode wakeup function. 1195 * |[22] |VBUSWKEN |VBUS Wake-up Enable Bit (Write Protect) 1196 * | | |0 = VBUS transition wake-up disabled at Deep Power-down mode. 1197 * | | |1 = VBUS transition wake-up enabled at Deep Power-down mode. 1198 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1199 * |[23] |RTCWKEN |RTC Wake-up Enable Bit (Write Protect) 1200 * | | |0 = RTC wake-up disabled at Deep Power-down mode or Standby Power-down mode. 1201 * | | |1 = RTC wake-up enabled at Deep Power-down mode or Standby Power-down mode. 1202 * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. 1203 * |[25:24] |WKPINEN1 |Wake-up Pin1 Enable Bit (Write Protect) 1204 * | | |This is control register for GPB.0 to wake-up pin. 1205 * | | |00 = Wake-up pin disable at Deep Power-down mode. 1206 * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. 1207 * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. 1208 * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. 1209 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 1210 * |[27:26] |WKPINEN2 |Wake-up Pin2 Enable Bit (Write Protect) 1211 * | | |This is control register for GPB.2 to wake-up pin. 1212 * | | |00 = Wake-up pin disabled at Deep Power-down mode. 1213 * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. 1214 * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. 1215 * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. 1216 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 1217 * |[29:28] |WKPINEN3 |Wake-up Pin3 Enable Bit (Write Protect) 1218 * | | |This is control register for GPB.12 to wake-up pin. 1219 * | | |00 = Wake-up pin disabled at Deep Power-down mode. 1220 * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. 1221 * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. 1222 * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. 1223 * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. 1224 * |[31:30] |WKPINEN4 |Wake-up Pin4 Enable Bit (Write Protect) 1225 * | | |This is control register for GPF.6 to wake-up pin. 1226 * | | |00 = Wake-up pin disabled at Deep Power-down mode. 1227 * | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. 1228 * | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. 1229 * | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. 1230 * | | |Note 1: These bits are write protected. Refer to the SYS_REGLCTL register. 1231 * | | |Note 2: To use GPF.6 wake-up pin function at Deep Power-down mode, user has to set IOCTLSEL(RTC_LXTCTL[8])=1 to control GPF.6 in VBAT power domain by RTC_GPIOCTL0. 1232 * | | |Otherwise, GPF.6 will be digital off (digital input tied to low) in DPD mode and cause unexpected falling edge to wake-up system. 1233 * @var CLK_T::PMUSTS 1234 * Offset: 0x94 Power Manager Status Register 1235 * --------------------------------------------------------------------------------------------------- 1236 * |Bits |Field |Descriptions 1237 * | :----: | :----: | :---- | 1238 * |[0] |PINWK0 |Pin0 Wake-up Flag (Read Only) 1239 * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (GPC.0). 1240 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD mode. 1241 * |[1] |TMRWK |Timer Wake-up Flag (Read Only) 1242 * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested by wakeup timer time-out. 1243 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD/DPD mode. 1244 * |[2] |RTCWK |RTC Wake-up Flag (Read Only) 1245 * | | |This flag indicates that wakeup of device from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested with a RTC alarm, tick time or tamper happened. 1246 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD/DPD mode. 1247 * |[3] |PINWK1 |Pin1 Wake-up Flag (Read Only) 1248 * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PB.0). 1249 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD mode. 1250 * |[4] |PINWK2 |Pin2 Wake-up Flag (Read Only) 1251 * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PB.2). 1252 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD mode. 1253 * |[5] |PINWK3 |Pin3 Wake-up Flag (Read Only) 1254 * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PB.12). 1255 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD mode. 1256 * |[6] |PINWK4 |Pin4 Wake-up Flag (Read Only) 1257 * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PF.6). 1258 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD mode. 1259 * |[7] |VBUSWK |VBUS Wake-up Flag( Read Only) 1260 * | | |This flag indicates that wake-up of chip from Deep Power-down mode was requested by a transition of the WAKEUP pin (PA.12). 1261 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering DPD mode. 1262 * |[8] |GPAWK |GPA Wake-up Flag (Read Only) 1263 * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPA group pins. 1264 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode. 1265 * |[9] |GPBWK |GPB Wake-up Flag (Read Only) 1266 * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPB group pins. 1267 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode. 1268 * |[10] |GPCWK |GPC Wake-up Flag (Read Only) 1269 * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPC group pins. 1270 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode. 1271 * |[11] |GPDWK |GPD Wake-up Flag (Read Only) 1272 * | | |This flag indicates that wake-up of chip from Standby Power-down mode was requested by a transition of selected one GPD group pins. 1273 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode. 1274 * |[12] |LVRWK |LVR Wake-up Flag (Read Only) 1275 * | | |This flag indicates that wakeup of device from Standby Power-down mode was requested with a LVR happened. 1276 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode. 1277 * |[13] |BODWK |BOD Wake-up Flag (Read Only) 1278 * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a BOD happened. 1279 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode. 1280 * |[15] |RSTWK |RST pin Wake-up Flag (Read Only) 1281 * | | |This flag indicates that wakeup of device from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested with a RST pin trigger happened. 1282 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD/DPD mode. 1283 * |[16] |ACMPWK0 |ACMP0 Wake-up Flag (Read Only) 1284 * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with an ACMP0 transition. 1285 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode. 1286 * |[17] |ACMPWK1 |ACMP1 Wake-up Flag (Read Only) 1287 * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with an ACMP1 transition. 1288 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode. 1289 * |[18] |ACMPWK2 |ACMP2 Wake-up Flag (Read Only) 1290 * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with an ACMP2 transition. 1291 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode. 1292 * |[19] |ACMPWK3 |ACMP3 Wake-up Flag (Read Only) 1293 * | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with an ACMP3 transition. 1294 * | | |Note: This flag needs to be cleared by setting CLRWK(CLK_PMUSTS[31] when entering SPD mode. 1295 * |[31] |CLRWK |Clear Wake-up Flag 1296 * | | |0 = No clear. 1297 * | | |1= Clear all wake-up flag. 1298 * | | |Note: This bit is auto cleared by hardware. 1299 * @var CLK_T::SWKDBCTL 1300 * Offset: 0x9C GPIO Standby Power-down Wake-up De-bounce Control Register 1301 * --------------------------------------------------------------------------------------------------- 1302 * |Bits |Field |Descriptions 1303 * | :----: | :----: | :---- | 1304 * |[3:0] |SWKDBCLKSEL|Standby Power-down Wake-up De-bounce Sampling Cycle Selection 1305 * | | |0000 = Sample wake-up input once per 1 clock. 1306 * | | |0001 = Sample wake-up input once per 2 clocks. 1307 * | | |0010 = Sample wake-up input once per 4 clocks. 1308 * | | |0011 = Sample wake-up input once per 8 clocks. 1309 * | | |0100 = Sample wake-up input once per 16 clocks. 1310 * | | |0101 = Sample wake-up input once per 32 clocks. 1311 * | | |0110 = Sample wake-up input once per 64 clocks. 1312 * | | |0111 = Sample wake-up input once per 128 clocks. 1313 * | | |1000 = Sample wake-up input once per 256 clocks. 1314 * | | |1001 = Sample wake-up input once per 2*256 clocks. 1315 * | | |1010 = Sample wake-up input once per 4*256 clocks. 1316 * | | |1011 = Sample wake-up input once per 8*256 clocks. 1317 * | | |1100 = Sample wake-up input once per 16*256 clocks. 1318 * | | |1101 = Sample wake-up input once per 32*256 clocks. 1319 * | | |1110 = Sample wake-up input once per 64*256 clocks. 1320 * | | |1111 = Sample wake-up input once per 128*256 clocks.. 1321 * | | |Note: De-bounce counter clock source is the 10 kHz internal low speed RC oscillator (LIRC). 1322 * @var CLK_T::PASWKCTL 1323 * Offset: 0xA0 GPA Standby Power-down Wake-up Control Register 1324 * --------------------------------------------------------------------------------------------------- 1325 * |Bits |Field |Descriptions 1326 * | :----: | :----: | :---- | 1327 * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit 1328 * | | |0 = GPA group pin wake-up function Disabled. 1329 * | | |1 = GPA group pin wake-up function Enabled. 1330 * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit 1331 * | | |0 = GPA group pin rising edge wake-up function Disabled. 1332 * | | |1 = GPA group pin rising edge wake-up function Enabled. 1333 * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit 1334 * | | |0 = GPA group pin falling edge wake-up function Disabled. 1335 * | | |1 = GPA group pin falling edge wake-up function Enabled. 1336 * |[7:4] |WKPSEL |GPA Standby Power-down Wake-up Pin Select 1337 * | | |0000 = GPA.0 wake-up function Enabled. 1338 * | | |0001 = GPA.1 wake-up function Enabled. 1339 * | | |0010 = GPA.2 wake-up function Enabled. 1340 * | | |0011 = GPA.3 wake-up function Enabled. 1341 * | | |0100 = GPA.4 wake-up function Enabled. 1342 * | | |0101 = GPA.5 wake-up function Enabled. 1343 * | | |0110 = GPA.6 wake-up function Enabled. 1344 * | | |0111 = GPA.7 wake-up function Enabled. 1345 * | | |1000 = GPA.8 wake-up function Enabled. 1346 * | | |1001 = GPA.9 wake-up function Enabled. 1347 * | | |1010 = GPA.10 wake-up function Enabled. 1348 * | | |1011 = GPA.11 wake-up function Enabled. 1349 * | | |1100 = GPA.12 wake-up function Enabled. 1350 * | | |1101 = GPA.13 wake-up function Enabled. 1351 * | | |1110 = GPA.14 wake-up function Enabled. 1352 * | | |1111 = GPA.15 wake-up function Enabled. 1353 * |[8] |DBEN |GPA Input Signal De-bounce Enable Bit 1354 * | | |The DBEN bit is used to enable the de-bounce function for each corresponding I/O. 1355 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up. 1356 * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC). 1357 * | | |0 = Standby power-down wake-up pin De-bounce function Disabled. 1358 * | | |1 = Standby power-down wake-up pin De-bounce function Enabled. 1359 * | | |The de-bounce function is valid only for edge triggered. 1360 * @var CLK_T::PBSWKCTL 1361 * Offset: 0xA4 GPB Standby Power-down Wake-up Control Register 1362 * --------------------------------------------------------------------------------------------------- 1363 * |Bits |Field |Descriptions 1364 * | :----: | :----: | :---- | 1365 * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit 1366 * | | |0 = GPB group pin wake-up function Disabled. 1367 * | | |1 = GPB group pin wake-up function Enabled. 1368 * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit 1369 * | | |0 = GPB group pin rising edge wake-up function Disabled. 1370 * | | |1 = GPB group pin rising edge wake-up function Enabled. 1371 * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit 1372 * | | |0 = GPB group pin falling edge wake-up function Disabled. 1373 * | | |1 = GPB group pin falling edge wake-up function Enabled. 1374 * |[7:4] |WKPSEL |GPB Standby Power-down Wake-up Pin Select 1375 * | | |0000 = GPB.0 wake-up function Enabled. 1376 * | | |0001 = GPB.1 wake-up function Enabled. 1377 * | | |0010 = GPB.2 wake-up function Enabled. 1378 * | | |0011 = GPB.3 wake-up function Enabled. 1379 * | | |0100 = GPB.4 wake-up function Enabled. 1380 * | | |0101 = GPB.5 wake-up function Enabled. 1381 * | | |0110 = GPB.6 wake-up function Enabled. 1382 * | | |0111 = GPB.7 wake-up function Enabled. 1383 * | | |1000 = GPB.8 wake-up function Enabled. 1384 * | | |1001 = GPB.9 wake-up function Enabled. 1385 * | | |1010 = GPB.10 wake-up function Enabled. 1386 * | | |1011 = GPB.11 wake-up function Enabled. 1387 * | | |1100 = GPB.12 wake-up function Enabled. 1388 * | | |1101 = GPB.13 wake-up function Enabled. 1389 * | | |1110 = GPB.14 wake-up function Enabled. 1390 * | | |1111 = GPB.15 wake-up function Enabled. 1391 * |[8] |DBEN |GPB Input Signal De-bounce Enable Bit 1392 * | | |The DBEN bit is used to enable the de-bounce function for each corresponding I/O. 1393 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up. 1394 * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator. (LIRC) 1395 * | | |0 = Standby power-down wake-up pin De-bounce function Disabled. 1396 * | | |1 = Standby power-down wake-up pin De-bounce function Enabled. 1397 * | | |The de-bounce function is valid only for edge triggered. 1398 * @var CLK_T::PCSWKCTL 1399 * Offset: 0xA8 GPC Standby Power-down Wake-up Control Register 1400 * --------------------------------------------------------------------------------------------------- 1401 * |Bits |Field |Descriptions 1402 * | :----: | :----: | :---- | 1403 * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit 1404 * | | |0 = GPC group pin wake-up function Disabled. 1405 * | | |1 = GPC group pin wake-up function Enabled. 1406 * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit 1407 * | | |0 = GPC group pin rising edge wake-up function Disabled. 1408 * | | |1 = GPC group pin rising edge wake-up function Enabled. 1409 * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit 1410 * | | |0 = GPC group pin falling edge wake-up function Disabled. 1411 * | | |1 = GPC group pin falling edge wake-up function Enabled. 1412 * |[7:4] |WKPSEL |GPC Standby Power-down Wake-up Pin Select 1413 * | | |0000 = GPC.0 wake-up function Enabled. 1414 * | | |0001 = GPC.1 wake-up function Enabled. 1415 * | | |0010 = GPC.2 wake-up function Enabled. 1416 * | | |0011 = GPC.3 wake-up function Enabled. 1417 * | | |0100 = GPC.4 wake-up function Enabled. 1418 * | | |0101 = GPC.5 wake-up function Enabled. 1419 * | | |0110 = GPC.6 wake-up function Enabled. 1420 * | | |0111 = GPC.7 wake-up function Enabled. 1421 * | | |1000 = GPC.8 wake-up function Enabled. 1422 * | | |1001 = GPC.9 wake-up function Enabled. 1423 * | | |1010 = GPC.10 wake-up function Enabled. 1424 * | | |1011 = GPC.11 wake-up function Enabled. 1425 * | | |1100 = GPC.12 wake-up function Enabled. 1426 * | | |1101 = GPC.13 wake-up function Enabled. 1427 * | | |1110 = GPC.14 wake-up function Enabled. 1428 * | | |1111 = GPC.15 wake-up function Enabled. 1429 * |[8] |DBEN |GPC Input Signal De-bounce Enable Bit 1430 * | | |The DBEN bit is used to enable the de-bounce function for each corresponding I/O. 1431 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up. 1432 * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC). 1433 * | | |0 = Standby power-down wake-up pin De-bounce function Disabled. 1434 * | | |1 = Standby power-down wake-up pin De-bounce function Enabled. 1435 * | | |Note: The de-bounce function is valid only for edge triggered. 1436 * @var CLK_T::PDSWKCTL 1437 * Offset: 0xAC GPD Standby Power-down Wake-up Control Register 1438 * --------------------------------------------------------------------------------------------------- 1439 * |Bits |Field |Descriptions 1440 * | :----: | :----: | :---- | 1441 * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit 1442 * | | |0 = GPD group pin wake-up function Disabled. 1443 * | | |1 = GPD group pin wake-up function Enabled. 1444 * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit 1445 * | | |0 = GPD group pin rising edge wake-up function Disabled. 1446 * | | |1 = GPD group pin rising edge wake-up function Enabled. 1447 * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit 1448 * | | |0 = GPD group pin falling edge wake-up function Disabled. 1449 * | | |1 = GPD group pin falling edge wake-up function Enabled. 1450 * |[7:4] |WKPSEL |GPD Standby Power-down Wake-up Pin Select 1451 * | | |0000 = GPD.0 wake-up function Enabled. 1452 * | | |0001 = GPD.1 wake-up function Enabled. 1453 * | | |0010 = GPD.2 wake-up function Enabled. 1454 * | | |0011 = GPD.3 wake-up function Enabled. 1455 * | | |0100 = GPD.4 wake-up function Enabled. 1456 * | | |0101 = GPD.5 wake-up function Enabled. 1457 * | | |0110 = GPD.6 wake-up function Enabled. 1458 * | | |0111 = GPD.7 wake-up function Enabled. 1459 * | | |1000 = GPD.8 wake-up function Enabled. 1460 * | | |1001 = GPD.9 wake-up function Enabled. 1461 * | | |1010 = GPD.10 wake-up function Enabled. 1462 * | | |1011 = GPD.11 wake-up function Enabled. 1463 * | | |1100 = GPD.12 wake-up function Enabled. 1464 * | | |1101 = GPD.13 wake-up function Enabled. 1465 * | | |1110 = GPD.14 wake-up function Enabled. 1466 * | | |1111 = GPD.15 wake-up function Enabled. 1467 * |[8] |DBEN |GPD Input Signal De-bounce Enable Bit 1468 * | | |The DBEN bit is used to enable the de-bounce function for each corresponding I/O. 1469 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wake-up. 1470 * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC). 1471 * | | |0 = Standby power-down wake-up pin De-bounce function Disabled. 1472 * | | |1 = Standby power-down wake-up pin De-bounce function Enabled. 1473 * | | |Note: The de-bounce function is valid only for edge triggered. 1474 * @var CLK_T::IOPDCTL 1475 * Offset: 0xB0 GPIO Standby Power-down Control Register 1476 * --------------------------------------------------------------------------------------------------- 1477 * |Bits |Field |Descriptions 1478 * | :----: | :----: | :---- | 1479 * |[0] |IOHR |GPIO Hold Release 1480 * | | |When GPIO enters deep power-down mode or standby power-down mode, all I/O status are hold to keep normal operating status. 1481 * | | |After chip is woken up from deep power-down mode or standby power-down mode, the I/O are still keep hold status until user set this bit to release I/O hold status. 1482 * | | |Note: This bit is auto cleared by hardware. 1483 */ 1484 __IO uint32_t PWRCTL; /*!< [0x0000] System Power-down Control Register */ 1485 __IO uint32_t AHBCLK0; /*!< [0x0004] AHB Devices Clock Enable Control Register 0 */ 1486 __IO uint32_t APBCLK0; /*!< [0x0008] APB Devices Clock Enable Control Register 0 */ 1487 __IO uint32_t APBCLK1; /*!< [0x000c] APB Devices Clock Enable Control Register 1 */ 1488 __IO uint32_t CLKSEL0; /*!< [0x0010] Clock Source Select Control Register 0 */ 1489 __IO uint32_t CLKSEL1; /*!< [0x0014] Clock Source Select Control Register 1 */ 1490 __IO uint32_t CLKSEL2; /*!< [0x0018] Clock Source Select Control Register 2 */ 1491 __IO uint32_t CLKSEL3; /*!< [0x001c] Clock Source Select Control Register 3 */ 1492 __IO uint32_t CLKDIV0; /*!< [0x0020] Clock Divider Number Register 0 */ 1493 __IO uint32_t CLKDIV1; /*!< [0x0024] Clock Divider Number Register 1 */ 1494 __IO uint32_t CLKDIV2; /*!< [0x0028] Clock Divider Number Register 2 */ 1495 __IO uint32_t CLKDIV3; /*!< [0x002c] Clock Divider Number Register 3 */ 1496 __IO uint32_t CLKDIV4; /*!< [0x0030] Clock Divider Number Register 4 */ 1497 __IO uint32_t PCLKDIV; /*!< [0x0034] APB Clock Divider Register */ 1498 __IO uint32_t APBCLK2; /*!< [0x0038] APB Devices Clock Enable Control Register 2 */ 1499 __IO uint32_t CLKDIV5; /*!< [0x003c] Clock Divider Number Register 5 */ 1500 __IO uint32_t PLLCTL; /*!< [0x0040] PLL Control Register */ 1501 __I uint32_t RESERVE0[1]; 1502 __IO uint32_t PLLFNCTL0; /*!< [0x0048] PLLFN Control Register 0 */ 1503 __IO uint32_t PLLFNCTL1; /*!< [0x004c] PLLFN Control Register 1 */ 1504 __I uint32_t STATUS; /*!< [0x0050] Clock Status Monitor Register */ 1505 __I uint32_t RESERVE1[1]; 1506 __IO uint32_t AHBCLK1; /*!< [0x0058] AHB Devices Clock Enable Control Register 1 */ 1507 __IO uint32_t CLKSEL4; /*!< [0x005c] Clock Source Select Control Register 4 */ 1508 __IO uint32_t CLKOCTL; /*!< [0x0060] Clock Output Control Register */ 1509 __I uint32_t RESERVE3[3]; 1510 __IO uint32_t CLKDCTL; /*!< [0x0070] Clock Fail Detector Control Register */ 1511 __IO uint32_t CLKDSTS; /*!< [0x0074] Clock Fail Detector Status Register */ 1512 __IO uint32_t CDUPB; /*!< [0x0078] Clock Frequency Range Detector Upper Boundary Register */ 1513 __IO uint32_t CDLOWB; /*!< [0x007c] Clock Frequency Range Detector Lower Boundary Register */ 1514 __IO uint32_t STOPREQ; /*!< [0x0080] Clock Stop Request Register */ 1515 __I uint32_t STOPACK; /*!< [0x0084] Clock Stop Acknowledge Register */ 1516 __I uint32_t RESERVE4[2]; 1517 __IO uint32_t PMUCTL; /*!< [0x0090] Power Manager Control Register */ 1518 __IO uint32_t PMUSTS; /*!< [0x0094] Power Manager Status Register */ 1519 __I uint32_t RESERVE5[1]; 1520 __IO uint32_t SWKDBCTL; /*!< [0x009c] GPIO Standby Power-down Wake-up De-bounce Control Register */ 1521 __IO uint32_t PASWKCTL; /*!< [0x00a0] GPA Standby Power-down Wake-up Control Register */ 1522 __IO uint32_t PBSWKCTL; /*!< [0x00a4] GPB Standby Power-down Wake-up Control Register */ 1523 __IO uint32_t PCSWKCTL; /*!< [0x00a8] GPC Standby Power-down Wake-up Control Register */ 1524 __IO uint32_t PDSWKCTL; /*!< [0x00ac] GPD Standby Power-down Wake-up Control Register */ 1525 __IO uint32_t IOPDCTL; /*!< [0x00b0] GPIO Standby Power-down Control Register */ 1526 1527 } CLK_T; 1528 1529 /** 1530 @addtogroup CLK_CONST CLK Bit Field Definition 1531 Constant Definitions for CLK Controller 1532 @{ */ 1533 1534 #define CLK_PWRCTL_HXTEN_Pos (0) /*!< CLK_T::PWRCTL: HXTEN Position */ 1535 #define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) /*!< CLK_T::PWRCTL: HXTEN Mask */ 1536 1537 #define CLK_PWRCTL_LXTEN_Pos (1) /*!< CLK_T::PWRCTL: LXTEN Position */ 1538 #define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) /*!< CLK_T::PWRCTL: LXTEN Mask */ 1539 1540 #define CLK_PWRCTL_HIRCEN_Pos (2) /*!< CLK_T::PWRCTL: HIRCEN Position */ 1541 #define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) /*!< CLK_T::PWRCTL: HIRCEN Mask */ 1542 1543 #define CLK_PWRCTL_LIRCEN_Pos (3) /*!< CLK_T::PWRCTL: LIRCEN Position */ 1544 #define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) /*!< CLK_T::PWRCTL: LIRCEN Mask */ 1545 1546 #define CLK_PWRCTL_PDWKDLY_Pos (4) /*!< CLK_T::PWRCTL: PDWKDLY Position */ 1547 #define CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos) /*!< CLK_T::PWRCTL: PDWKDLY Mask */ 1548 1549 #define CLK_PWRCTL_PDWKIEN_Pos (5) /*!< CLK_T::PWRCTL: PDWKIEN Position */ 1550 #define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) /*!< CLK_T::PWRCTL: PDWKIEN Mask */ 1551 1552 #define CLK_PWRCTL_PDWKIF_Pos (6) /*!< CLK_T::PWRCTL: PDWKIF Position */ 1553 #define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos) /*!< CLK_T::PWRCTL: PDWKIF Mask */ 1554 1555 #define CLK_PWRCTL_PDEN_Pos (7) /*!< CLK_T::PWRCTL: PDEN Position */ 1556 #define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) /*!< CLK_T::PWRCTL: PDEN Mask */ 1557 1558 #define CLK_PWRCTL_HXTGAIN_Pos (10) /*!< CLK_T::PWRCTL: HXTGAIN Position */ 1559 #define CLK_PWRCTL_HXTGAIN_Msk (0x3ul << CLK_PWRCTL_HXTGAIN_Pos) /*!< CLK_T::PWRCTL: HXTGAIN Mask */ 1560 1561 #define CLK_PWRCTL_HXTSELTYP_Pos (12) /*!< CLK_T::PWRCTL: HXTSELTYP Position */ 1562 #define CLK_PWRCTL_HXTSELTYP_Msk (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos) /*!< CLK_T::PWRCTL: HXTSELTYP Mask */ 1563 1564 #define CLK_PWRCTL_HIRCSTBS_Pos (16) /*!< CLK_T::PWRCTL: HIRCSTBS Position */ 1565 #define CLK_PWRCTL_HIRCSTBS_Msk (0x3ul << CLK_PWRCTL_HIRCSTBS_Pos) /*!< CLK_T::PWRCTL: HIRCSTBS Mask */ 1566 1567 #define CLK_PWRCTL_HIRC48MEN_Pos (18) /*!< CLK_T::PWRCTL: HIRC48MEN Position */ 1568 #define CLK_PWRCTL_HIRC48MEN_Msk (0x1ul << CLK_PWRCTL_HIRC48MEN_Pos) /*!< CLK_T::PWRCTL: HIRC48MEN Mask */ 1569 1570 #define CLK_PWRCTL_HXTMD_Pos (31) /*!< CLK_T::PWRCTL: HXTMD Position */ 1571 #define CLK_PWRCTL_HXTMD_Msk (0x1ul << CLK_PWRCTL_HXTMD_Pos) /*!< CLK_T::PWRCTL: HXTMD Mask */ 1572 1573 #define CLK_AHBCLK0_PDMA0CKEN_Pos (1) /*!< CLK_T::AHBCLK0: PDMA0CKEN Position */ 1574 #define CLK_AHBCLK0_PDMA0CKEN_Msk (0x1ul << CLK_AHBCLK0_PDMA0CKEN_Pos) /*!< CLK_T::AHBCLK0: PDMA0CKEN Mask */ 1575 1576 #define CLK_AHBCLK0_ISPCKEN_Pos (2) /*!< CLK_T::AHBCLK0: ISPCKEN Position */ 1577 #define CLK_AHBCLK0_ISPCKEN_Msk (0x1ul << CLK_AHBCLK0_ISPCKEN_Pos) /*!< CLK_T::AHBCLK0: ISPCKEN Mask */ 1578 1579 #define CLK_AHBCLK0_EBICKEN_Pos (3) /*!< CLK_T::AHBCLK0: EBICKEN Position */ 1580 #define CLK_AHBCLK0_EBICKEN_Msk (0x1ul << CLK_AHBCLK0_EBICKEN_Pos) /*!< CLK_T::AHBCLK0: EBICKEN Mask */ 1581 1582 #define CLK_AHBCLK0_STCKEN_Pos (4) /*!< CLK_T::AHBCLK0: STCKEN Position */ 1583 #define CLK_AHBCLK0_STCKEN_Msk (0x1ul << CLK_AHBCLK0_STCKEN_Pos) /*!< CLK_T::AHBCLK0: STCKEN Mask */ 1584 1585 #define CLK_AHBCLK0_EMAC0CKEN_Pos (5) /*!< CLK_T::AHBCLK0: EMAC0CKEN Position */ 1586 #define CLK_AHBCLK0_EMAC0CKEN_Msk (0x1ul << CLK_AHBCLK0_EMAC0CKEN_Pos) /*!< CLK_T::AHBCLK0: EMAC0CKEN Mask */ 1587 1588 #define CLK_AHBCLK0_SDH0CKEN_Pos (6) /*!< CLK_T::AHBCLK0: SDH0CKEN Position */ 1589 #define CLK_AHBCLK0_SDH0CKEN_Msk (0x1ul << CLK_AHBCLK0_SDH0CKEN_Pos) /*!< CLK_T::AHBCLK0: SDH0CKEN Mask */ 1590 1591 #define CLK_AHBCLK0_CRCCKEN_Pos (7) /*!< CLK_T::AHBCLK0: CRCCKEN Position */ 1592 #define CLK_AHBCLK0_CRCCKEN_Msk (0x1ul << CLK_AHBCLK0_CRCCKEN_Pos) /*!< CLK_T::AHBCLK0: CRCCKEN Mask */ 1593 1594 #define CLK_AHBCLK0_CCAPCKEN_Pos (8) /*!< CLK_T::AHBCLK0: CCAPCKEN Position */ 1595 #define CLK_AHBCLK0_CCAPCKEN_Msk (0x1ul << CLK_AHBCLK0_CCAPCKEN_Pos) /*!< CLK_T::AHBCLK0: CCAPCKEN Mask */ 1596 1597 #define CLK_AHBCLK0_SENCKEN_Pos (9) /*!< CLK_T::AHBCLK0: SENCKEN Position */ 1598 #define CLK_AHBCLK0_SENCKEN_Msk (0x1ul << CLK_AHBCLK0_SENCKEN_Pos) /*!< CLK_T::AHBCLK0: SENCKEN Mask */ 1599 1600 #define CLK_AHBCLK0_HSUSBDCKEN_Pos (10) /*!< CLK_T::AHBCLK0: HSUSBDCKEN Position */ 1601 #define CLK_AHBCLK0_HSUSBDCKEN_Msk (0x1ul << CLK_AHBCLK0_HSUSBDCKEN_Pos) /*!< CLK_T::AHBCLK0: HSUSBDCKEN Mask */ 1602 1603 #define CLK_AHBCLK0_HBICKEN_Pos (11) /*!< CLK_T::AHBCLK0: HBICKEN Position */ 1604 #define CLK_AHBCLK0_HBICKEN_Msk (0x1ul << CLK_AHBCLK0_HBICKEN_Pos) /*!< CLK_T::AHBCLK0: HBICKEN Mask */ 1605 1606 #define CLK_AHBCLK0_CRPTCKEN_Pos (12) /*!< CLK_T::AHBCLK0: CRPTCKEN Position */ 1607 #define CLK_AHBCLK0_CRPTCKEN_Msk (0x1ul << CLK_AHBCLK0_CRPTCKEN_Pos) /*!< CLK_T::AHBCLK0: CRPTCKEN Mask */ 1608 1609 #define CLK_AHBCLK0_KSCKEN_Pos (13) /*!< CLK_T::AHBCLK0: KSCKEN Position */ 1610 #define CLK_AHBCLK0_KSCKEN_Msk (0x1ul << CLK_AHBCLK0_KSCKEN_Pos) /*!< CLK_T::AHBCLK0: KSCKEN Mask */ 1611 1612 #define CLK_AHBCLK0_SPIMCKEN_Pos (14) /*!< CLK_T::AHBCLK0: SPIMCKEN Position */ 1613 #define CLK_AHBCLK0_SPIMCKEN_Msk (0x1ul << CLK_AHBCLK0_SPIMCKEN_Pos) /*!< CLK_T::AHBCLK0: SPIMCKEN Mask */ 1614 1615 #define CLK_AHBCLK0_FMCIDLE_Pos (15) /*!< CLK_T::AHBCLK0: FMCIDLE Position */ 1616 #define CLK_AHBCLK0_FMCIDLE_Msk (0x1ul << CLK_AHBCLK0_FMCIDLE_Pos) /*!< CLK_T::AHBCLK0: FMCIDLE Mask */ 1617 1618 #define CLK_AHBCLK0_USBHCKEN_Pos (16) /*!< CLK_T::AHBCLK0: USBHCKEN Position */ 1619 #define CLK_AHBCLK0_USBHCKEN_Msk (0x1ul << CLK_AHBCLK0_USBHCKEN_Pos) /*!< CLK_T::AHBCLK0: USBHCKEN Mask */ 1620 1621 #define CLK_AHBCLK0_SDH1CKEN_Pos (17) /*!< CLK_T::AHBCLK0: SDH1CKEN Position */ 1622 #define CLK_AHBCLK0_SDH1CKEN_Msk (0x1ul << CLK_AHBCLK0_SDH1CKEN_Pos) /*!< CLK_T::AHBCLK0: SDH1CKEN Mask */ 1623 1624 #define CLK_AHBCLK0_PDMA1CKEN_Pos (18) /*!< CLK_T::AHBCLK0: PDMA1CKEN Position */ 1625 #define CLK_AHBCLK0_PDMA1CKEN_Msk (0x1ul << CLK_AHBCLK0_PDMA1CKEN_Pos) /*!< CLK_T::AHBCLK0: PDMA1CKEN Mask */ 1626 1627 #define CLK_AHBCLK0_TRACECKEN_Pos (19) /*!< CLK_T::AHBCLK0: TRACECKEN Position */ 1628 #define CLK_AHBCLK0_TRACECKEN_Msk (0x1ul << CLK_AHBCLK0_TRACECKEN_Pos) /*!< CLK_T::AHBCLK0: TRACECKEN Mask */ 1629 1630 #define CLK_AHBCLK0_GPACKEN_Pos (24) /*!< CLK_T::AHBCLK0: GPACKEN Position */ 1631 #define CLK_AHBCLK0_GPACKEN_Msk (0x1ul << CLK_AHBCLK0_GPACKEN_Pos) /*!< CLK_T::AHBCLK0: GPACKEN Mask */ 1632 1633 #define CLK_AHBCLK0_GPBCKEN_Pos (25) /*!< CLK_T::AHBCLK0: GPBCKEN Position */ 1634 #define CLK_AHBCLK0_GPBCKEN_Msk (0x1ul << CLK_AHBCLK0_GPBCKEN_Pos) /*!< CLK_T::AHBCLK0: GPBCKEN Mask */ 1635 1636 #define CLK_AHBCLK0_GPCCKEN_Pos (26) /*!< CLK_T::AHBCLK0: GPCCKEN Position */ 1637 #define CLK_AHBCLK0_GPCCKEN_Msk (0x1ul << CLK_AHBCLK0_GPCCKEN_Pos) /*!< CLK_T::AHBCLK0: GPCCKEN Mask */ 1638 1639 #define CLK_AHBCLK0_GPDCKEN_Pos (27) /*!< CLK_T::AHBCLK0: GPDCKEN Position */ 1640 #define CLK_AHBCLK0_GPDCKEN_Msk (0x1ul << CLK_AHBCLK0_GPDCKEN_Pos) /*!< CLK_T::AHBCLK0: GPDCKEN Mask */ 1641 1642 #define CLK_AHBCLK0_GPECKEN_Pos (28) /*!< CLK_T::AHBCLK0: GPECKEN Position */ 1643 #define CLK_AHBCLK0_GPECKEN_Msk (0x1ul << CLK_AHBCLK0_GPECKEN_Pos) /*!< CLK_T::AHBCLK0: GPECKEN Mask */ 1644 1645 #define CLK_AHBCLK0_GPFCKEN_Pos (29) /*!< CLK_T::AHBCLK0: GPFCKEN Position */ 1646 #define CLK_AHBCLK0_GPFCKEN_Msk (0x1ul << CLK_AHBCLK0_GPFCKEN_Pos) /*!< CLK_T::AHBCLK0: GPFCKEN Mask */ 1647 1648 #define CLK_AHBCLK0_GPGCKEN_Pos (30) /*!< CLK_T::AHBCLK0: GPGCKEN Position */ 1649 #define CLK_AHBCLK0_GPGCKEN_Msk (0x1ul << CLK_AHBCLK0_GPGCKEN_Pos) /*!< CLK_T::AHBCLK0: GPGCKEN Mask */ 1650 1651 #define CLK_AHBCLK0_GPHCKEN_Pos (31) /*!< CLK_T::AHBCLK0: GPHCKEN Position */ 1652 #define CLK_AHBCLK0_GPHCKEN_Msk (0x1ul << CLK_AHBCLK0_GPHCKEN_Pos) /*!< CLK_T::AHBCLK0: GPHCKEN Mask */ 1653 1654 #define CLK_APBCLK0_WDTCKEN_Pos (0) /*!< CLK_T::APBCLK0: WDTCKEN Position */ 1655 #define CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos) /*!< CLK_T::APBCLK0: WDTCKEN Mask */ 1656 1657 #define CLK_APBCLK0_RTCCKEN_Pos (1) /*!< CLK_T::APBCLK0: RTCCKEN Position */ 1658 #define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) /*!< CLK_T::APBCLK0: RTCCKEN Mask */ 1659 1660 #define CLK_APBCLK0_TMR0CKEN_Pos (2) /*!< CLK_T::APBCLK0: TMR0CKEN Position */ 1661 #define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) /*!< CLK_T::APBCLK0: TMR0CKEN Mask */ 1662 1663 #define CLK_APBCLK0_TMR1CKEN_Pos (3) /*!< CLK_T::APBCLK0: TMR1CKEN Position */ 1664 #define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) /*!< CLK_T::APBCLK0: TMR1CKEN Mask */ 1665 1666 #define CLK_APBCLK0_TMR2CKEN_Pos (4) /*!< CLK_T::APBCLK0: TMR2CKEN Position */ 1667 #define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) /*!< CLK_T::APBCLK0: TMR2CKEN Mask */ 1668 1669 #define CLK_APBCLK0_TMR3CKEN_Pos (5) /*!< CLK_T::APBCLK0: TMR3CKEN Position */ 1670 #define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) /*!< CLK_T::APBCLK0: TMR3CKEN Mask */ 1671 1672 #define CLK_APBCLK0_CLKOCKEN_Pos (6) /*!< CLK_T::APBCLK0: CLKOCKEN Position */ 1673 #define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos) /*!< CLK_T::APBCLK0: CLKOCKEN Mask */ 1674 1675 #define CLK_APBCLK0_ACMP01CKEN_Pos (7) /*!< CLK_T::APBCLK0: ACMP01CKEN Position */ 1676 #define CLK_APBCLK0_ACMP01CKEN_Msk (0x1ul << CLK_APBCLK0_ACMP01CKEN_Pos) /*!< CLK_T::APBCLK0: ACMP01CKEN Mask */ 1677 1678 #define CLK_APBCLK0_I2C0CKEN_Pos (8) /*!< CLK_T::APBCLK0: I2C0CKEN Position */ 1679 #define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos) /*!< CLK_T::APBCLK0: I2C0CKEN Mask */ 1680 1681 #define CLK_APBCLK0_I2C1CKEN_Pos (9) /*!< CLK_T::APBCLK0: I2C1CKEN Position */ 1682 #define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos) /*!< CLK_T::APBCLK0: I2C1CKEN Mask */ 1683 1684 #define CLK_APBCLK0_I2C2CKEN_Pos (10) /*!< CLK_T::APBCLK0: I2C2CKEN Position */ 1685 #define CLK_APBCLK0_I2C2CKEN_Msk (0x1ul << CLK_APBCLK0_I2C2CKEN_Pos) /*!< CLK_T::APBCLK0: I2C2CKEN Mask */ 1686 1687 #define CLK_APBCLK0_I2C3CKEN_Pos (11) /*!< CLK_T::APBCLK0: I2C3CKEN Position */ 1688 #define CLK_APBCLK0_I2C3CKEN_Msk (0x1ul << CLK_APBCLK0_I2C3CKEN_Pos) /*!< CLK_T::APBCLK0: I2C3CKEN Mask */ 1689 1690 #define CLK_APBCLK0_QSPI0CKEN_Pos (12) /*!< CLK_T::APBCLK0: QSPI0CKEN Position */ 1691 #define CLK_APBCLK0_QSPI0CKEN_Msk (0x1ul << CLK_APBCLK0_QSPI0CKEN_Pos) /*!< CLK_T::APBCLK0: QSPI0CKEN Mask */ 1692 1693 #define CLK_APBCLK0_SPI0CKEN_Pos (13) /*!< CLK_T::APBCLK0: SPI0CKEN Position */ 1694 #define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos) /*!< CLK_T::APBCLK0: SPI0CKEN Mask */ 1695 1696 #define CLK_APBCLK0_SPI1CKEN_Pos (14) /*!< CLK_T::APBCLK0: SPI1CKEN Position */ 1697 #define CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos) /*!< CLK_T::APBCLK0: SPI1CKEN Mask */ 1698 1699 #define CLK_APBCLK0_SPI2CKEN_Pos (15) /*!< CLK_T::APBCLK0: SPI2CKEN Position */ 1700 #define CLK_APBCLK0_SPI2CKEN_Msk (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos) /*!< CLK_T::APBCLK0: SPI2CKEN Mask */ 1701 1702 #define CLK_APBCLK0_UART0CKEN_Pos (16) /*!< CLK_T::APBCLK0: UART0CKEN Position */ 1703 #define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) /*!< CLK_T::APBCLK0: UART0CKEN Mask */ 1704 1705 #define CLK_APBCLK0_UART1CKEN_Pos (17) /*!< CLK_T::APBCLK0: UART1CKEN Position */ 1706 #define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) /*!< CLK_T::APBCLK0: UART1CKEN Mask */ 1707 1708 #define CLK_APBCLK0_UART2CKEN_Pos (18) /*!< CLK_T::APBCLK0: UART2CKEN Position */ 1709 #define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) /*!< CLK_T::APBCLK0: UART2CKEN Mask */ 1710 1711 #define CLK_APBCLK0_UART3CKEN_Pos (19) /*!< CLK_T::APBCLK0: UART3CKEN Position */ 1712 #define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos) /*!< CLK_T::APBCLK0: UART3CKEN Mask */ 1713 1714 #define CLK_APBCLK0_UART4CKEN_Pos (20) /*!< CLK_T::APBCLK0: UART4CKEN Position */ 1715 #define CLK_APBCLK0_UART4CKEN_Msk (0x1ul << CLK_APBCLK0_UART4CKEN_Pos) /*!< CLK_T::APBCLK0: UART4CKEN Mask */ 1716 1717 #define CLK_APBCLK0_UART5CKEN_Pos (21) /*!< CLK_T::APBCLK0: UART5CKEN Position */ 1718 #define CLK_APBCLK0_UART5CKEN_Msk (0x1ul << CLK_APBCLK0_UART5CKEN_Pos) /*!< CLK_T::APBCLK0: UART5CKEN Mask */ 1719 1720 #define CLK_APBCLK0_UART6CKEN_Pos (22) /*!< CLK_T::APBCLK0: UART6CKEN Position */ 1721 #define CLK_APBCLK0_UART6CKEN_Msk (0x1ul << CLK_APBCLK0_UART6CKEN_Pos) /*!< CLK_T::APBCLK0: UART6CKEN Mask */ 1722 1723 #define CLK_APBCLK0_UART7CKEN_Pos (23) /*!< CLK_T::APBCLK0: UART7CKEN Position */ 1724 #define CLK_APBCLK0_UART7CKEN_Msk (0x1ul << CLK_APBCLK0_UART7CKEN_Pos) /*!< CLK_T::APBCLK0: UART7CKEN Mask */ 1725 1726 #define CLK_APBCLK0_OTGCKEN_Pos (26) /*!< CLK_T::APBCLK0: OTGCKEN Position */ 1727 #define CLK_APBCLK0_OTGCKEN_Msk (0x1ul << CLK_APBCLK0_OTGCKEN_Pos) /*!< CLK_T::APBCLK0: OTGCKEN Mask */ 1728 1729 #define CLK_APBCLK0_USBDCKEN_Pos (27) /*!< CLK_T::APBCLK0: USBDCKEN Position */ 1730 #define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) /*!< CLK_T::APBCLK0: USBDCKEN Mask */ 1731 1732 #define CLK_APBCLK0_EADC0CKEN_Pos (28) /*!< CLK_T::APBCLK0: EADC0CKEN Position */ 1733 #define CLK_APBCLK0_EADC0CKEN_Msk (0x1ul << CLK_APBCLK0_EADC0CKEN_Pos) /*!< CLK_T::APBCLK0: EADC0CKEN Mask */ 1734 1735 #define CLK_APBCLK0_I2S0CKEN_Pos (29) /*!< CLK_T::APBCLK0: I2S0CKEN Position */ 1736 #define CLK_APBCLK0_I2S0CKEN_Msk (0x1ul << CLK_APBCLK0_I2S0CKEN_Pos) /*!< CLK_T::APBCLK0: I2S0CKEN Mask */ 1737 1738 #define CLK_APBCLK0_HSOTGCKEN_Pos (30) /*!< CLK_T::APBCLK0: HSOTGCKEN Position */ 1739 #define CLK_APBCLK0_HSOTGCKEN_Msk (0x1ul << CLK_APBCLK0_HSOTGCKEN_Pos) /*!< CLK_T::APBCLK0: HSOTGCKEN Mask */ 1740 1741 #define CLK_APBCLK1_SC0CKEN_Pos (0) /*!< CLK_T::APBCLK1: SC0CKEN Position */ 1742 #define CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos) /*!< CLK_T::APBCLK1: SC0CKEN Mask */ 1743 1744 #define CLK_APBCLK1_SC1CKEN_Pos (1) /*!< CLK_T::APBCLK1: SC1CKEN Position */ 1745 #define CLK_APBCLK1_SC1CKEN_Msk (0x1ul << CLK_APBCLK1_SC1CKEN_Pos) /*!< CLK_T::APBCLK1: SC1CKEN Mask */ 1746 1747 #define CLK_APBCLK1_SC2CKEN_Pos (2) /*!< CLK_T::APBCLK1: SC2CKEN Position */ 1748 #define CLK_APBCLK1_SC2CKEN_Msk (0x1ul << CLK_APBCLK1_SC2CKEN_Pos) /*!< CLK_T::APBCLK1: SC2CKEN Mask */ 1749 1750 #define CLK_APBCLK1_I2C4CKEN_Pos (3) /*!< CLK_T::APBCLK1: I2C4CKEN Position */ 1751 #define CLK_APBCLK1_I2C4CKEN_Msk (0x1ul << CLK_APBCLK1_I2C4CKEN_Pos) /*!< CLK_T::APBCLK1: I2C4CKEN Mask */ 1752 1753 #define CLK_APBCLK1_QSPI1CKEN_Pos (4) /*!< CLK_T::APBCLK1: QSPI1CKEN Position */ 1754 #define CLK_APBCLK1_QSPI1CKEN_Msk (0x1ul << CLK_APBCLK1_QSPI1CKEN_Pos) /*!< CLK_T::APBCLK1: QSPI1CKEN Mask */ 1755 1756 #define CLK_APBCLK1_SPI3CKEN_Pos (6) /*!< CLK_T::APBCLK1: SPI3CKEN Position */ 1757 #define CLK_APBCLK1_SPI3CKEN_Msk (0x1ul << CLK_APBCLK1_SPI3CKEN_Pos) /*!< CLK_T::APBCLK1: SPI3CKEN Mask */ 1758 1759 #define CLK_APBCLK1_SPI4CKEN_Pos (7) /*!< CLK_T::APBCLK1: SPI4CKEN Position */ 1760 #define CLK_APBCLK1_SPI4CKEN_Msk (0x1ul << CLK_APBCLK1_SPI4CKEN_Pos) /*!< CLK_T::APBCLK1: SPI4CKEN Mask */ 1761 1762 #define CLK_APBCLK1_USCI0CKEN_Pos (8) /*!< CLK_T::APBCLK1: USCI0CKEN Position */ 1763 #define CLK_APBCLK1_USCI0CKEN_Msk (0x1ul << CLK_APBCLK1_USCI0CKEN_Pos) /*!< CLK_T::APBCLK1: USCI0CKEN Mask */ 1764 1765 #define CLK_APBCLK1_PSIOCKEN_Pos (10) /*!< CLK_T::APBCLK1: PSIOCKEN Position */ 1766 #define CLK_APBCLK1_PSIOCKEN_Msk (0x1ul << CLK_APBCLK1_PSIOCKEN_Pos) /*!< CLK_T::APBCLK1: PSIOCKEN Mask */ 1767 1768 #define CLK_APBCLK1_DACCKEN_Pos (12) /*!< CLK_T::APBCLK1: DACCKEN Position */ 1769 #define CLK_APBCLK1_DACCKEN_Msk (0x1ul << CLK_APBCLK1_DACCKEN_Pos) /*!< CLK_T::APBCLK1: DACCKEN Mask */ 1770 1771 #define CLK_APBCLK1_ECAP2CKEN_Pos (13) /*!< CLK_T::APBCLK1: ECAP2CKEN Position */ 1772 #define CLK_APBCLK1_ECAP2CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP2CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP2CKEN Mask */ 1773 1774 #define CLK_APBCLK1_ECAP3CKEN_Pos (14) /*!< CLK_T::APBCLK1: ECAP3CKEN Position */ 1775 #define CLK_APBCLK1_ECAP3CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP3CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP3CKEN Mask */ 1776 1777 #define CLK_APBCLK1_EPWM0CKEN_Pos (16) /*!< CLK_T::APBCLK1: EPWM0CKEN Position */ 1778 #define CLK_APBCLK1_EPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM0CKEN Mask */ 1779 1780 #define CLK_APBCLK1_EPWM1CKEN_Pos (17) /*!< CLK_T::APBCLK1: EPWM1CKEN Position */ 1781 #define CLK_APBCLK1_EPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: EPWM1CKEN Mask */ 1782 1783 #define CLK_APBCLK1_BPWM0CKEN_Pos (18) /*!< CLK_T::APBCLK1: BPWM0CKEN Position */ 1784 #define CLK_APBCLK1_BPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM0CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM0CKEN Mask */ 1785 1786 #define CLK_APBCLK1_BPWM1CKEN_Pos (19) /*!< CLK_T::APBCLK1: BPWM1CKEN Position */ 1787 #define CLK_APBCLK1_BPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM1CKEN_Pos) /*!< CLK_T::APBCLK1: BPWM1CKEN Mask */ 1788 1789 #define CLK_APBCLK1_EQEI2CKEN_Pos (20) /*!< CLK_T::APBCLK1: EQEI2CKEN Position */ 1790 #define CLK_APBCLK1_EQEI2CKEN_Msk (0x1ul << CLK_APBCLK1_EQEI2CKEN_Pos) /*!< CLK_T::APBCLK1: EQEI2CKEN Mask */ 1791 1792 #define CLK_APBCLK1_EQEI3CKEN_Pos (21) /*!< CLK_T::APBCLK1: EQEI3CKEN Position */ 1793 #define CLK_APBCLK1_EQEI3CKEN_Msk (0x1ul << CLK_APBCLK1_EQEI3CKEN_Pos) /*!< CLK_T::APBCLK1: EQEI3CKEN Mask */ 1794 1795 #define CLK_APBCLK1_EQEI0CKEN_Pos (22) /*!< CLK_T::APBCLK1: EQEI0CKEN Position */ 1796 #define CLK_APBCLK1_EQEI0CKEN_Msk (0x1ul << CLK_APBCLK1_EQEI0CKEN_Pos) /*!< CLK_T::APBCLK1: EQEI0CKEN Mask */ 1797 1798 #define CLK_APBCLK1_EQEI1CKEN_Pos (23) /*!< CLK_T::APBCLK1: EQEI1CKEN Position */ 1799 #define CLK_APBCLK1_EQEI1CKEN_Msk (0x1ul << CLK_APBCLK1_EQEI1CKEN_Pos) /*!< CLK_T::APBCLK1: EQEI1CKEN Mask */ 1800 1801 #define CLK_APBCLK1_TRNGCKEN_Pos (25) /*!< CLK_T::APBCLK1: TRNGCKEN Position */ 1802 #define CLK_APBCLK1_TRNGCKEN_Msk (0x1ul << CLK_APBCLK1_TRNGCKEN_Pos) /*!< CLK_T::APBCLK1: TRNGCKEN Mask */ 1803 1804 #define CLK_APBCLK1_ECAP0CKEN_Pos (26) /*!< CLK_T::APBCLK1: ECAP0CKEN Position */ 1805 #define CLK_APBCLK1_ECAP0CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP0CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP0CKEN Mask */ 1806 1807 #define CLK_APBCLK1_ECAP1CKEN_Pos (27) /*!< CLK_T::APBCLK1: ECAP1CKEN Position */ 1808 #define CLK_APBCLK1_ECAP1CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP1CKEN_Pos) /*!< CLK_T::APBCLK1: ECAP1CKEN Mask */ 1809 1810 #define CLK_APBCLK1_I2S1CKEN_Pos (29) /*!< CLK_T::APBCLK1: I2S1CKEN Position */ 1811 #define CLK_APBCLK1_I2S1CKEN_Msk (0x1ul << CLK_APBCLK1_I2S1CKEN_Pos) /*!< CLK_T::APBCLK1: I2S1CKEN Mask */ 1812 1813 #define CLK_APBCLK1_EADC1CKEN_Pos (31) /*!< CLK_T::APBCLK1: EADC1CKEN Position */ 1814 #define CLK_APBCLK1_EADC1CKEN_Msk (0x1ul << CLK_APBCLK1_EADC1CKEN_Pos) /*!< CLK_T::APBCLK1: EADC1CKEN Mask */ 1815 1816 #define CLK_CLKSEL0_HCLKSEL_Pos (0) /*!< CLK_T::CLKSEL0: HCLKSEL Position */ 1817 #define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) /*!< CLK_T::CLKSEL0: HCLKSEL Mask */ 1818 1819 #define CLK_CLKSEL0_STCLKSEL_Pos (3) /*!< CLK_T::CLKSEL0: STCLKSEL Position */ 1820 #define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos) /*!< CLK_T::CLKSEL0: STCLKSEL Mask */ 1821 1822 #define CLK_CLKSEL0_USBSEL_Pos (8) /*!< CLK_T::CLKSEL0: USBSEL Position */ 1823 #define CLK_CLKSEL0_USBSEL_Msk (0x1ul << CLK_CLKSEL0_USBSEL_Pos) /*!< CLK_T::CLKSEL0: USBSEL Mask */ 1824 1825 #define CLK_CLKSEL0_EADC0SEL_Pos (10) /*!< CLK_T::CLKSEL0: EADC0SEL Position */ 1826 #define CLK_CLKSEL0_EADC0SEL_Msk (0x3ul << CLK_CLKSEL0_EADC0SEL_Pos) /*!< CLK_T::CLKSEL0: EADC0SEL Mask */ 1827 1828 #define CLK_CLKSEL0_EADC1SEL_Pos (12) /*!< CLK_T::CLKSEL0: EADC1SEL Position */ 1829 #define CLK_CLKSEL0_EADC1SEL_Msk (0x3ul << CLK_CLKSEL0_EADC1SEL_Pos) /*!< CLK_T::CLKSEL0: EADC1SEL Mask */ 1830 1831 #define CLK_CLKSEL0_EADC2SEL_Pos (14) /*!< CLK_T::CLKSEL0: EADC2SEL Position */ 1832 #define CLK_CLKSEL0_EADC2SEL_Msk (0x3ul << CLK_CLKSEL0_EADC2SEL_Pos) /*!< CLK_T::CLKSEL0: EADC2SEL Mask */ 1833 1834 #define CLK_CLKSEL0_CCAPSEL_Pos (16) /*!< CLK_T::CLKSEL0: CCAPSEL Position */ 1835 #define CLK_CLKSEL0_CCAPSEL_Msk (0x3ul << CLK_CLKSEL0_CCAPSEL_Pos) /*!< CLK_T::CLKSEL0: CCAPSEL Mask */ 1836 1837 #define CLK_CLKSEL0_SDH0SEL_Pos (20) /*!< CLK_T::CLKSEL0: SDH0SEL Position */ 1838 #define CLK_CLKSEL0_SDH0SEL_Msk (0x3ul << CLK_CLKSEL0_SDH0SEL_Pos) /*!< CLK_T::CLKSEL0: SDH0SEL Mask */ 1839 1840 #define CLK_CLKSEL0_SDH1SEL_Pos (22) /*!< CLK_T::CLKSEL0: SDH1SEL Position */ 1841 #define CLK_CLKSEL0_SDH1SEL_Msk (0x3ul << CLK_CLKSEL0_SDH1SEL_Pos) /*!< CLK_T::CLKSEL0: SDH1SEL Mask */ 1842 1843 #define CLK_CLKSEL0_CANFD0SEL_Pos (24) /*!< CLK_T::CLKSEL0: CANFD0SEL Position */ 1844 #define CLK_CLKSEL0_CANFD0SEL_Msk (0x3ul << CLK_CLKSEL0_CANFD0SEL_Pos) /*!< CLK_T::CLKSEL0: CANFD0SEL Mask */ 1845 1846 #define CLK_CLKSEL0_CANFD1SEL_Pos (26) /*!< CLK_T::CLKSEL0: CANFD1SEL Position */ 1847 #define CLK_CLKSEL0_CANFD1SEL_Msk (0x3ul << CLK_CLKSEL0_CANFD1SEL_Pos) /*!< CLK_T::CLKSEL0: CANFD1SEL Mask */ 1848 1849 #define CLK_CLKSEL0_CANFD2SEL_Pos (28) /*!< CLK_T::CLKSEL0: CANFD2SEL Position */ 1850 #define CLK_CLKSEL0_CANFD2SEL_Msk (0x3ul << CLK_CLKSEL0_CANFD2SEL_Pos) /*!< CLK_T::CLKSEL0: CANFD2SEL Mask */ 1851 1852 #define CLK_CLKSEL0_CANFD3SEL_Pos (30) /*!< CLK_T::CLKSEL0: CANFD3SEL Position */ 1853 #define CLK_CLKSEL0_CANFD3SEL_Msk (0x3ul << CLK_CLKSEL0_CANFD3SEL_Pos) /*!< CLK_T::CLKSEL0: CANFD3SEL Mask */ 1854 1855 #define CLK_CLKSEL1_WDTSEL_Pos (0) /*!< CLK_T::CLKSEL1: WDTSEL Position */ 1856 #define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) /*!< CLK_T::CLKSEL1: WDTSEL Mask */ 1857 1858 #define CLK_CLKSEL1_CLKOSEL_Pos (4) /*!< CLK_T::CLKSEL1: CLKOSEL Position */ 1859 #define CLK_CLKSEL1_CLKOSEL_Msk (0x7ul << CLK_CLKSEL1_CLKOSEL_Pos) /*!< CLK_T::CLKSEL1: CLKOSEL Mask */ 1860 1861 #define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK_T::CLKSEL1: TMR0SEL Position */ 1862 #define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK_T::CLKSEL1: TMR0SEL Mask */ 1863 1864 #define CLK_CLKSEL1_TMR1SEL_Pos (12) /*!< CLK_T::CLKSEL1: TMR1SEL Position */ 1865 #define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) /*!< CLK_T::CLKSEL1: TMR1SEL Mask */ 1866 1867 #define CLK_CLKSEL1_TMR2SEL_Pos (16) /*!< CLK_T::CLKSEL1: TMR2SEL Position */ 1868 #define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) /*!< CLK_T::CLKSEL1: TMR2SEL Mask */ 1869 1870 #define CLK_CLKSEL1_TMR3SEL_Pos (20) /*!< CLK_T::CLKSEL1: TMR3SEL Position */ 1871 #define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) /*!< CLK_T::CLKSEL1: TMR3SEL Mask */ 1872 1873 #define CLK_CLKSEL1_UART0SEL_Pos (24) /*!< CLK_T::CLKSEL1: UART0SEL Position */ 1874 #define CLK_CLKSEL1_UART0SEL_Msk (0x3ul << CLK_CLKSEL1_UART0SEL_Pos) /*!< CLK_T::CLKSEL1: UART0SEL Mask */ 1875 1876 #define CLK_CLKSEL1_UART1SEL_Pos (26) /*!< CLK_T::CLKSEL1: UART1SEL Position */ 1877 #define CLK_CLKSEL1_UART1SEL_Msk (0x3ul << CLK_CLKSEL1_UART1SEL_Pos) /*!< CLK_T::CLKSEL1: UART1SEL Mask */ 1878 1879 #define CLK_CLKSEL1_WWDTSEL_Pos (30) /*!< CLK_T::CLKSEL1: WWDTSEL Position */ 1880 #define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) /*!< CLK_T::CLKSEL1: WWDTSEL Mask */ 1881 1882 #define CLK_CLKSEL2_EPWM0SEL_Pos (0) /*!< CLK_T::CLKSEL2: EPWM0SEL Position */ 1883 #define CLK_CLKSEL2_EPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM0SEL Mask */ 1884 1885 #define CLK_CLKSEL2_EPWM1SEL_Pos (1) /*!< CLK_T::CLKSEL2: EPWM1SEL Position */ 1886 #define CLK_CLKSEL2_EPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: EPWM1SEL Mask */ 1887 1888 #define CLK_CLKSEL2_QSPI0SEL_Pos (2) /*!< CLK_T::CLKSEL2: QSPI0SEL Position */ 1889 #define CLK_CLKSEL2_QSPI0SEL_Msk (0x3ul << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< CLK_T::CLKSEL2: QSPI0SEL Mask */ 1890 1891 #define CLK_CLKSEL2_SPI0SEL_Pos (4) /*!< CLK_T::CLKSEL2: SPI0SEL Position */ 1892 #define CLK_CLKSEL2_SPI0SEL_Msk (0x7ul << CLK_CLKSEL2_SPI0SEL_Pos) /*!< CLK_T::CLKSEL2: SPI0SEL Mask */ 1893 1894 #define CLK_CLKSEL2_BPWM0SEL_Pos (8) /*!< CLK_T::CLKSEL2: BPWM0SEL Position */ 1895 #define CLK_CLKSEL2_BPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM0SEL Mask */ 1896 1897 #define CLK_CLKSEL2_BPWM1SEL_Pos (9) /*!< CLK_T::CLKSEL2: BPWM1SEL Position */ 1898 #define CLK_CLKSEL2_BPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< CLK_T::CLKSEL2: BPWM1SEL Mask */ 1899 1900 #define CLK_CLKSEL2_QSPI1SEL_Pos (10) /*!< CLK_T::CLKSEL2: QSPI1SEL Position */ 1901 #define CLK_CLKSEL2_QSPI1SEL_Msk (0x3ul << CLK_CLKSEL2_QSPI1SEL_Pos) /*!< CLK_T::CLKSEL2: QSPI1SEL Mask */ 1902 1903 #define CLK_CLKSEL2_SPI1SEL_Pos (12) /*!< CLK_T::CLKSEL2: SPI1SEL Position */ 1904 #define CLK_CLKSEL2_SPI1SEL_Msk (0x7ul << CLK_CLKSEL2_SPI1SEL_Pos) /*!< CLK_T::CLKSEL2: SPI1SEL Mask */ 1905 1906 #define CLK_CLKSEL2_I2S1SEL_Pos (16) /*!< CLK_T::CLKSEL2: I2S1SEL Position */ 1907 #define CLK_CLKSEL2_I2S1SEL_Msk (0x7ul << CLK_CLKSEL2_I2S1SEL_Pos) /*!< CLK_T::CLKSEL2: I2S1SEL Mask */ 1908 1909 #define CLK_CLKSEL2_UART8SEL_Pos (20) /*!< CLK_T::CLKSEL2: UART8SEL Position */ 1910 #define CLK_CLKSEL2_UART8SEL_Msk (0x3ul << CLK_CLKSEL2_UART8SEL_Pos) /*!< CLK_T::CLKSEL2: UART8SEL Mask */ 1911 1912 #define CLK_CLKSEL2_UART9SEL_Pos (22) /*!< CLK_T::CLKSEL2: UART9SEL Position */ 1913 #define CLK_CLKSEL2_UART9SEL_Msk (0x3ul << CLK_CLKSEL2_UART9SEL_Pos) /*!< CLK_T::CLKSEL2: UART9SEL Mask */ 1914 1915 #define CLK_CLKSEL2_TRNGSEL_Pos (27) /*!< CLK_T::CLKSEL2: TRNGSEL Position */ 1916 #define CLK_CLKSEL2_TRNGSEL_Msk (0x1ul << CLK_CLKSEL2_TRNGSEL_Pos) /*!< CLK_T::CLKSEL2: TRNGSEL Mask */ 1917 1918 #define CLK_CLKSEL2_PSIOSEL_Pos (28) /*!< CLK_T::CLKSEL2: PSIOSEL Position */ 1919 #define CLK_CLKSEL2_PSIOSEL_Msk (0x7ul << CLK_CLKSEL2_PSIOSEL_Pos) /*!< CLK_T::CLKSEL2: PSIOSEL Mask */ 1920 1921 #define CLK_CLKSEL3_SC0SEL_Pos (0) /*!< CLK_T::CLKSEL3: SC0SEL Position */ 1922 #define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos) /*!< CLK_T::CLKSEL3: SC0SEL Mask */ 1923 1924 #define CLK_CLKSEL3_SC1SEL_Pos (2) /*!< CLK_T::CLKSEL3: SC1SEL Position */ 1925 #define CLK_CLKSEL3_SC1SEL_Msk (0x3ul << CLK_CLKSEL3_SC1SEL_Pos) /*!< CLK_T::CLKSEL3: SC1SEL Mask */ 1926 1927 #define CLK_CLKSEL3_SC2SEL_Pos (4) /*!< CLK_T::CLKSEL3: SC2SEL Position */ 1928 #define CLK_CLKSEL3_SC2SEL_Msk (0x3ul << CLK_CLKSEL3_SC2SEL_Pos) /*!< CLK_T::CLKSEL3: SC2SEL Mask */ 1929 1930 #define CLK_CLKSEL3_KPISEL_Pos (6) /*!< CLK_T::CLKSEL3: KPISEL Position */ 1931 #define CLK_CLKSEL3_KPISEL_Msk (0x3ul << CLK_CLKSEL3_KPISEL_Pos) /*!< CLK_T::CLKSEL3: KPISEL Mask */ 1932 1933 #define CLK_CLKSEL3_SPI2SEL_Pos (9) /*!< CLK_T::CLKSEL3: SPI2SEL Position */ 1934 #define CLK_CLKSEL3_SPI2SEL_Msk (0x7ul << CLK_CLKSEL3_SPI2SEL_Pos) /*!< CLK_T::CLKSEL3: SPI2SEL Mask */ 1935 1936 #define CLK_CLKSEL3_SPI3SEL_Pos (12) /*!< CLK_T::CLKSEL3: SPI3SEL Position */ 1937 #define CLK_CLKSEL3_SPI3SEL_Msk (0x7ul << CLK_CLKSEL3_SPI3SEL_Pos) /*!< CLK_T::CLKSEL3: SPI3SEL Mask */ 1938 1939 #define CLK_CLKSEL3_I2S0SEL_Pos (16) /*!< CLK_T::CLKSEL3: I2S0SEL Position */ 1940 #define CLK_CLKSEL3_I2S0SEL_Msk (0x7ul << CLK_CLKSEL3_I2S0SEL_Pos) /*!< CLK_T::CLKSEL3: I2S0SEL Mask */ 1941 1942 #define CLK_CLKSEL3_UART6SEL_Pos (20) /*!< CLK_T::CLKSEL3: UART6SEL Position */ 1943 #define CLK_CLKSEL3_UART6SEL_Msk (0x3ul << CLK_CLKSEL3_UART6SEL_Pos) /*!< CLK_T::CLKSEL3: UART6SEL Mask */ 1944 1945 #define CLK_CLKSEL3_UART7SEL_Pos (22) /*!< CLK_T::CLKSEL3: UART7SEL Position */ 1946 #define CLK_CLKSEL3_UART7SEL_Msk (0x3ul << CLK_CLKSEL3_UART7SEL_Pos) /*!< CLK_T::CLKSEL3: UART7SEL Mask */ 1947 1948 #define CLK_CLKSEL3_UART2SEL_Pos (24) /*!< CLK_T::CLKSEL3: UART2SEL Position */ 1949 #define CLK_CLKSEL3_UART2SEL_Msk (0x3ul << CLK_CLKSEL3_UART2SEL_Pos) /*!< CLK_T::CLKSEL3: UART2SEL Mask */ 1950 1951 #define CLK_CLKSEL3_UART3SEL_Pos (26) /*!< CLK_T::CLKSEL3: UART3SEL Position */ 1952 #define CLK_CLKSEL3_UART3SEL_Msk (0x3ul << CLK_CLKSEL3_UART3SEL_Pos) /*!< CLK_T::CLKSEL3: UART3SEL Mask */ 1953 1954 #define CLK_CLKSEL3_UART4SEL_Pos (28) /*!< CLK_T::CLKSEL3: UART4SEL Position */ 1955 #define CLK_CLKSEL3_UART4SEL_Msk (0x3ul << CLK_CLKSEL3_UART4SEL_Pos) /*!< CLK_T::CLKSEL3: UART4SEL Mask */ 1956 1957 #define CLK_CLKSEL3_UART5SEL_Pos (30) /*!< CLK_T::CLKSEL3: UART5SEL Position */ 1958 #define CLK_CLKSEL3_UART5SEL_Msk (0x3ul << CLK_CLKSEL3_UART5SEL_Pos) /*!< CLK_T::CLKSEL3: UART5SEL Mask */ 1959 1960 #define CLK_CLKDIV0_HCLKDIV_Pos (0) /*!< CLK_T::CLKDIV0: HCLKDIV Position */ 1961 #define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLK_T::CLKDIV0: HCLKDIV Mask */ 1962 1963 #define CLK_CLKDIV0_USBDIV_Pos (4) /*!< CLK_T::CLKDIV0: USBDIV Position */ 1964 #define CLK_CLKDIV0_USBDIV_Msk (0xful << CLK_CLKDIV0_USBDIV_Pos) /*!< CLK_T::CLKDIV0: USBDIV Mask */ 1965 1966 #define CLK_CLKDIV0_UART0DIV_Pos (8) /*!< CLK_T::CLKDIV0: UART0DIV Position */ 1967 #define CLK_CLKDIV0_UART0DIV_Msk (0xful << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLK_T::CLKDIV0: UART0DIV Mask */ 1968 1969 #define CLK_CLKDIV0_UART1DIV_Pos (12) /*!< CLK_T::CLKDIV0: UART1DIV Position */ 1970 #define CLK_CLKDIV0_UART1DIV_Msk (0xful << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLK_T::CLKDIV0: UART1DIV Mask */ 1971 1972 #define CLK_CLKDIV0_EADC0DIV_Pos (16) /*!< CLK_T::CLKDIV0: EADC0DIV Position */ 1973 #define CLK_CLKDIV0_EADC0DIV_Msk (0xfful << CLK_CLKDIV0_EADC0DIV_Pos) /*!< CLK_T::CLKDIV0: EADC0DIV Mask */ 1974 1975 #define CLK_CLKDIV0_SDH0DIV_Pos (24) /*!< CLK_T::CLKDIV0: SDH0DIV Position */ 1976 #define CLK_CLKDIV0_SDH0DIV_Msk (0xfful << CLK_CLKDIV0_SDH0DIV_Pos) /*!< CLK_T::CLKDIV0: SDH0DIV Mask */ 1977 1978 #define CLK_CLKDIV1_SC0DIV_Pos (0) /*!< CLK_T::CLKDIV1: SC0DIV Position */ 1979 #define CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLK_T::CLKDIV1: SC0DIV Mask */ 1980 1981 #define CLK_CLKDIV1_SC1DIV_Pos (8) /*!< CLK_T::CLKDIV1: SC1DIV Position */ 1982 #define CLK_CLKDIV1_SC1DIV_Msk (0xfful << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLK_T::CLKDIV1: SC1DIV Mask */ 1983 1984 #define CLK_CLKDIV1_SC2DIV_Pos (16) /*!< CLK_T::CLKDIV1: SC2DIV Position */ 1985 #define CLK_CLKDIV1_SC2DIV_Msk (0xfful << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLK_T::CLKDIV1: SC2DIV Mask */ 1986 1987 #define CLK_CLKDIV1_PSIODIV_Pos (24) /*!< CLK_T::CLKDIV1: PSIODIV Position */ 1988 #define CLK_CLKDIV1_PSIODIV_Msk (0xfful << CLK_CLKDIV1_PSIODIV_Pos) /*!< CLK_T::CLKDIV1: PSIODIV Mask */ 1989 1990 #define CLK_CLKDIV2_I2S0DIV_Pos (0) /*!< CLK_T::CLKDIV2: I2S0DIV Position */ 1991 #define CLK_CLKDIV2_I2S0DIV_Msk (0xful << CLK_CLKDIV2_I2S0DIV_Pos) /*!< CLK_T::CLKDIV2: I2S0DIV Mask */ 1992 1993 #define CLK_CLKDIV2_I2S1DIV_Pos (4) /*!< CLK_T::CLKDIV2: I2S1DIV Position */ 1994 #define CLK_CLKDIV2_I2S1DIV_Msk (0xful << CLK_CLKDIV2_I2S1DIV_Pos) /*!< CLK_T::CLKDIV2: I2S1DIV Mask */ 1995 1996 #define CLK_CLKDIV2_KPIDIV_Pos (8) /*!< CLK_T::CLKDIV2: KPIDIV Position */ 1997 #define CLK_CLKDIV2_KPIDIV_Msk (0xfful << CLK_CLKDIV2_KPIDIV_Pos) /*!< CLK_T::CLKDIV2: KPIDIV Mask */ 1998 1999 #define CLK_CLKDIV2_EADC1DIV_Pos (24) /*!< CLK_T::CLKDIV2: EADC1DIV Position */ 2000 #define CLK_CLKDIV2_EADC1DIV_Msk (0xfful << CLK_CLKDIV2_EADC1DIV_Pos) /*!< CLK_T::CLKDIV2: EADC1DIV Mask */ 2001 2002 #define CLK_CLKDIV3_VSENSEDIV_Pos (8) /*!< CLK_T::CLKDIV3: VSENSEDIV Position */ 2003 #define CLK_CLKDIV3_VSENSEDIV_Msk (0xfful << CLK_CLKDIV3_VSENSEDIV_Pos) /*!< CLK_T::CLKDIV3: VSENSEDIV Mask */ 2004 2005 #define CLK_CLKDIV3_SDH1DIV_Pos (24) /*!< CLK_T::CLKDIV3: SDH1DIV Position */ 2006 #define CLK_CLKDIV3_SDH1DIV_Msk (0xfful << CLK_CLKDIV3_SDH1DIV_Pos) /*!< CLK_T::CLKDIV3: SDH1DIV Mask */ 2007 2008 #define CLK_CLKDIV4_UART2DIV_Pos (0) /*!< CLK_T::CLKDIV4: UART2DIV Position */ 2009 #define CLK_CLKDIV4_UART2DIV_Msk (0xful << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLK_T::CLKDIV4: UART2DIV Mask */ 2010 2011 #define CLK_CLKDIV4_UART3DIV_Pos (4) /*!< CLK_T::CLKDIV4: UART3DIV Position */ 2012 #define CLK_CLKDIV4_UART3DIV_Msk (0xful << CLK_CLKDIV4_UART3DIV_Pos) /*!< CLK_T::CLKDIV4: UART3DIV Mask */ 2013 2014 #define CLK_CLKDIV4_UART4DIV_Pos (8) /*!< CLK_T::CLKDIV4: UART4DIV Position */ 2015 #define CLK_CLKDIV4_UART4DIV_Msk (0xful << CLK_CLKDIV4_UART4DIV_Pos) /*!< CLK_T::CLKDIV4: UART4DIV Mask */ 2016 2017 #define CLK_CLKDIV4_UART5DIV_Pos (12) /*!< CLK_T::CLKDIV4: UART5DIV Position */ 2018 #define CLK_CLKDIV4_UART5DIV_Msk (0xful << CLK_CLKDIV4_UART5DIV_Pos) /*!< CLK_T::CLKDIV4: UART5DIV Mask */ 2019 2020 #define CLK_CLKDIV4_UART6DIV_Pos (16) /*!< CLK_T::CLKDIV4: UART6DIV Position */ 2021 #define CLK_CLKDIV4_UART6DIV_Msk (0xful << CLK_CLKDIV4_UART6DIV_Pos) /*!< CLK_T::CLKDIV4: UART6DIV Mask */ 2022 2023 #define CLK_CLKDIV4_UART7DIV_Pos (20) /*!< CLK_T::CLKDIV4: UART7DIV Position */ 2024 #define CLK_CLKDIV4_UART7DIV_Msk (0xful << CLK_CLKDIV4_UART7DIV_Pos) /*!< CLK_T::CLKDIV4: UART7DIV Mask */ 2025 2026 #define CLK_PCLKDIV_APB0DIV_Pos (0) /*!< CLK_T::PCLKDIV: APB0DIV Position */ 2027 #define CLK_PCLKDIV_APB0DIV_Msk (0x7ul << CLK_PCLKDIV_APB0DIV_Pos) /*!< CLK_T::PCLKDIV: APB0DIV Mask */ 2028 2029 #define CLK_PCLKDIV_APB1DIV_Pos (4) /*!< CLK_T::PCLKDIV: APB1DIV Position */ 2030 #define CLK_PCLKDIV_APB1DIV_Msk (0x7ul << CLK_PCLKDIV_APB1DIV_Pos) /*!< CLK_T::PCLKDIV: APB1DIV Mask */ 2031 2032 #define CLK_APBCLK2_KPICKEN_Pos (0) /*!< CLK_T::APBCLK2: KPICKEN Position */ 2033 #define CLK_APBCLK2_KPICKEN_Msk (0x1ul << CLK_APBCLK2_KPICKEN_Pos) /*!< CLK_T::APBCLK2: KPICKEN Mask */ 2034 2035 #define CLK_APBCLK2_EADC2CKEN_Pos (6) /*!< CLK_T::APBCLK2: EADC2CKEN Position */ 2036 #define CLK_APBCLK2_EADC2CKEN_Msk (0x1ul << CLK_APBCLK2_EADC2CKEN_Pos) /*!< CLK_T::APBCLK2: EADC2CKEN Mask */ 2037 2038 #define CLK_APBCLK2_ACMP23CKEN_Pos (7) /*!< CLK_T::APBCLK2: ACMP23CKEN Position */ 2039 #define CLK_APBCLK2_ACMP23CKEN_Msk (0x1ul << CLK_APBCLK2_ACMP23CKEN_Pos) /*!< CLK_T::APBCLK2: ACMP23CKEN Mask */ 2040 2041 #define CLK_APBCLK2_SPI5CKEN_Pos (8) /*!< CLK_T::APBCLK2: SPI5CKEN Position */ 2042 #define CLK_APBCLK2_SPI5CKEN_Msk (0x1ul << CLK_APBCLK2_SPI5CKEN_Pos) /*!< CLK_T::APBCLK2: SPI5CKEN Mask */ 2043 2044 #define CLK_APBCLK2_SPI6CKEN_Pos (9) /*!< CLK_T::APBCLK2: SPI6CKEN Position */ 2045 #define CLK_APBCLK2_SPI6CKEN_Msk (0x1ul << CLK_APBCLK2_SPI6CKEN_Pos) /*!< CLK_T::APBCLK2: SPI6CKEN Mask */ 2046 2047 #define CLK_APBCLK2_SPI7CKEN_Pos (10) /*!< CLK_T::APBCLK2: SPI7CKEN Position */ 2048 #define CLK_APBCLK2_SPI7CKEN_Msk (0x1ul << CLK_APBCLK2_SPI7CKEN_Pos) /*!< CLK_T::APBCLK2: SPI7CKEN Mask */ 2049 2050 #define CLK_APBCLK2_SPI8CKEN_Pos (11) /*!< CLK_T::APBCLK2: SPI8CKEN Position */ 2051 #define CLK_APBCLK2_SPI8CKEN_Msk (0x1ul << CLK_APBCLK2_SPI8CKEN_Pos) /*!< CLK_T::APBCLK2: SPI8CKEN Mask */ 2052 2053 #define CLK_APBCLK2_SPI9CKEN_Pos (12) /*!< CLK_T::APBCLK2: SPI9CKEN Position */ 2054 #define CLK_APBCLK2_SPI9CKEN_Msk (0x1ul << CLK_APBCLK2_SPI9CKEN_Pos) /*!< CLK_T::APBCLK2: SPI9CKEN Mask */ 2055 2056 #define CLK_APBCLK2_SPI10CKEN_Pos (13) /*!< CLK_T::APBCLK2: SPI10CKEN Position */ 2057 #define CLK_APBCLK2_SPI10CKEN_Msk (0x1ul << CLK_APBCLK2_SPI10CKEN_Pos) /*!< CLK_T::APBCLK2: SPI10CKEN Mask */ 2058 2059 #define CLK_APBCLK2_UART8CKEN_Pos (16) /*!< CLK_T::APBCLK2: UART8CKEN Position */ 2060 #define CLK_APBCLK2_UART8CKEN_Msk (0x1ul << CLK_APBCLK2_UART8CKEN_Pos) /*!< CLK_T::APBCLK2: UART8CKEN Mask */ 2061 2062 #define CLK_APBCLK2_UART9CKEN_Pos (17) /*!< CLK_T::APBCLK2: UART9CKEN Position */ 2063 #define CLK_APBCLK2_UART9CKEN_Msk (0x1ul << CLK_APBCLK2_UART9CKEN_Pos) /*!< CLK_T::APBCLK2: UART9CKEN Mask */ 2064 2065 #define CLK_CLKDIV5_CANFD0DIV_Pos (0) /*!< CLK_T::CLKDIV5: CANFD0DIV Position */ 2066 #define CLK_CLKDIV5_CANFD0DIV_Msk (0xful << CLK_CLKDIV5_CANFD0DIV_Pos) /*!< CLK_T::CLKDIV5: CANFD0DIV Mask */ 2067 2068 #define CLK_CLKDIV5_CANFD1DIV_Pos (4) /*!< CLK_T::CLKDIV5: CANFD1DIV Position */ 2069 #define CLK_CLKDIV5_CANFD1DIV_Msk (0xful << CLK_CLKDIV5_CANFD1DIV_Pos) /*!< CLK_T::CLKDIV5: CANFD1DIV Mask */ 2070 2071 #define CLK_CLKDIV5_CANFD2DIV_Pos (8) /*!< CLK_T::CLKDIV5: CANFD2DIV Position */ 2072 #define CLK_CLKDIV5_CANFD2DIV_Msk (0xful << CLK_CLKDIV5_CANFD2DIV_Pos) /*!< CLK_T::CLKDIV5: CANFD2DIV Mask */ 2073 2074 #define CLK_CLKDIV5_CANFD3DIV_Pos (12) /*!< CLK_T::CLKDIV5: CANFD3DIV Position */ 2075 #define CLK_CLKDIV5_CANFD3DIV_Msk (0xful << CLK_CLKDIV5_CANFD3DIV_Pos) /*!< CLK_T::CLKDIV5: CANFD3DIV Mask */ 2076 2077 #define CLK_CLKDIV5_UART8DIV_Pos (16) /*!< CLK_T::CLKDIV5: UART8DIV Position */ 2078 #define CLK_CLKDIV5_UART8DIV_Msk (0xful << CLK_CLKDIV5_UART8DIV_Pos) /*!< CLK_T::CLKDIV5: UART8DIV Mask */ 2079 2080 #define CLK_CLKDIV5_UART9DIV_Pos (20) /*!< CLK_T::CLKDIV5: UART9DIV Position */ 2081 #define CLK_CLKDIV5_UART9DIV_Msk (0xful << CLK_CLKDIV5_UART9DIV_Pos) /*!< CLK_T::CLKDIV5: UART9DIV Mask */ 2082 2083 #define CLK_CLKDIV5_EADC2DIV_Pos (24) /*!< CLK_T::CLKDIV5: EADC2DIV Position */ 2084 #define CLK_CLKDIV5_EADC2DIV_Msk (0xfful << CLK_CLKDIV5_EADC2DIV_Pos) /*!< CLK_T::CLKDIV5: EADC2DIV Mask */ 2085 2086 #define CLK_PLLCTL_FBDIV_Pos (0) /*!< CLK_T::PLLCTL: FBDIV Position */ 2087 #define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) /*!< CLK_T::PLLCTL: FBDIV Mask */ 2088 2089 #define CLK_PLLCTL_INDIV_Pos (9) /*!< CLK_T::PLLCTL: INDIV Position */ 2090 #define CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos) /*!< CLK_T::PLLCTL: INDIV Mask */ 2091 2092 #define CLK_PLLCTL_OUTDIV_Pos (14) /*!< CLK_T::PLLCTL: OUTDIV Position */ 2093 #define CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos) /*!< CLK_T::PLLCTL: OUTDIV Mask */ 2094 2095 #define CLK_PLLCTL_PD_Pos (16) /*!< CLK_T::PLLCTL: PD Position */ 2096 #define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) /*!< CLK_T::PLLCTL: PD Mask */ 2097 2098 #define CLK_PLLCTL_BP_Pos (17) /*!< CLK_T::PLLCTL: BP Position */ 2099 #define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos) /*!< CLK_T::PLLCTL: BP Mask */ 2100 2101 #define CLK_PLLCTL_OE_Pos (18) /*!< CLK_T::PLLCTL: OE Position */ 2102 #define CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos) /*!< CLK_T::PLLCTL: OE Mask */ 2103 2104 #define CLK_PLLCTL_PLLSRC_Pos (19) /*!< CLK_T::PLLCTL: PLLSRC Position */ 2105 #define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos) /*!< CLK_T::PLLCTL: PLLSRC Mask */ 2106 2107 #define CLK_PLLCTL_STBSEL_Pos (23) /*!< CLK_T::PLLCTL: STBSEL Position */ 2108 #define CLK_PLLCTL_STBSEL_Msk (0x1ul << CLK_PLLCTL_STBSEL_Pos) /*!< CLK_T::PLLCTL: STBSEL Mask */ 2109 2110 #define CLK_PLLFNCTL0_FBDIV_Pos (0) /*!< CLK_T::PLLFNCTL0: FBDIV Position */ 2111 #define CLK_PLLFNCTL0_FBDIV_Msk (0x1fful << CLK_PLLFNCTL0_FBDIV_Pos) /*!< CLK_T::PLLFNCTL0: FBDIV Mask */ 2112 2113 #define CLK_PLLFNCTL0_INDIV_Pos (9) /*!< CLK_T::PLLFNCTL0: INDIV Position */ 2114 #define CLK_PLLFNCTL0_INDIV_Msk (0x1ful << CLK_PLLFNCTL0_INDIV_Pos) /*!< CLK_T::PLLFNCTL0: INDIV Mask */ 2115 2116 #define CLK_PLLFNCTL0_OUTDIV_Pos (14) /*!< CLK_T::PLLFNCTL0: OUTDIV Position */ 2117 #define CLK_PLLFNCTL0_OUTDIV_Msk (0x3ul << CLK_PLLFNCTL0_OUTDIV_Pos) /*!< CLK_T::PLLFNCTL0: OUTDIV Mask */ 2118 2119 #define CLK_PLLFNCTL0_FRDIV_Pos (16) /*!< CLK_T::PLLFNCTL0: FRDIV Position */ 2120 #define CLK_PLLFNCTL0_FRDIV_Msk (0xffful << CLK_PLLFNCTL0_FRDIV_Pos) /*!< CLK_T::PLLFNCTL0: FRDIV Mask */ 2121 2122 #define CLK_PLLFNCTL1_STBSEL_Pos (27) /*!< CLK_T::PLLFNCTL1: STBSEL Position */ 2123 #define CLK_PLLFNCTL1_STBSEL_Msk (0x1ul << CLK_PLLFNCTL1_STBSEL_Pos) /*!< CLK_T::PLLFNCTL1: STBSEL Mask */ 2124 2125 #define CLK_PLLFNCTL1_PD_Pos (28) /*!< CLK_T::PLLFNCTL1: PD Position */ 2126 #define CLK_PLLFNCTL1_PD_Msk (0x1ul << CLK_PLLFNCTL1_PD_Pos) /*!< CLK_T::PLLFNCTL1: PD Mask */ 2127 2128 #define CLK_PLLFNCTL1_BP_Pos (29) /*!< CLK_T::PLLFNCTL1: BP Position */ 2129 #define CLK_PLLFNCTL1_BP_Msk (0x1ul << CLK_PLLFNCTL1_BP_Pos) /*!< CLK_T::PLLFNCTL1: BP Mask */ 2130 2131 #define CLK_PLLFNCTL1_OE_Pos (30) /*!< CLK_T::PLLFNCTL1: OE Position */ 2132 #define CLK_PLLFNCTL1_OE_Msk (0x1ul << CLK_PLLFNCTL1_OE_Pos) /*!< CLK_T::PLLFNCTL1: OE Mask */ 2133 2134 #define CLK_PLLFNCTL1_PLLSRC_Pos (31) /*!< CLK_T::PLLFNCTL1: PLLSRC Position */ 2135 #define CLK_PLLFNCTL1_PLLSRC_Msk (0x1ul << CLK_PLLFNCTL1_PLLSRC_Pos) /*!< CLK_T::PLLFNCTL1: PLLSRC Mask */ 2136 2137 #define CLK_STATUS_HXTSTB_Pos (0) /*!< CLK_T::STATUS: HXTSTB Position */ 2138 #define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) /*!< CLK_T::STATUS: HXTSTB Mask */ 2139 2140 #define CLK_STATUS_LXTSTB_Pos (1) /*!< CLK_T::STATUS: LXTSTB Position */ 2141 #define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) /*!< CLK_T::STATUS: LXTSTB Mask */ 2142 2143 #define CLK_STATUS_PLLSTB_Pos (2) /*!< CLK_T::STATUS: PLLSTB Position */ 2144 #define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) /*!< CLK_T::STATUS: PLLSTB Mask */ 2145 2146 #define CLK_STATUS_LIRCSTB_Pos (3) /*!< CLK_T::STATUS: LIRCSTB Position */ 2147 #define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) /*!< CLK_T::STATUS: LIRCSTB Mask */ 2148 2149 #define CLK_STATUS_HIRCSTB_Pos (4) /*!< CLK_T::STATUS: HIRCSTB Position */ 2150 #define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) /*!< CLK_T::STATUS: HIRCSTB Mask */ 2151 2152 #define CLK_STATUS_HIRC48MSTB_Pos (6) /*!< CLK_T::STATUS: HIRC48MSTB Position */ 2153 #define CLK_STATUS_HIRC48MSTB_Msk (0x1ul << CLK_STATUS_HIRC48MSTB_Pos) /*!< CLK_T::STATUS: HIRC48MSTB Mask */ 2154 2155 #define CLK_STATUS_CLKSFAIL_Pos (7) /*!< CLK_T::STATUS: CLKSFAIL Position */ 2156 #define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) /*!< CLK_T::STATUS: CLKSFAIL Mask */ 2157 2158 #define CLK_STATUS_PLLFNSTB_Pos (10) /*!< CLK_T::STATUS: PLLFNSTB Position */ 2159 #define CLK_STATUS_PLLFNSTB_Msk (0x1ul << CLK_STATUS_PLLFNSTB_Pos) /*!< CLK_T::STATUS: PLLFNSTB Mask */ 2160 2161 #define CLK_AHBCLK1_CANFD0CKEN_Pos (20) /*!< CLK_T::AHBCLK1: CANFD0CKEN Position */ 2162 #define CLK_AHBCLK1_CANFD0CKEN_Msk (0x1ul << CLK_AHBCLK1_CANFD0CKEN_Pos) /*!< CLK_T::AHBCLK1: CANFD0CKEN Mask */ 2163 2164 #define CLK_AHBCLK1_CANFD1CKEN_Pos (21) /*!< CLK_T::AHBCLK1: CANFD1CKEN Position */ 2165 #define CLK_AHBCLK1_CANFD1CKEN_Msk (0x1ul << CLK_AHBCLK1_CANFD1CKEN_Pos) /*!< CLK_T::AHBCLK1: CANFD1CKEN Mask */ 2166 2167 #define CLK_AHBCLK1_CANFD2CKEN_Pos (22) /*!< CLK_T::AHBCLK1: CANFD2CKEN Position */ 2168 #define CLK_AHBCLK1_CANFD2CKEN_Msk (0x1ul << CLK_AHBCLK1_CANFD2CKEN_Pos) /*!< CLK_T::AHBCLK1: CANFD2CKEN Mask */ 2169 2170 #define CLK_AHBCLK1_CANFD3CKEN_Pos (23) /*!< CLK_T::AHBCLK1: CANFD3CKEN Position */ 2171 #define CLK_AHBCLK1_CANFD3CKEN_Msk (0x1ul << CLK_AHBCLK1_CANFD3CKEN_Pos) /*!< CLK_T::AHBCLK1: CANFD3CKEN Mask */ 2172 2173 #define CLK_AHBCLK1_GPICKEN_Pos (24) /*!< CLK_T::AHBCLK1: GPICKEN Position */ 2174 #define CLK_AHBCLK1_GPICKEN_Msk (0x1ul << CLK_AHBCLK1_GPICKEN_Pos) /*!< CLK_T::AHBCLK1: GPICKEN Mask */ 2175 2176 #define CLK_AHBCLK1_GPJCKEN_Pos (25) /*!< CLK_T::AHBCLK1: GPJCKEN Position */ 2177 #define CLK_AHBCLK1_GPJCKEN_Msk (0x1ul << CLK_AHBCLK1_GPJCKEN_Pos) /*!< CLK_T::AHBCLK1: GPJCKEN Mask */ 2178 2179 #define CLK_AHBCLK1_BMCCKEN_Pos (28) /*!< CLK_T::AHBCLK1: BMCCKEN Position */ 2180 #define CLK_AHBCLK1_BMCCKEN_Msk (0x1ul << CLK_AHBCLK1_BMCCKEN_Pos) /*!< CLK_T::AHBCLK1: BMCCKEN Mask */ 2181 2182 #define CLK_CLKSEL4_SPI4SEL_Pos (0) /*!< CLK_T::CLKSEL4: SPI4SEL Position */ 2183 #define CLK_CLKSEL4_SPI4SEL_Msk (0x7ul << CLK_CLKSEL4_SPI4SEL_Pos) /*!< CLK_T::CLKSEL4: SPI4SEL Mask */ 2184 2185 #define CLK_CLKSEL4_SPI5SEL_Pos (4) /*!< CLK_T::CLKSEL4: SPI5SEL Position */ 2186 #define CLK_CLKSEL4_SPI5SEL_Msk (0x7ul << CLK_CLKSEL4_SPI5SEL_Pos) /*!< CLK_T::CLKSEL4: SPI5SEL Mask */ 2187 2188 #define CLK_CLKSEL4_SPI6SEL_Pos (8) /*!< CLK_T::CLKSEL4: SPI6SEL Position */ 2189 #define CLK_CLKSEL4_SPI6SEL_Msk (0x7ul << CLK_CLKSEL4_SPI6SEL_Pos) /*!< CLK_T::CLKSEL4: SPI6SEL Mask */ 2190 2191 #define CLK_CLKSEL4_SPI7SEL_Pos (12) /*!< CLK_T::CLKSEL4: SPI7SEL Position */ 2192 #define CLK_CLKSEL4_SPI7SEL_Msk (0x7ul << CLK_CLKSEL4_SPI7SEL_Pos) /*!< CLK_T::CLKSEL4: SPI7SEL Mask */ 2193 2194 #define CLK_CLKSEL4_SPI8SEL_Pos (16) /*!< CLK_T::CLKSEL4: SPI8SEL Position */ 2195 #define CLK_CLKSEL4_SPI8SEL_Msk (0x7ul << CLK_CLKSEL4_SPI8SEL_Pos) /*!< CLK_T::CLKSEL4: SPI8SEL Mask */ 2196 2197 #define CLK_CLKSEL4_SPI9SEL_Pos (20) /*!< CLK_T::CLKSEL4: SPI9SEL Position */ 2198 #define CLK_CLKSEL4_SPI9SEL_Msk (0x7ul << CLK_CLKSEL4_SPI9SEL_Pos) /*!< CLK_T::CLKSEL4: SPI9SEL Mask */ 2199 2200 #define CLK_CLKSEL4_SPI10SEL_Pos (24) /*!< CLK_T::CLKSEL4: SPI10SEL Position */ 2201 #define CLK_CLKSEL4_SPI10SEL_Msk (0x7ul << CLK_CLKSEL4_SPI10SEL_Pos) /*!< CLK_T::CLKSEL4: SPI10SEL Mask */ 2202 2203 #define CLK_CLKOCTL_FREQSEL_Pos (0) /*!< CLK_T::CLKOCTL: FREQSEL Position */ 2204 #define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos) /*!< CLK_T::CLKOCTL: FREQSEL Mask */ 2205 2206 #define CLK_CLKOCTL_CLKOEN_Pos (4) /*!< CLK_T::CLKOCTL: CLKOEN Position */ 2207 #define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) /*!< CLK_T::CLKOCTL: CLKOEN Mask */ 2208 2209 #define CLK_CLKOCTL_DIV1EN_Pos (5) /*!< CLK_T::CLKOCTL: DIV1EN Position */ 2210 #define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) /*!< CLK_T::CLKOCTL: DIV1EN Mask */ 2211 2212 #define CLK_CLKOCTL_CLK1HZEN_Pos (6) /*!< CLK_T::CLKOCTL: CLK1HZEN Position */ 2213 #define CLK_CLKOCTL_CLK1HZEN_Msk (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos) /*!< CLK_T::CLKOCTL: CLK1HZEN Mask */ 2214 2215 #define CLK_CLKDCTL_HXTFDEN_Pos (4) /*!< CLK_T::CLKDCTL: HXTFDEN Position */ 2216 #define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFDEN Mask */ 2217 2218 #define CLK_CLKDCTL_HXTFIEN_Pos (5) /*!< CLK_T::CLKDCTL: HXTFIEN Position */ 2219 #define CLK_CLKDCTL_HXTFIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFIEN Mask */ 2220 2221 #define CLK_CLKDCTL_LXTFDEN_Pos (12) /*!< CLK_T::CLKDCTL: LXTFDEN Position */ 2222 #define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos) /*!< CLK_T::CLKDCTL: LXTFDEN Mask */ 2223 2224 #define CLK_CLKDCTL_LXTFIEN_Pos (13) /*!< CLK_T::CLKDCTL: LXTFIEN Position */ 2225 #define CLK_CLKDCTL_LXTFIEN_Msk (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos) /*!< CLK_T::CLKDCTL: LXTFIEN Mask */ 2226 2227 #define CLK_CLKDCTL_HXTFQDEN_Pos (16) /*!< CLK_T::CLKDCTL: HXTFQDEN Position */ 2228 #define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQDEN Mask */ 2229 2230 #define CLK_CLKDCTL_HXTFQIEN_Pos (17) /*!< CLK_T::CLKDCTL: HXTFQIEN Position */ 2231 #define CLK_CLKDCTL_HXTFQIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos) /*!< CLK_T::CLKDCTL: HXTFQIEN Mask */ 2232 2233 #define CLK_CLKDCTL_HXTFQASW_Pos (18) /*!< CLK_T::CLKDCTL: HXTFQASW Position */ 2234 #define CLK_CLKDCTL_HXTFQASW_Msk (0x1ul << CLK_CLKDCTL_HXTFQASW_Pos) /*!< CLK_T::CLKDCTL: HXTFQASW Mask */ 2235 2236 #define CLK_CLKDSTS_HXTFIF_Pos (0) /*!< CLK_T::CLKDSTS: HXTFIF Position */ 2237 #define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos) /*!< CLK_T::CLKDSTS: HXTFIF Mask */ 2238 2239 #define CLK_CLKDSTS_LXTFIF_Pos (1) /*!< CLK_T::CLKDSTS: LXTFIF Position */ 2240 #define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos) /*!< CLK_T::CLKDSTS: LXTFIF Mask */ 2241 2242 #define CLK_CLKDSTS_HXTFQIF_Pos (8) /*!< CLK_T::CLKDSTS: HXTFQIF Position */ 2243 #define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos) /*!< CLK_T::CLKDSTS: HXTFQIF Mask */ 2244 2245 #define CLK_CDUPB_UPERBD_Pos (0) /*!< CLK_T::CDUPB: UPERBD Position */ 2246 #define CLK_CDUPB_UPERBD_Msk (0x3fful << CLK_CDUPB_UPERBD_Pos) /*!< CLK_T::CDUPB: UPERBD Mask */ 2247 2248 #define CLK_CDLOWB_LOWERBD_Pos (0) /*!< CLK_T::CDLOWB: LOWERBD Position */ 2249 #define CLK_CDLOWB_LOWERBD_Msk (0x3fful << CLK_CDLOWB_LOWERBD_Pos) /*!< CLK_T::CDLOWB: LOWERBD Mask */ 2250 2251 #define CLK_STOPREQ_CANFD0STR_Pos (0) /*!< CLK_T::STOPREQ: CANFD0STR Position */ 2252 #define CLK_STOPREQ_CANFD0STR_Msk (0x1ul << CLK_STOPREQ_CANFD0STR_Pos) /*!< CLK_T::STOPREQ: CANFD0STR Mask */ 2253 2254 #define CLK_STOPREQ_CANFD1STR_Pos (1) /*!< CLK_T::STOPREQ: CANFD1STR Position */ 2255 #define CLK_STOPREQ_CANFD1STR_Msk (0x1ul << CLK_STOPREQ_CANFD1STR_Pos) /*!< CLK_T::STOPREQ: CANFD1STR Mask */ 2256 2257 #define CLK_STOPREQ_CANFD2STR_Pos (2) /*!< CLK_T::STOPREQ: CANFD2STR Position */ 2258 #define CLK_STOPREQ_CANFD2STR_Msk (0x1ul << CLK_STOPREQ_CANFD2STR_Pos) /*!< CLK_T::STOPREQ: CANFD2STR Mask */ 2259 2260 #define CLK_STOPREQ_CANFD3STR_Pos (3) /*!< CLK_T::STOPREQ: CANFD3STR Position */ 2261 #define CLK_STOPREQ_CANFD3STR_Msk (0x1ul << CLK_STOPREQ_CANFD3STR_Pos) /*!< CLK_T::STOPREQ: CANFD3STR Mask */ 2262 2263 #define CLK_STOPACK_CANFD0STA_Pos (0) /*!< CLK_T::STOPACK: CANFD0STA Position */ 2264 #define CLK_STOPACK_CANFD0STA_Msk (0x1ul << CLK_STOPACK_CANFD0STA_Pos) /*!< CLK_T::STOPACK: CANFD0STA Mask */ 2265 2266 #define CLK_STOPACK_CANFD1STA_Pos (1) /*!< CLK_T::STOPACK: CANFD1STA Position */ 2267 #define CLK_STOPACK_CANFD1STA_Msk (0x1ul << CLK_STOPACK_CANFD1STA_Pos) /*!< CLK_T::STOPACK: CANFD1STA Mask */ 2268 2269 #define CLK_STOPACK_CANFD2STA_Pos (2) /*!< CLK_T::STOPACK: CANFD2STA Position */ 2270 #define CLK_STOPACK_CANFD2STA_Msk (0x1ul << CLK_STOPACK_CANFD2STA_Pos) /*!< CLK_T::STOPACK: CANFD2STA Mask */ 2271 2272 #define CLK_STOPACK_CANFD3STA_Pos (3) /*!< CLK_T::STOPACK: CANFD3STA Position */ 2273 #define CLK_STOPACK_CANFD3STA_Msk (0x1ul << CLK_STOPACK_CANFD3STA_Pos) /*!< CLK_T::STOPACK: CANFD3STA Mask */ 2274 2275 #define CLK_PMUCTL_PDMSEL_Pos (0) /*!< CLK_T::PMUCTL: PDMSEL Position */ 2276 #define CLK_PMUCTL_PDMSEL_Msk (0x7ul << CLK_PMUCTL_PDMSEL_Pos) /*!< CLK_T::PMUCTL: PDMSEL Mask */ 2277 2278 #define CLK_PMUCTL_DPDHOLDEN_Pos (3) /*!< CLK_T::PMUCTL: DPDHOLDEN Position */ 2279 #define CLK_PMUCTL_DPDHOLDEN_Msk (0x1ul << CLK_PMUCTL_DPDHOLDEN_Pos) /*!< CLK_T::PMUCTL: DPDHOLDEN Mask */ 2280 2281 #define CLK_PMUCTL_SRETSEL_Pos (4) /*!< CLK_T::PMUCTL: SRETSEL Position */ 2282 #define CLK_PMUCTL_SRETSEL_Msk (0x7ul << CLK_PMUCTL_SRETSEL_Pos) /*!< CLK_T::PMUCTL: SRETSEL Mask */ 2283 2284 #define CLK_PMUCTL_WKTMREN_Pos (8) /*!< CLK_T::PMUCTL: WKTMREN Position */ 2285 #define CLK_PMUCTL_WKTMREN_Msk (0x1ul << CLK_PMUCTL_WKTMREN_Pos) /*!< CLK_T::PMUCTL: WKTMREN Mask */ 2286 2287 #define CLK_PMUCTL_WKTMRIS_Pos (9) /*!< CLK_T::PMUCTL: WKTMRIS Position */ 2288 #define CLK_PMUCTL_WKTMRIS_Msk (0xful << CLK_PMUCTL_WKTMRIS_Pos) /*!< CLK_T::PMUCTL: WKTMRIS Mask */ 2289 2290 #define CLK_PMUCTL_WKPINEN0_Pos (16) /*!< CLK_T::PMUCTL: WKPINEN0 Position */ 2291 #define CLK_PMUCTL_WKPINEN0_Msk (0x3ul << CLK_PMUCTL_WKPINEN0_Pos) /*!< CLK_T::PMUCTL: WKPINEN0 Mask */ 2292 2293 #define CLK_PMUCTL_ACMPSPWK_Pos (18) /*!< CLK_T::PMUCTL: ACMPSPWK Position */ 2294 #define CLK_PMUCTL_ACMPSPWK_Msk (0x1ul << CLK_PMUCTL_ACMPSPWK_Pos) /*!< CLK_T::PMUCTL: ACMPSPWK Mask */ 2295 2296 #define CLK_PMUCTL_VBUSWKEN_Pos (22) /*!< CLK_T::PMUCTL: VBUSWKEN Position */ 2297 #define CLK_PMUCTL_VBUSWKEN_Msk (0x1ul << CLK_PMUCTL_VBUSWKEN_Pos) /*!< CLK_T::PMUCTL: VBUSWKEN Mask */ 2298 2299 #define CLK_PMUCTL_RTCWKEN_Pos (23) /*!< CLK_T::PMUCTL: RTCWKEN Position */ 2300 #define CLK_PMUCTL_RTCWKEN_Msk (0x1ul << CLK_PMUCTL_RTCWKEN_Pos) /*!< CLK_T::PMUCTL: RTCWKEN Mask */ 2301 2302 #define CLK_PMUCTL_WKPINEN1_Pos (24) /*!< CLK_T::PMUCTL: WKPINEN1 Position */ 2303 #define CLK_PMUCTL_WKPINEN1_Msk (0x3ul << CLK_PMUCTL_WKPINEN1_Pos) /*!< CLK_T::PMUCTL: WKPINEN1 Mask */ 2304 2305 #define CLK_PMUCTL_WKPINEN2_Pos (26) /*!< CLK_T::PMUCTL: WKPINEN2 Position */ 2306 #define CLK_PMUCTL_WKPINEN2_Msk (0x3ul << CLK_PMUCTL_WKPINEN2_Pos) /*!< CLK_T::PMUCTL: WKPINEN2 Mask */ 2307 2308 #define CLK_PMUCTL_WKPINEN3_Pos (28) /*!< CLK_T::PMUCTL: WKPINEN3 Position */ 2309 #define CLK_PMUCTL_WKPINEN3_Msk (0x3ul << CLK_PMUCTL_WKPINEN3_Pos) /*!< CLK_T::PMUCTL: WKPINEN3 Mask */ 2310 2311 #define CLK_PMUCTL_WKPINEN4_Pos (30) /*!< CLK_T::PMUCTL: WKPINEN4 Position */ 2312 #define CLK_PMUCTL_WKPINEN4_Msk (0x3ul << CLK_PMUCTL_WKPINEN4_Pos) /*!< CLK_T::PMUCTL: WKPINEN4 Mask */ 2313 2314 #define CLK_PMUSTS_PINWK0_Pos (0) /*!< CLK_T::PMUSTS: PINWK0 Position */ 2315 #define CLK_PMUSTS_PINWK0_Msk (0x1ul << CLK_PMUSTS_PINWK0_Pos) /*!< CLK_T::PMUSTS: PINWK0 Mask */ 2316 2317 #define CLK_PMUSTS_TMRWK_Pos (1) /*!< CLK_T::PMUSTS: TMRWK Position */ 2318 #define CLK_PMUSTS_TMRWK_Msk (0x1ul << CLK_PMUSTS_TMRWK_Pos) /*!< CLK_T::PMUSTS: TMRWK Mask */ 2319 2320 #define CLK_PMUSTS_RTCWK_Pos (2) /*!< CLK_T::PMUSTS: RTCWK Position */ 2321 #define CLK_PMUSTS_RTCWK_Msk (0x1ul << CLK_PMUSTS_RTCWK_Pos) /*!< CLK_T::PMUSTS: RTCWK Mask */ 2322 2323 #define CLK_PMUSTS_PINWK1_Pos (3) /*!< CLK_T::PMUSTS: PINWK1 Position */ 2324 #define CLK_PMUSTS_PINWK1_Msk (0x1ul << CLK_PMUSTS_PINWK1_Pos) /*!< CLK_T::PMUSTS: PINWK1 Mask */ 2325 2326 #define CLK_PMUSTS_PINWK2_Pos (4) /*!< CLK_T::PMUSTS: PINWK2 Position */ 2327 #define CLK_PMUSTS_PINWK2_Msk (0x1ul << CLK_PMUSTS_PINWK2_Pos) /*!< CLK_T::PMUSTS: PINWK2 Mask */ 2328 2329 #define CLK_PMUSTS_PINWK3_Pos (5) /*!< CLK_T::PMUSTS: PINWK3 Position */ 2330 #define CLK_PMUSTS_PINWK3_Msk (0x1ul << CLK_PMUSTS_PINWK3_Pos) /*!< CLK_T::PMUSTS: PINWK3 Mask */ 2331 2332 #define CLK_PMUSTS_PINWK4_Pos (6) /*!< CLK_T::PMUSTS: PINWK4 Position */ 2333 #define CLK_PMUSTS_PINWK4_Msk (0x1ul << CLK_PMUSTS_PINWK4_Pos) /*!< CLK_T::PMUSTS: PINWK4 Mask */ 2334 2335 #define CLK_PMUSTS_VBUSWK_Pos (7) /*!< CLK_T::PMUSTS: VBUSWK Position */ 2336 #define CLK_PMUSTS_VBUSWK_Msk (0x1ul << CLK_PMUSTS_VBUSWK_Pos) /*!< CLK_T::PMUSTS: VBUSWK Mask */ 2337 2338 #define CLK_PMUSTS_GPAWK_Pos (8) /*!< CLK_T::PMUSTS: GPAWK Position */ 2339 #define CLK_PMUSTS_GPAWK_Msk (0x1ul << CLK_PMUSTS_GPAWK_Pos) /*!< CLK_T::PMUSTS: GPAWK Mask */ 2340 2341 #define CLK_PMUSTS_GPBWK_Pos (9) /*!< CLK_T::PMUSTS: GPBWK Position */ 2342 #define CLK_PMUSTS_GPBWK_Msk (0x1ul << CLK_PMUSTS_GPBWK_Pos) /*!< CLK_T::PMUSTS: GPBWK Mask */ 2343 2344 #define CLK_PMUSTS_GPCWK_Pos (10) /*!< CLK_T::PMUSTS: GPCWK Position */ 2345 #define CLK_PMUSTS_GPCWK_Msk (0x1ul << CLK_PMUSTS_GPCWK_Pos) /*!< CLK_T::PMUSTS: GPCWK Mask */ 2346 2347 #define CLK_PMUSTS_GPDWK_Pos (11) /*!< CLK_T::PMUSTS: GPDWK Position */ 2348 #define CLK_PMUSTS_GPDWK_Msk (0x1ul << CLK_PMUSTS_GPDWK_Pos) /*!< CLK_T::PMUSTS: GPDWK Mask */ 2349 2350 #define CLK_PMUSTS_LVRWK_Pos (12) /*!< CLK_T::PMUSTS: LVRWK Position */ 2351 #define CLK_PMUSTS_LVRWK_Msk (0x1ul << CLK_PMUSTS_LVRWK_Pos) /*!< CLK_T::PMUSTS: LVRWK Mask */ 2352 2353 #define CLK_PMUSTS_BODWK_Pos (13) /*!< CLK_T::PMUSTS: BODWK Position */ 2354 #define CLK_PMUSTS_BODWK_Msk (0x1ul << CLK_PMUSTS_BODWK_Pos) /*!< CLK_T::PMUSTS: BODWK Mask */ 2355 2356 #define CLK_PMUSTS_RSTWK_Pos (15) /*!< CLK_T::PMUSTS: RSTWK Position */ 2357 #define CLK_PMUSTS_RSTWK_Msk (0x1ul << CLK_PMUSTS_RSTWK_Pos) /*!< CLK_T::PMUSTS: RSTWK Mask */ 2358 2359 #define CLK_PMUSTS_ACMPWK0_Pos (16) /*!< CLK_T::PMUSTS: ACMPWK0 Position */ 2360 #define CLK_PMUSTS_ACMPWK0_Msk (0x1ul << CLK_PMUSTS_ACMPWK0_Pos) /*!< CLK_T::PMUSTS: ACMPWK0 Mask */ 2361 2362 #define CLK_PMUSTS_ACMPWK1_Pos (17) /*!< CLK_T::PMUSTS: ACMPWK1 Position */ 2363 #define CLK_PMUSTS_ACMPWK1_Msk (0x1ul << CLK_PMUSTS_ACMPWK1_Pos) /*!< CLK_T::PMUSTS: ACMPWK1 Mask */ 2364 2365 #define CLK_PMUSTS_ACMPWK2_Pos (18) /*!< CLK_T::PMUSTS: ACMPWK2 Position */ 2366 #define CLK_PMUSTS_ACMPWK2_Msk (0x1ul << CLK_PMUSTS_ACMPWK2_Pos) /*!< CLK_T::PMUSTS: ACMPWK2 Mask */ 2367 2368 #define CLK_PMUSTS_ACMPWK3_Pos (19) /*!< CLK_T::PMUSTS: ACMPWK3 Position */ 2369 #define CLK_PMUSTS_ACMPWK3_Msk (0x1ul << CLK_PMUSTS_ACMPWK3_Pos) /*!< CLK_T::PMUSTS: ACMPWK3 Mask */ 2370 2371 #define CLK_PMUSTS_CLRWK_Pos (31) /*!< CLK_T::PMUSTS: CLRWK Position */ 2372 #define CLK_PMUSTS_CLRWK_Msk (0x1ul << CLK_PMUSTS_CLRWK_Pos) /*!< CLK_T::PMUSTS: CLRWK Mask */ 2373 2374 #define CLK_SWKDBCTL_SWKDBCLKSEL_Pos (0) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Position */ 2375 #define CLK_SWKDBCTL_SWKDBCLKSEL_Msk (0xful << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< CLK_T::SWKDBCTL: SWKDBCLKSEL Mask */ 2376 2377 #define CLK_PASWKCTL_WKEN_Pos (0) /*!< CLK_T::PASWKCTL: WKEN Position */ 2378 #define CLK_PASWKCTL_WKEN_Msk (0x1ul << CLK_PASWKCTL_WKEN_Pos) /*!< CLK_T::PASWKCTL: WKEN Mask */ 2379 2380 #define CLK_PASWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PASWKCTL: PRWKEN Position */ 2381 #define CLK_PASWKCTL_PRWKEN_Msk (0x1ul << CLK_PASWKCTL_PRWKEN_Pos) /*!< CLK_T::PASWKCTL: PRWKEN Mask */ 2382 2383 #define CLK_PASWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PASWKCTL: PFWKEN Position */ 2384 #define CLK_PASWKCTL_PFWKEN_Msk (0x1ul << CLK_PASWKCTL_PFWKEN_Pos) /*!< CLK_T::PASWKCTL: PFWKEN Mask */ 2385 2386 #define CLK_PASWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PASWKCTL: WKPSEL Position */ 2387 #define CLK_PASWKCTL_WKPSEL_Msk (0xful << CLK_PASWKCTL_WKPSEL_Pos) /*!< CLK_T::PASWKCTL: WKPSEL Mask */ 2388 2389 #define CLK_PASWKCTL_DBEN_Pos (8) /*!< CLK_T::PASWKCTL: DBEN Position */ 2390 #define CLK_PASWKCTL_DBEN_Msk (0x1ul << CLK_PASWKCTL_DBEN_Pos) /*!< CLK_T::PASWKCTL: DBEN Mask */ 2391 2392 #define CLK_PBSWKCTL_WKEN_Pos (0) /*!< CLK_T::PBSWKCTL: WKEN Position */ 2393 #define CLK_PBSWKCTL_WKEN_Msk (0x1ul << CLK_PBSWKCTL_WKEN_Pos) /*!< CLK_T::PBSWKCTL: WKEN Mask */ 2394 2395 #define CLK_PBSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PBSWKCTL: PRWKEN Position */ 2396 #define CLK_PBSWKCTL_PRWKEN_Msk (0x1ul << CLK_PBSWKCTL_PRWKEN_Pos) /*!< CLK_T::PBSWKCTL: PRWKEN Mask */ 2397 2398 #define CLK_PBSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PBSWKCTL: PFWKEN Position */ 2399 #define CLK_PBSWKCTL_PFWKEN_Msk (0x1ul << CLK_PBSWKCTL_PFWKEN_Pos) /*!< CLK_T::PBSWKCTL: PFWKEN Mask */ 2400 2401 #define CLK_PBSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PBSWKCTL: WKPSEL Position */ 2402 #define CLK_PBSWKCTL_WKPSEL_Msk (0xful << CLK_PBSWKCTL_WKPSEL_Pos) /*!< CLK_T::PBSWKCTL: WKPSEL Mask */ 2403 2404 #define CLK_PBSWKCTL_DBEN_Pos (8) /*!< CLK_T::PBSWKCTL: DBEN Position */ 2405 #define CLK_PBSWKCTL_DBEN_Msk (0x1ul << CLK_PBSWKCTL_DBEN_Pos) /*!< CLK_T::PBSWKCTL: DBEN Mask */ 2406 2407 #define CLK_PCSWKCTL_WKEN_Pos (0) /*!< CLK_T::PCSWKCTL: WKEN Position */ 2408 #define CLK_PCSWKCTL_WKEN_Msk (0x1ul << CLK_PCSWKCTL_WKEN_Pos) /*!< CLK_T::PCSWKCTL: WKEN Mask */ 2409 2410 #define CLK_PCSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PCSWKCTL: PRWKEN Position */ 2411 #define CLK_PCSWKCTL_PRWKEN_Msk (0x1ul << CLK_PCSWKCTL_PRWKEN_Pos) /*!< CLK_T::PCSWKCTL: PRWKEN Mask */ 2412 2413 #define CLK_PCSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PCSWKCTL: PFWKEN Position */ 2414 #define CLK_PCSWKCTL_PFWKEN_Msk (0x1ul << CLK_PCSWKCTL_PFWKEN_Pos) /*!< CLK_T::PCSWKCTL: PFWKEN Mask */ 2415 2416 #define CLK_PCSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PCSWKCTL: WKPSEL Position */ 2417 #define CLK_PCSWKCTL_WKPSEL_Msk (0xful << CLK_PCSWKCTL_WKPSEL_Pos) /*!< CLK_T::PCSWKCTL: WKPSEL Mask */ 2418 2419 #define CLK_PCSWKCTL_DBEN_Pos (8) /*!< CLK_T::PCSWKCTL: DBEN Position */ 2420 #define CLK_PCSWKCTL_DBEN_Msk (0x1ul << CLK_PCSWKCTL_DBEN_Pos) /*!< CLK_T::PCSWKCTL: DBEN Mask */ 2421 2422 #define CLK_PDSWKCTL_WKEN_Pos (0) /*!< CLK_T::PDSWKCTL: WKEN Position */ 2423 #define CLK_PDSWKCTL_WKEN_Msk (0x1ul << CLK_PDSWKCTL_WKEN_Pos) /*!< CLK_T::PDSWKCTL: WKEN Mask */ 2424 2425 #define CLK_PDSWKCTL_PRWKEN_Pos (1) /*!< CLK_T::PDSWKCTL: PRWKEN Position */ 2426 #define CLK_PDSWKCTL_PRWKEN_Msk (0x1ul << CLK_PDSWKCTL_PRWKEN_Pos) /*!< CLK_T::PDSWKCTL: PRWKEN Mask */ 2427 2428 #define CLK_PDSWKCTL_PFWKEN_Pos (2) /*!< CLK_T::PDSWKCTL: PFWKEN Position */ 2429 #define CLK_PDSWKCTL_PFWKEN_Msk (0x1ul << CLK_PDSWKCTL_PFWKEN_Pos) /*!< CLK_T::PDSWKCTL: PFWKEN Mask */ 2430 2431 #define CLK_PDSWKCTL_WKPSEL_Pos (4) /*!< CLK_T::PDSWKCTL: WKPSEL Position */ 2432 #define CLK_PDSWKCTL_WKPSEL_Msk (0xful << CLK_PDSWKCTL_WKPSEL_Pos) /*!< CLK_T::PDSWKCTL: WKPSEL Mask */ 2433 2434 #define CLK_PDSWKCTL_DBEN_Pos (8) /*!< CLK_T::PDSWKCTL: DBEN Position */ 2435 #define CLK_PDSWKCTL_DBEN_Msk (0x1ul << CLK_PDSWKCTL_DBEN_Pos) /*!< CLK_T::PDSWKCTL: DBEN Mask */ 2436 2437 #define CLK_IOPDCTL_IOHR_Pos (0) /*!< CLK_T::IOPDCTL: IOHR Position */ 2438 #define CLK_IOPDCTL_IOHR_Msk (0x1ul << CLK_IOPDCTL_IOHR_Pos) /*!< CLK_T::IOPDCTL: IOHR Mask */ 2439 2440 2441 /**@}*/ /* CLK_CONST */ 2442 /**@}*/ /* end of CLK register group */ 2443 /**@}*/ /* end of REGISTER group */ 2444 2445 #if defined ( __CC_ARM ) 2446 #pragma no_anon_unions 2447 #endif 2448 2449 #endif /* __CLK_REG_H__ */ 2450
