1 /**************************************************************************//**
2 * @file CLK.h
3 * @version V3.00
4 * @brief M460 Series CLK Driver Header File
5 *
6 * @copyright SPDX-License-Identifier: Apache-2.0
7 * @copyright Copyright (C) 2021 Nuvoton Technology Corp. All rights reserved.
8 ******************************************************************************/
9 #ifndef __CLK_H__
10 #define __CLK_H__
11
12 #ifdef __cplusplus
13 extern "C"
14 {
15 #endif
16
17
18 /** @addtogroup Standard_Driver Standard Driver
19 @{
20 */
21
22 /** @addtogroup CLK_Driver CLK Driver
23 @{
24 */
25
26 /** @addtogroup CLK_EXPORTED_CONSTANTS CLK Exported Constants
27 @{
28 */
29
30
31 #define FREQ_1MHZ 1000000UL /*!< 1 MHz \hideinitializer */
32 #define FREQ_4MHZ 4000000UL /*!< 4 MHz \hideinitializer */
33 #define FREQ_8MHZ 8000000UL /*!< 8 MHz \hideinitializer */
34 #define FREQ_25MHZ 25000000UL /*!< 25 MHz \hideinitializer */
35 #define FREQ_50MHZ 50000000UL /*!< 50 MHz \hideinitializer */
36 #define FREQ_75MHZ 75000000UL /*!< 75 MHz \hideinitializer */
37 #define FREQ_100MHZ 100000000UL /*!< 100 MHz \hideinitializer */
38 #define FREQ_125MHZ 125000000UL /*!< 125 MHz \hideinitializer */
39 #define FREQ_150MHZ 150000000UL /*!< 50 MHz \hideinitializer */
40 #define FREQ_175MHZ 175000000UL /*!< 175 MHz \hideinitializer */
41 #define FREQ_180MHZ 180000000UL /*!< 180 MHz \hideinitializer */
42 #define FREQ_192MHZ 192000000UL /*!< 192 MHz \hideinitializer */
43 #define FREQ_200MHZ 200000000UL /*!< 200 MHz \hideinitializer */
44 #define FREQ_500MHZ 500000000UL /*!< 500 MHz \hideinitializer */
45
46 /*---------------------------------------------------------------------------------------------------------*/
47 /* CLKSEL0 constant definitions. (Write-protection) */
48 /*---------------------------------------------------------------------------------------------------------*/
49 #define CLK_CLKSEL0_HCLKSEL_HXT (0x0UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from high speed crystal \hideinitializer */
50 #define CLK_CLKSEL0_HCLKSEL_LXT (0x1UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from low speed crystal \hideinitializer */
51 #define CLK_CLKSEL0_HCLKSEL_PLL (0x2UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from PLL \hideinitializer */
52 #define CLK_CLKSEL0_HCLKSEL_LIRC (0x3UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from low speed oscillator \hideinitializer */
53 #define CLK_CLKSEL0_HCLKSEL_HIRC (0x7UL << CLK_CLKSEL0_HCLKSEL_Pos) /*!< Select HCLK clock source from high speed oscillator \hideinitializer */
54
55 #define CLK_CLKSEL0_STCLKSEL_HXT (0x0UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from high speed crystal \hideinitializer */
56 #define CLK_CLKSEL0_STCLKSEL_LXT (0x1UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from low speed crystal \hideinitializer */
57 #define CLK_CLKSEL0_STCLKSEL_HXT_DIV2 (0x2UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from HXT/2 \hideinitializer */
58 #define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 (0x3UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from HCLK/2 \hideinitializer */
59 #define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 (0x7UL << CLK_CLKSEL0_STCLKSEL_Pos) /*!< Select SysTick clock source from HIRC/2 \hideinitializer */
60 #define CLK_CLKSEL0_STCLKSEL_HCLK (0x1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< Select SysTick clock source from HCLK \hideinitializer */
61
62 #define CLK_CLKSEL0_USBSEL_HIRC48M (0x0UL << CLK_CLKSEL0_USBSEL_Pos) /*!< Select USB clock source from HIRC48M \hideinitializer */
63 #define CLK_CLKSEL0_USBSEL_PLL_DIV2 (0x1UL << CLK_CLKSEL0_USBSEL_Pos) /*!< Select USB clock source from PLL/2 \hideinitializer */
64
65 #define CLK_CLKSEL0_EADC0SEL_PLLFN_DIV2 (0x0UL << CLK_CLKSEL0_EADC0SEL_Pos) /*!< Select EADC0 clock source from PLLFN/2 \hideinitializer */
66 #define CLK_CLKSEL0_EADC0SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL0_EADC0SEL_Pos) /*!< Select EADC0 clock source from PLL/2 \hideinitializer */
67 #define CLK_CLKSEL0_EADC0SEL_HCLK (0x2UL << CLK_CLKSEL0_EADC0SEL_Pos) /*!< Select EADC0 clock source from HCLK \hideinitializer */
68
69 #define CLK_CLKSEL0_EADC1SEL_PLLFN_DIV2 (0x0UL << CLK_CLKSEL0_EADC1SEL_Pos) /*!< Select EADC1 clock source from PLLFN/2 \hideinitializer */
70 #define CLK_CLKSEL0_EADC1SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL0_EADC1SEL_Pos) /*!< Select EADC1 clock source from PLL/2 \hideinitializer */
71 #define CLK_CLKSEL0_EADC1SEL_HCLK (0x2UL << CLK_CLKSEL0_EADC1SEL_Pos) /*!< Select EADC1 clock source from HCLK \hideinitializer */
72
73 #define CLK_CLKSEL0_EADC2SEL_PLLFN_DIV2 (0x0UL << CLK_CLKSEL0_EADC2SEL_Pos) /*!< Select EADC2 clock source from PLLFN/2 \hideinitializer */
74 #define CLK_CLKSEL0_EADC2SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL0_EADC2SEL_Pos) /*!< Select EADC2 clock source from PLL/2 \hideinitializer */
75 #define CLK_CLKSEL0_EADC2SEL_HCLK (0x2UL << CLK_CLKSEL0_EADC2SEL_Pos) /*!< Select EADC2 clock source from HCLK \hideinitializer */
76
77 #define CLK_CLKSEL0_CCAPSEL_HXT (0x0UL << CLK_CLKSEL0_CCAPSEL_Pos) /*!< Select CCAP sensor clock source from HXT \hideinitializer */
78 #define CLK_CLKSEL0_CCAPSEL_PLL_DIV2 (0x1UL << CLK_CLKSEL0_CCAPSEL_Pos) /*!< Select CCAP sensor clock source from PLL/2 \hideinitializer */
79 #define CLK_CLKSEL0_CCAPSEL_HCLK (0x2UL << CLK_CLKSEL0_CCAPSEL_Pos) /*!< Select CCAP sensor clock source from HCLK \hideinitializer */
80 #define CLK_CLKSEL0_CCAPSEL_HIRC (0x3UL << CLK_CLKSEL0_CCAPSEL_Pos) /*!< Select CCAP sensor clock source from HIRC \hideinitializer */
81
82 #define CLK_CLKSEL0_SDH0SEL_HXT (0x0UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from high speed crystal \hideinitializer */
83 #define CLK_CLKSEL0_SDH0SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from PLL/2 \hideinitializer */
84 #define CLK_CLKSEL0_SDH0SEL_HCLK (0x2UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from HCLK \hideinitializer */
85 #define CLK_CLKSEL0_SDH0SEL_HIRC (0x3UL << CLK_CLKSEL0_SDH0SEL_Pos) /*!< Select SDH0 clock source from high speed oscillator \hideinitializer */
86
87 #define CLK_CLKSEL0_SDH1SEL_HXT (0x0UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from high speed crystal \hideinitializer */
88 #define CLK_CLKSEL0_SDH1SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from PLL/2 \hideinitializer */
89 #define CLK_CLKSEL0_SDH1SEL_HCLK (0x2UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from HCLK \hideinitializer */
90 #define CLK_CLKSEL0_SDH1SEL_HIRC (0x3UL << CLK_CLKSEL0_SDH1SEL_Pos) /*!< Select SDH1 clock source from high speed oscillator \hideinitializer */
91
92 #define CLK_CLKSEL0_CANFD0SEL_HXT (0x0UL << CLK_CLKSEL0_CANFD0SEL_Pos) /*!< Select CANFD0 clock source from HXT \hideinitializer */
93 #define CLK_CLKSEL0_CANFD0SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL0_CANFD0SEL_Pos) /*!< Select CANFD0 clock source from PLL/2 \hideinitializer */
94 #define CLK_CLKSEL0_CANFD0SEL_HCLK (0x2UL << CLK_CLKSEL0_CANFD0SEL_Pos) /*!< Select CANFD0 clock source from HCLK \hideinitializer */
95 #define CLK_CLKSEL0_CANFD0SEL_HIRC (0x3UL << CLK_CLKSEL0_CANFD0SEL_Pos) /*!< Select CANFD0 clock source from HIRC \hideinitializer */
96
97 #define CLK_CLKSEL0_CANFD1SEL_HXT (0x0UL << CLK_CLKSEL0_CANFD1SEL_Pos) /*!< Select CANFD1 clock source from HXT \hideinitializer */
98 #define CLK_CLKSEL0_CANFD1SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL0_CANFD1SEL_Pos) /*!< Select CANFD1 clock source from PLL/2 \hideinitializer */
99 #define CLK_CLKSEL0_CANFD1SEL_HCLK (0x2UL << CLK_CLKSEL0_CANFD1SEL_Pos) /*!< Select CANFD1 clock source from HCLK \hideinitializer */
100 #define CLK_CLKSEL0_CANFD1SEL_HIRC (0x3UL << CLK_CLKSEL0_CANFD1SEL_Pos) /*!< Select CANFD1 clock source from HIRC \hideinitializer */
101
102 #define CLK_CLKSEL0_CANFD2SEL_HXT (0x0UL << CLK_CLKSEL0_CANFD2SEL_Pos) /*!< Select CANFD2 clock source from HXT \hideinitializer */
103 #define CLK_CLKSEL0_CANFD2SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL0_CANFD2SEL_Pos) /*!< Select CANFD2 clock source from PLL/2 \hideinitializer */
104 #define CLK_CLKSEL0_CANFD2SEL_HCLK (0x2UL << CLK_CLKSEL0_CANFD2SEL_Pos) /*!< Select CANFD2 clock source from HCLK \hideinitializer */
105 #define CLK_CLKSEL0_CANFD2SEL_HIRC (0x3UL << CLK_CLKSEL0_CANFD2SEL_Pos) /*!< Select CANFD2 clock source from HIRC \hideinitializer */
106
107 #define CLK_CLKSEL0_CANFD3SEL_HXT (0x0UL << CLK_CLKSEL0_CANFD3SEL_Pos) /*!< Select CANFD3 clock source from HXT \hideinitializer */
108 #define CLK_CLKSEL0_CANFD3SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL0_CANFD3SEL_Pos) /*!< Select CANFD3 clock source from PLL/2 \hideinitializer */
109 #define CLK_CLKSEL0_CANFD3SEL_HCLK (0x2UL << CLK_CLKSEL0_CANFD3SEL_Pos) /*!< Select CANFD3 clock source from HCLK \hideinitializer */
110 #define CLK_CLKSEL0_CANFD3SEL_HIRC (0x3UL << CLK_CLKSEL0_CANFD3SEL_Pos) /*!< Select CANFD3 clock source from HIRC \hideinitializer */
111
112
113 /*---------------------------------------------------------------------------------------------------------*/
114 /* CLKSEL1 constant definitions. */
115 /*---------------------------------------------------------------------------------------------------------*/
116 #define CLK_CLKSEL1_WDTSEL_LXT (0x1UL << CLK_CLKSEL1_WDTSEL_Pos) /*!< Select WDT clock source from low speed crystal \hideinitializer */
117 #define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 (0x2UL << CLK_CLKSEL1_WDTSEL_Pos) /*!< Select WDT clock source from HCLK/2048 \hideinitializer */
118 #define CLK_CLKSEL1_WDTSEL_LIRC (0x3UL << CLK_CLKSEL1_WDTSEL_Pos) /*!< Select WDT clock source from low speed oscillator \hideinitializer */
119
120 #define CLK_CLKSEL1_CLKOSEL_HXT (0x0UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from HXT \hideinitializer */
121 #define CLK_CLKSEL1_CLKOSEL_LXT (0x1UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from LXT \hideinitializer */
122 #define CLK_CLKSEL1_CLKOSEL_HCLK (0x2UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from HCLK \hideinitializer */
123 #define CLK_CLKSEL1_CLKOSEL_HIRC (0x3UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from HIRC \hideinitializer */
124 #define CLK_CLKSEL1_CLKOSEL_LIRC (0x4UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from LIRC \hideinitializer */
125 #define CLK_CLKSEL1_CLKOSEL_PLLFN_DIV2 (0x5UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from PLLFN/2 \hideinitializer */
126 #define CLK_CLKSEL1_CLKOSEL_PLL_DIV2 (0x6UL << CLK_CLKSEL1_CLKOSEL_Pos) /*!< Select CLKO clock source from PLL/2 \hideinitializer */
127
128 #define CLK_CLKSEL1_TMR0SEL_HXT (0x0UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from high speed crystal \hideinitializer */
129 #define CLK_CLKSEL1_TMR0SEL_LXT (0x1UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from low speed crystal \hideinitializer */
130 #define CLK_CLKSEL1_TMR0SEL_PCLK0 (0x2UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from PCLK0 \hideinitializer */
131 #define CLK_CLKSEL1_TMR0SEL_EXT (0x3UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from external trigger \hideinitializer */
132 #define CLK_CLKSEL1_TMR0SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from low speed oscillator \hideinitializer */
133 #define CLK_CLKSEL1_TMR0SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR0SEL_Pos) /*!< Select TMR0 clock source from high speed oscillator \hideinitializer */
134
135 #define CLK_CLKSEL1_TMR1SEL_HXT (0x0UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from high speed crystal \hideinitializer */
136 #define CLK_CLKSEL1_TMR1SEL_LXT (0x1UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from low speed crystal \hideinitializer */
137 #define CLK_CLKSEL1_TMR1SEL_PCLK0 (0x2UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from PCLK0 \hideinitializer */
138 #define CLK_CLKSEL1_TMR1SEL_EXT (0x3UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from external trigger \hideinitializer */
139 #define CLK_CLKSEL1_TMR1SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from low speed oscillator \hideinitializer */
140 #define CLK_CLKSEL1_TMR1SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR1SEL_Pos) /*!< Select TMR1 clock source from high speed oscillator \hideinitializer */
141
142 #define CLK_CLKSEL1_TMR2SEL_HXT (0x0UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from high speed crystal \hideinitializer */
143 #define CLK_CLKSEL1_TMR2SEL_LXT (0x1UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from low speed crystal \hideinitializer */
144 #define CLK_CLKSEL1_TMR2SEL_PCLK1 (0x2UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from PCLK1 \hideinitializer */
145 #define CLK_CLKSEL1_TMR2SEL_EXT (0x3UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from external trigger \hideinitializer */
146 #define CLK_CLKSEL1_TMR2SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from low speed oscillator \hideinitializer */
147 #define CLK_CLKSEL1_TMR2SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR2SEL_Pos) /*!< Select TMR2 clock source from high speed oscillator \hideinitializer */
148
149 #define CLK_CLKSEL1_TMR3SEL_HXT (0x0UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from high speed crystal \hideinitializer */
150 #define CLK_CLKSEL1_TMR3SEL_LXT (0x1UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from low speed crystal \hideinitializer */
151 #define CLK_CLKSEL1_TMR3SEL_PCLK1 (0x2UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from PCLK1 \hideinitializer */
152 #define CLK_CLKSEL1_TMR3SEL_EXT (0x3UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from external trigger \hideinitializer */
153 #define CLK_CLKSEL1_TMR3SEL_LIRC (0x5UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from low speed oscillator \hideinitializer */
154 #define CLK_CLKSEL1_TMR3SEL_HIRC (0x7UL << CLK_CLKSEL1_TMR3SEL_Pos) /*!< Select TMR3 clock source from high speed oscillator \hideinitializer */
155
156 #define CLK_CLKSEL1_UART0SEL_HXT (0x0UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from high speed crystal \hideinitializer */
157 #define CLK_CLKSEL1_UART0SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from PLL/2 \hideinitializer */
158 #define CLK_CLKSEL1_UART0SEL_LXT (0x2UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from low speed crystal \hideinitializer */
159 #define CLK_CLKSEL1_UART0SEL_HIRC (0x3UL << CLK_CLKSEL1_UART0SEL_Pos) /*!< Select UART0 clock source from high speed oscillator \hideinitializer */
160
161 #define CLK_CLKSEL1_UART1SEL_HXT (0x0UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from high speed crystal \hideinitializer */
162 #define CLK_CLKSEL1_UART1SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from PLL/2 \hideinitializer */
163 #define CLK_CLKSEL1_UART1SEL_LXT (0x2UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from low speed crystal \hideinitializer */
164 #define CLK_CLKSEL1_UART1SEL_HIRC (0x3UL << CLK_CLKSEL1_UART1SEL_Pos) /*!< Select UART1 clock source from high speed oscillator \hideinitializer */
165
166 #define CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 (0x2UL << CLK_CLKSEL1_WWDTSEL_Pos) /*!< Select WWDT clock source from HCLK/2048 \hideinitializer */
167 #define CLK_CLKSEL1_WWDTSEL_LIRC (0x3UL << CLK_CLKSEL1_WWDTSEL_Pos) /*!< Select WWDT clock source from low speed oscillator \hideinitializer */
168
169
170 /*---------------------------------------------------------------------------------------------------------*/
171 /* CLKSEL2 constant definitions. */
172 /*---------------------------------------------------------------------------------------------------------*/
173 #define CLK_CLKSEL2_EPWM0SEL_HCLK (0x0UL << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< Select EPWM0 clock source from HCLK \hideinitializer */
174 #define CLK_CLKSEL2_EPWM0SEL_PCLK0 (0x1UL << CLK_CLKSEL2_EPWM0SEL_Pos) /*!< Select EPWM0 clock source from PCLK0 \hideinitializer */
175
176 #define CLK_CLKSEL2_EPWM1SEL_HCLK (0x0UL << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< Select EPWM1 clock source from HCLK \hideinitializer */
177 #define CLK_CLKSEL2_EPWM1SEL_PCLK1 (0x1UL << CLK_CLKSEL2_EPWM1SEL_Pos) /*!< Select EPWM1 clock source from PCLK1 \hideinitializer */
178
179 #define CLK_CLKSEL2_QSPI0SEL_HXT (0x0UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from high speed crystal \hideinitializer */
180 #define CLK_CLKSEL2_QSPI0SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from PLL/2 \hideinitializer */
181 #define CLK_CLKSEL2_QSPI0SEL_PCLK0 (0x2UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from PCLK0 \hideinitializer */
182 #define CLK_CLKSEL2_QSPI0SEL_HIRC (0x3UL << CLK_CLKSEL2_QSPI0SEL_Pos) /*!< Select QSPI0 clock source from high speed oscillator \hideinitializer */
183
184 #define CLK_CLKSEL2_SPI0SEL_HXT (0x0UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from high speed crystal \hideinitializer */
185 #define CLK_CLKSEL2_SPI0SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from PLL/2 \hideinitializer */
186 #define CLK_CLKSEL2_SPI0SEL_PCLK1 (0x2UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from PCLK1 \hideinitializer */
187 #define CLK_CLKSEL2_SPI0SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from high speed oscillator \hideinitializer */
188 #define CLK_CLKSEL2_SPI0SEL_HIRC48M (0x4UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from HIRC48M \hideinitializer */
189 #define CLK_CLKSEL2_SPI0SEL_PLLFN_DIV2 (0x5UL << CLK_CLKSEL2_SPI0SEL_Pos) /*!< Select SPI0 clock source from PLLFN/2 \hideinitializer */
190
191 #define CLK_CLKSEL2_BPWM0SEL_HCLK (0x0UL << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< Select BPWM0 clock source from HCLK \hideinitializer */
192 #define CLK_CLKSEL2_BPWM0SEL_PCLK0 (0x1UL << CLK_CLKSEL2_BPWM0SEL_Pos) /*!< Select BPWM0 clock source from PCLK0 \hideinitializer */
193
194 #define CLK_CLKSEL2_BPWM1SEL_HCLK (0x0UL << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< Select BPWM1 clock source from HCLK \hideinitializer */
195 #define CLK_CLKSEL2_BPWM1SEL_PCLK1 (0x1UL << CLK_CLKSEL2_BPWM1SEL_Pos) /*!< Select BPWM1 clock source from PCLK1 \hideinitializer */
196
197 #define CLK_CLKSEL2_QSPI1SEL_HXT (0x0UL << CLK_CLKSEL2_QSPI1SEL_Pos) /*!< Select QSPI1 clock source from high speed crystal \hideinitializer */
198 #define CLK_CLKSEL2_QSPI1SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL2_QSPI1SEL_Pos) /*!< Select QSPI1 clock source from PLL/2 \hideinitializer */
199 #define CLK_CLKSEL2_QSPI1SEL_PCLK1 (0x2UL << CLK_CLKSEL2_QSPI1SEL_Pos) /*!< Select QSPI1 clock source from PCLK1 \hideinitializer */
200 #define CLK_CLKSEL2_QSPI1SEL_HIRC (0x3UL << CLK_CLKSEL2_QSPI1SEL_Pos) /*!< Select QSPI1 clock source from high speed oscillator \hideinitializer */
201
202 #define CLK_CLKSEL2_SPI1SEL_HXT (0x0UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from high speed crystal \hideinitializer */
203 #define CLK_CLKSEL2_SPI1SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from PLL/2 \hideinitializer */
204 #define CLK_CLKSEL2_SPI1SEL_PCLK0 (0x2UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from PCLK0 \hideinitializer */
205 #define CLK_CLKSEL2_SPI1SEL_HIRC (0x3UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from high speed oscillator \hideinitializer */
206 #define CLK_CLKSEL2_SPI1SEL_HIRC48M (0x4UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from HIRC48M \hideinitializer */
207 #define CLK_CLKSEL2_SPI1SEL_PLLFN_DIV2 (0x5UL << CLK_CLKSEL2_SPI1SEL_Pos) /*!< Select SPI1 clock source from PLLFN/2 \hideinitializer */
208
209 #define CLK_CLKSEL2_I2S1SEL_HXT (0x0UL << CLK_CLKSEL2_I2S1SEL_Pos) /*!< Select I2S1 clock source from HXT \hideinitializer */
210 #define CLK_CLKSEL2_I2S1SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL2_I2S1SEL_Pos) /*!< Select I2S1 clock source from PLL/2 \hideinitializer */
211 #define CLK_CLKSEL2_I2S1SEL_PCLK1 (0x2UL << CLK_CLKSEL2_I2S1SEL_Pos) /*!< Select I2S1 clock source from PCLK1 \hideinitializer */
212 #define CLK_CLKSEL2_I2S1SEL_HIRC (0x3UL << CLK_CLKSEL2_I2S1SEL_Pos) /*!< Select I2S1 clock source from HIRC \hideinitializer */
213 #define CLK_CLKSEL2_I2S1SEL_HIRC48M (0x4UL << CLK_CLKSEL2_I2S1SEL_Pos) /*!< Select I2S1 clock source from HIRC48M \hideinitializer */
214 #define CLK_CLKSEL2_I2S1SEL_PLLFN_DIV2 (0x5UL << CLK_CLKSEL2_I2S1SEL_Pos) /*!< Select I2S1 clock source from PLLFN/2 \hideinitializer */
215
216 #define CLK_CLKSEL2_UART8SEL_HXT (0x0UL << CLK_CLKSEL2_UART8SEL_Pos) /*!< Select UART8 clock source from HXT \hideinitializer */
217 #define CLK_CLKSEL2_UART8SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL2_UART8SEL_Pos) /*!< Select UART8 clock source from PLL/2 \hideinitializer */
218 #define CLK_CLKSEL2_UART8SEL_LXT (0x2UL << CLK_CLKSEL2_UART8SEL_Pos) /*!< Select UART8 clock source from LXT \hideinitializer */
219 #define CLK_CLKSEL2_UART8SEL_HIRC (0x3UL << CLK_CLKSEL2_UART8SEL_Pos) /*!< Select UART8 clock source from HIRC \hideinitializer */
220
221 #define CLK_CLKSEL2_UART9SEL_HXT (0x0UL << CLK_CLKSEL2_UART9SEL_Pos) /*!< Select UART9 clock source from HXT \hideinitializer */
222 #define CLK_CLKSEL2_UART9SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL2_UART9SEL_Pos) /*!< Select UART9 clock source from PLL/2 \hideinitializer */
223 #define CLK_CLKSEL2_UART9SEL_LXT (0x2UL << CLK_CLKSEL2_UART9SEL_Pos) /*!< Select UART9 clock source from LXT \hideinitializer */
224 #define CLK_CLKSEL2_UART9SEL_HIRC (0x3UL << CLK_CLKSEL2_UART9SEL_Pos) /*!< Select UART9 clock source from HIRC \hideinitializer */
225
226 #define CLK_CLKSEL2_TRNGSEL_LXT (0x0UL << CLK_CLKSEL2_TRNGSEL_Pos) /*!< Select TRNG clock source from LXT \hideinitializer */
227 #define CLK_CLKSEL2_TRNGSEL_LIRC (0x1UL << CLK_CLKSEL2_TRNGSEL_Pos) /*!< Select TRNG clock source from LIRC \hideinitializer */
228
229 #define CLK_CLKSEL2_PSIOSEL_HXT (0x0UL << CLK_CLKSEL2_PSIOSEL_Pos) /*!< Select PSIO clock source from LXT \hideinitializer */
230 #define CLK_CLKSEL2_PSIOSEL_LXT (0x1UL << CLK_CLKSEL2_PSIOSEL_Pos) /*!< Select PSIO clock source from LIRC \hideinitializer */
231 #define CLK_CLKSEL2_PSIOSEL_PCLK1 (0x2UL << CLK_CLKSEL2_PSIOSEL_Pos) /*!< Select PSIO clock source from PCLK1 \hideinitializer */
232 #define CLK_CLKSEL2_PSIOSEL_PLL_DIV2 (0x3UL << CLK_CLKSEL2_PSIOSEL_Pos) /*!< Select PSIO clock source from PLL/2 \hideinitializer */
233 #define CLK_CLKSEL2_PSIOSEL_LIRC (0x4UL << CLK_CLKSEL2_PSIOSEL_Pos) /*!< Select PSIO clock source from LIRC \hideinitializer */
234 #define CLK_CLKSEL2_PSIOSEL_HIRC (0x5UL << CLK_CLKSEL2_PSIOSEL_Pos) /*!< Select PSIO clock source from HIRC \hideinitializer */
235
236 /*---------------------------------------------------------------------------------------------------------*/
237 /* CLKSEL3 constant definitions. */
238 /*---------------------------------------------------------------------------------------------------------*/
239 #define CLK_CLKSEL3_SC0SEL_HXT (0x0UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from high speed crystal \hideinitializer */
240 #define CLK_CLKSEL3_SC0SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from PLL/2 \hideinitializer */
241 #define CLK_CLKSEL3_SC0SEL_PCLK0 (0x2UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from PCLK0 \hideinitializer */
242 #define CLK_CLKSEL3_SC0SEL_HIRC (0x3UL << CLK_CLKSEL3_SC0SEL_Pos) /*!< Select SC0 clock source from high speed oscillator \hideinitializer */
243
244 #define CLK_CLKSEL3_SC1SEL_HXT (0x0UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from high speed crystal \hideinitializer */
245 #define CLK_CLKSEL3_SC1SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from PLL/2 \hideinitializer */
246 #define CLK_CLKSEL3_SC1SEL_PCLK1 (0x2UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from PCLK1 \hideinitializer */
247 #define CLK_CLKSEL3_SC1SEL_HIRC (0x3UL << CLK_CLKSEL3_SC1SEL_Pos) /*!< Select SC1 clock source from high speed oscillator \hideinitializer */
248
249 #define CLK_CLKSEL3_SC2SEL_HXT (0x0UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from high speed crystal \hideinitializer */
250 #define CLK_CLKSEL3_SC2SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from PLL/2 \hideinitializer */
251 #define CLK_CLKSEL3_SC2SEL_PCLK0 (0x2UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from PCLK0 \hideinitializer */
252 #define CLK_CLKSEL3_SC2SEL_HIRC (0x3UL << CLK_CLKSEL3_SC2SEL_Pos) /*!< Select SC2 clock source from high speed oscillator \hideinitializer */
253
254 #define CLK_CLKSEL3_KPISEL_HXT (0x0UL << CLK_CLKSEL3_KPISEL_Pos) /*!< Select KPI clock source from high speed crystal \hideinitializer */
255 #define CLK_CLKSEL3_KPISEL_LIRC (0x1UL << CLK_CLKSEL3_KPISEL_Pos) /*!< Select KPI clock source from low speed oscillator \hideinitializer */
256 #define CLK_CLKSEL3_KPISEL_HIRC (0x2UL << CLK_CLKSEL3_KPISEL_Pos) /*!< Select KPI clock source from high speed oscillator \hideinitializer */
257
258 #define CLK_CLKSEL3_SPI2SEL_HXT (0x0UL << CLK_CLKSEL3_SPI2SEL_Pos) /*!< Select SPI2 clock source from high speed crystal \hideinitializer */
259 #define CLK_CLKSEL3_SPI2SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL3_SPI2SEL_Pos) /*!< Select SPI2 clock source from PLL/2 \hideinitializer */
260 #define CLK_CLKSEL3_SPI2SEL_PCLK1 (0x2UL << CLK_CLKSEL3_SPI2SEL_Pos) /*!< Select SPI2 clock source from PCLK1 \hideinitializer */
261 #define CLK_CLKSEL3_SPI2SEL_HIRC (0x3UL << CLK_CLKSEL3_SPI2SEL_Pos) /*!< Select SPI2 clock source from high speed oscillator \hideinitializer */
262 #define CLK_CLKSEL3_SPI2SEL_HIRC48M (0x4UL << CLK_CLKSEL3_SPI2SEL_Pos) /*!< Select SPI2 clock source from HIRC48M \hideinitializer */
263 #define CLK_CLKSEL3_SPI2SEL_PLLFN_DIV2 (0x5UL << CLK_CLKSEL3_SPI2SEL_Pos) /*!< Select SPI2 clock source from PLLFN/2 \hideinitializer */
264
265 #define CLK_CLKSEL3_SPI3SEL_HXT (0x0UL << CLK_CLKSEL3_SPI3SEL_Pos) /*!< Select SPI3 clock source from high speed crystal \hideinitializer */
266 #define CLK_CLKSEL3_SPI3SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL3_SPI3SEL_Pos) /*!< Select SPI3 clock source from PLL/2 \hideinitializer */
267 #define CLK_CLKSEL3_SPI3SEL_PCLK0 (0x2UL << CLK_CLKSEL3_SPI3SEL_Pos) /*!< Select SPI3 clock source from PCLK0 \hideinitializer */
268 #define CLK_CLKSEL3_SPI3SEL_HIRC (0x3UL << CLK_CLKSEL3_SPI3SEL_Pos) /*!< Select SPI3 clock source from high speed oscillator \hideinitializer */
269 #define CLK_CLKSEL3_SPI3SEL_HIRC48M (0x4UL << CLK_CLKSEL3_SPI3SEL_Pos) /*!< Select SPI3 clock source from HIRC48M \hideinitializer */
270 #define CLK_CLKSEL3_SPI3SEL_PLLFN_DIV2 (0x5UL << CLK_CLKSEL3_SPI3SEL_Pos) /*!< Select SPI3 clock source from PLLFN/2 \hideinitializer */
271
272 #define CLK_CLKSEL3_I2S0SEL_HXT (0x0UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from high speed crystal \hideinitializer */
273 #define CLK_CLKSEL3_I2S0SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from PLL/2 \hideinitializer */
274 #define CLK_CLKSEL3_I2S0SEL_PCLK0 (0x2UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from PCLK0 \hideinitializer */
275 #define CLK_CLKSEL3_I2S0SEL_HIRC (0x3UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from high speed oscillator \hideinitializer */
276 #define CLK_CLKSEL3_I2S0SEL_HIRC48M (0x4UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from HIRC48M \hideinitializer */
277 #define CLK_CLKSEL3_I2S0SEL_PLLFN_DIV2 (0x5UL << CLK_CLKSEL3_I2S0SEL_Pos) /*!< Select I2S0 clock source from PLLFN/2 \hideinitializer */
278
279 #define CLK_CLKSEL3_UART6SEL_HXT (0x0UL << CLK_CLKSEL3_UART6SEL_Pos) /*!< Select UART6 clock source from HXT \hideinitializer */
280 #define CLK_CLKSEL3_UART6SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL3_UART6SEL_Pos) /*!< Select UART6 clock source from PLL/2 \hideinitializer */
281 #define CLK_CLKSEL3_UART6SEL_LXT (0x2UL << CLK_CLKSEL3_UART6SEL_Pos) /*!< Select UART6 clock source from LXT \hideinitializer */
282 #define CLK_CLKSEL3_UART6SEL_HIRC (0x3UL << CLK_CLKSEL3_UART6SEL_Pos) /*!< Select UART6 clock source from HIRC \hideinitializer */
283
284 #define CLK_CLKSEL3_UART7SEL_HXT (0x0UL << CLK_CLKSEL3_UART7SEL_Pos) /*!< Select UART7 clock source from HXT \hideinitializer */
285 #define CLK_CLKSEL3_UART7SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL3_UART7SEL_Pos) /*!< Select UART7 clock source from PLL/2 \hideinitializer */
286 #define CLK_CLKSEL3_UART7SEL_LXT (0x2UL << CLK_CLKSEL3_UART7SEL_Pos) /*!< Select UART7 clock source from LXT \hideinitializer */
287 #define CLK_CLKSEL3_UART7SEL_HIRC (0x3UL << CLK_CLKSEL3_UART7SEL_Pos) /*!< Select UART7 clock source from HIRC \hideinitializer */
288
289 #define CLK_CLKSEL3_UART2SEL_HXT (0x0UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from high speed crystal \hideinitializer */
290 #define CLK_CLKSEL3_UART2SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from PLL/2 \hideinitializer */
291 #define CLK_CLKSEL3_UART2SEL_LXT (0x2UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from low speed crystal \hideinitializer */
292 #define CLK_CLKSEL3_UART2SEL_HIRC (0x3UL << CLK_CLKSEL3_UART2SEL_Pos) /*!< Select UART2 clock source from high speed oscillator \hideinitializer */
293
294 #define CLK_CLKSEL3_UART3SEL_HXT (0x0UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from high speed crystal \hideinitializer */
295 #define CLK_CLKSEL3_UART3SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from PLL/2 \hideinitializer */
296 #define CLK_CLKSEL3_UART3SEL_LXT (0x2UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from low speed crystal \hideinitializer */
297 #define CLK_CLKSEL3_UART3SEL_HIRC (0x3UL << CLK_CLKSEL3_UART3SEL_Pos) /*!< Select UART3 clock source from high speed oscillator \hideinitializer */
298
299 #define CLK_CLKSEL3_UART4SEL_HXT (0x0UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from high speed crystal \hideinitializer */
300 #define CLK_CLKSEL3_UART4SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from PLL/2 \hideinitializer */
301 #define CLK_CLKSEL3_UART4SEL_LXT (0x2UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from low speed crystal \hideinitializer */
302 #define CLK_CLKSEL3_UART4SEL_HIRC (0x3UL << CLK_CLKSEL3_UART4SEL_Pos) /*!< Select UART4 clock source from high speed oscillator \hideinitializer */
303
304 #define CLK_CLKSEL3_UART5SEL_HXT (0x0UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from high speed crystal \hideinitializer */
305 #define CLK_CLKSEL3_UART5SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from PLL/2 \hideinitializer */
306 #define CLK_CLKSEL3_UART5SEL_LXT (0x2UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from low speed crystal \hideinitializer */
307 #define CLK_CLKSEL3_UART5SEL_HIRC (0x3UL << CLK_CLKSEL3_UART5SEL_Pos) /*!< Select UART5 clock source from high speed oscillator \hideinitializer */
308
309 /*---------------------------------------------------------------------------------------------------------*/
310 /* CLKSEL4 constant definitions. */
311 /*---------------------------------------------------------------------------------------------------------*/
312 #define CLK_CLKSEL4_SPI4SEL_HXT (0x0UL << CLK_CLKSEL4_SPI4SEL_Pos) /*!< Select SPI4 clock source from high speed crystal \hideinitializer */
313 #define CLK_CLKSEL4_SPI4SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL4_SPI4SEL_Pos) /*!< Select SPI4 clock source from PLL/2 \hideinitializer */
314 #define CLK_CLKSEL4_SPI4SEL_PCLK1 (0x2UL << CLK_CLKSEL4_SPI4SEL_Pos) /*!< Select SPI4 clock source from PCLK1 \hideinitializer */
315 #define CLK_CLKSEL4_SPI4SEL_HIRC (0x3UL << CLK_CLKSEL4_SPI4SEL_Pos) /*!< Select SPI4 clock source from high speed oscillator \hideinitializer */
316
317 #define CLK_CLKSEL4_SPI5SEL_HXT (0x0UL << CLK_CLKSEL4_SPI5SEL_Pos) /*!< Select SPI5 clock source from high speed crystal \hideinitializer */
318 #define CLK_CLKSEL4_SPI5SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL4_SPI5SEL_Pos) /*!< Select SPI5 clock source from PLL/2 \hideinitializer */
319 #define CLK_CLKSEL4_SPI5SEL_PCLK0 (0x2UL << CLK_CLKSEL4_SPI5SEL_Pos) /*!< Select SPI5 clock source from PCLK0 \hideinitializer */
320 #define CLK_CLKSEL4_SPI5SEL_HIRC (0x3UL << CLK_CLKSEL4_SPI5SEL_Pos) /*!< Select SPI5 clock source from high speed oscillator \hideinitializer */
321
322 #define CLK_CLKSEL4_SPI6SEL_HXT (0x0UL << CLK_CLKSEL4_SPI6SEL_Pos) /*!< Select SPI6 clock source from high speed crystal \hideinitializer */
323 #define CLK_CLKSEL4_SPI6SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL4_SPI6SEL_Pos) /*!< Select SPI6 clock source from PLL/2 \hideinitializer */
324 #define CLK_CLKSEL4_SPI6SEL_PCLK1 (0x2UL << CLK_CLKSEL4_SPI6SEL_Pos) /*!< Select SPI6 clock source from PCLK1 \hideinitializer */
325 #define CLK_CLKSEL4_SPI6SEL_HIRC (0x3UL << CLK_CLKSEL4_SPI6SEL_Pos) /*!< Select SPI6 clock source from high speed oscillator \hideinitializer */
326
327 #define CLK_CLKSEL4_SPI7SEL_HXT (0x0UL << CLK_CLKSEL4_SPI7SEL_Pos) /*!< Select SPI7 clock source from high speed crystal \hideinitializer */
328 #define CLK_CLKSEL4_SPI7SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL4_SPI7SEL_Pos) /*!< Select SPI7 clock source from PLL/2 \hideinitializer */
329 #define CLK_CLKSEL4_SPI7SEL_PCLK0 (0x2UL << CLK_CLKSEL4_SPI7SEL_Pos) /*!< Select SPI7 clock source from PCLK0 \hideinitializer */
330 #define CLK_CLKSEL4_SPI7SEL_HIRC (0x3UL << CLK_CLKSEL4_SPI7SEL_Pos) /*!< Select SPI7 clock source from high speed oscillator \hideinitializer */
331
332 #define CLK_CLKSEL4_SPI8SEL_HXT (0x0UL << CLK_CLKSEL4_SPI8SEL_Pos) /*!< Select SPI8 clock source from high speed crystal \hideinitializer */
333 #define CLK_CLKSEL4_SPI8SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL4_SPI8SEL_Pos) /*!< Select SPI8 clock source from PLL/2 \hideinitializer */
334 #define CLK_CLKSEL4_SPI8SEL_PCLK1 (0x2UL << CLK_CLKSEL4_SPI8SEL_Pos) /*!< Select SPI8 clock source from PCLK1 \hideinitializer */
335 #define CLK_CLKSEL4_SPI8SEL_HIRC (0x3UL << CLK_CLKSEL4_SPI8SEL_Pos) /*!< Select SPI8 clock source from high speed oscillator \hideinitializer */
336
337 #define CLK_CLKSEL4_SPI9SEL_HXT (0x0UL << CLK_CLKSEL4_SPI9SEL_Pos) /*!< Select SPI9 clock source from high speed crystal \hideinitializer */
338 #define CLK_CLKSEL4_SPI9SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL4_SPI9SEL_Pos) /*!< Select SPI9 clock source from PLL/2 \hideinitializer */
339 #define CLK_CLKSEL4_SPI9SEL_PCLK0 (0x2UL << CLK_CLKSEL4_SPI9SEL_Pos) /*!< Select SPI9 clock source from PCLK0 \hideinitializer */
340 #define CLK_CLKSEL4_SPI9SEL_HIRC (0x3UL << CLK_CLKSEL4_SPI9SEL_Pos) /*!< Select SPI9 clock source from high speed oscillator \hideinitializer */
341
342 #define CLK_CLKSEL4_SPI10SEL_HXT (0x0UL << CLK_CLKSEL4_SPI10SEL_Pos) /*!< Select SPI10 clock source from high speed crystal \hideinitializer */
343 #define CLK_CLKSEL4_SPI10SEL_PLL_DIV2 (0x1UL << CLK_CLKSEL4_SPI10SEL_Pos) /*!< Select SPI10 clock source from PLL/2 \hideinitializer */
344 #define CLK_CLKSEL4_SPI10SEL_PCLK1 (0x2UL << CLK_CLKSEL4_SPI10SEL_Pos) /*!< Select SPI10 clock source from PCLK1 \hideinitializer */
345 #define CLK_CLKSEL4_SPI10SEL_HIRC (0x3UL << CLK_CLKSEL4_SPI10SEL_Pos) /*!< Select SPI10 clock source from high speed oscillator \hideinitializer */
346
347 /*---------------------------------------------------------------------------------------------------------*/
348 /* RTC clock source constant definitions. */
349 /*---------------------------------------------------------------------------------------------------------*/
350 #define RTC_LXTCTL_RTCCKSEL_LXT (0x0UL<<RTC_LXTCTL_RTCCKSEL_Pos) /*!< Setting RTC clock source as LXT \hideinitializer */
351 #define RTC_LXTCTL_RTCCKSEL_LIRC (0x1UL<<RTC_LXTCTL_RTCCKSEL_Pos) /*!< Setting RTC clock source as LIRC \hideinitializer */
352
353 /*---------------------------------------------------------------------------------------------------------*/
354 /* CLKDIV0 constant definitions. */
355 /*---------------------------------------------------------------------------------------------------------*/
356 #define CLK_CLKDIV0_HCLK(x) (((x) - 1UL) << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLKDIV0 Setting for HCLK clock divider. It could be 1~16 \hideinitializer */
357 #define CLK_CLKDIV0_USB(x) (((x) - 1UL) << CLK_CLKDIV0_USBDIV_Pos) /*!< CLKDIV0 Setting for USB clock divider. It could be 1~16 \hideinitializer */
358 #define CLK_CLKDIV0_SDH0(x) (((x) - 1UL) << CLK_CLKDIV0_SDH0DIV_Pos) /*!< CLKDIV0 Setting for SDH0 clock divider. It could be 1~256 \hideinitializer */
359 #define CLK_CLKDIV0_UART0(x) (((x) - 1UL) << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLKDIV0 Setting for UART0 clock divider. It could be 1~16 \hideinitializer */
360 #define CLK_CLKDIV0_UART1(x) (((x) - 1UL) << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLKDIV0 Setting for UART1 clock divider. It could be 1~16 \hideinitializer */
361 #define CLK_CLKDIV0_EADC0(x) (((x) - 1UL) << CLK_CLKDIV0_EADC0DIV_Pos) /*!< CLKDIV0 Setting for EADC0 clock divider. It could be 1~256 \hideinitializer */
362
363 /*---------------------------------------------------------------------------------------------------------*/
364 /* CLKDIV1 constant definitions. */
365 /*---------------------------------------------------------------------------------------------------------*/
366 #define CLK_CLKDIV1_SC0(x) (((x) - 1UL) << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLKDIV1 Setting for SC0 clock divider. It could be 1~256 \hideinitializer */
367 #define CLK_CLKDIV1_SC1(x) (((x) - 1UL) << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLKDIV1 Setting for SC1 clock divider. It could be 1~256 \hideinitializer */
368 #define CLK_CLKDIV1_SC2(x) (((x) - 1UL) << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLKDIV1 Setting for SC2 clock divider. It could be 1~256 \hideinitializer */
369 #define CLK_CLKDIV1_PSIO(x) (((x) - 1UL) << CLK_CLKDIV1_PSIODIV_Pos) /*!< CLKDIV1 Setting for PSIO clock divider. It could be 1~256 \hideinitializer */
370
371 /*---------------------------------------------------------------------------------------------------------*/
372 /* CLKDIV2 constant definitions. */
373 /*---------------------------------------------------------------------------------------------------------*/
374 #define CLK_CLKDIV2_I2S0(x) (((x) - 1UL) << CLK_CLKDIV2_I2S0DIV_Pos) /*!< CLKDIV2 Setting for I2S0 clock divider. It could be 1~16 */
375 #define CLK_CLKDIV2_I2S1(x) (((x) - 1UL) << CLK_CLKDIV2_I2S1DIV_Pos) /*!< CLKDIV2 Setting for I2S1 clock divider. It could be 1~16 */
376 #define CLK_CLKDIV2_KPI(x) (((x) - 1UL) << CLK_CLKDIV2_KPIDIV_Pos) /*!< CLKDIV2 Setting for KPI clock divider. It could be 1~256 */
377 #define CLK_CLKDIV2_EADC1(x) (((x) - 1UL) << CLK_CLKDIV2_EADC1DIV_Pos) /*!< CLKDIV2 Setting for EADC1 clock divider. It could be 1~256 */
378
379 /*---------------------------------------------------------------------------------------------------------*/
380 /* CLKDIV3 constant definitions. */
381 /*---------------------------------------------------------------------------------------------------------*/
382 #define CLK_CLKDIV3_VSENSE(x) (((x) - 1UL) << CLK_CLKDIV3_VSENSEDIV_Pos) /*!< CLKDIV3 Setting for VSENSE clock divider. It could be 1~256 \hideinitializer */
383 #define CLK_CLKDIV3_SDH1(x) (((x) - 1UL) << CLK_CLKDIV3_SDH1DIV_Pos) /*!< CLKDIV3 Setting for SDH1 clock divider. It could be 1~256 \hideinitializer */
384
385 /*---------------------------------------------------------------------------------------------------------*/
386 /* CLKDIV4 constant definitions. */
387 /*---------------------------------------------------------------------------------------------------------*/
388 #define CLK_CLKDIV4_UART2(x) (((x) - 1UL) << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLKDIV4 Setting for UART2 clock divider. It could be 1~16 \hideinitializer */
389 #define CLK_CLKDIV4_UART3(x) (((x) - 1UL) << CLK_CLKDIV4_UART3DIV_Pos) /*!< CLKDIV4 Setting for UART3 clock divider. It could be 1~16 \hideinitializer */
390 #define CLK_CLKDIV4_UART4(x) (((x) - 1UL) << CLK_CLKDIV4_UART4DIV_Pos) /*!< CLKDIV4 Setting for UART4 clock divider. It could be 1~16 \hideinitializer */
391 #define CLK_CLKDIV4_UART5(x) (((x) - 1UL) << CLK_CLKDIV4_UART5DIV_Pos) /*!< CLKDIV4 Setting for UART5 clock divider. It could be 1~16 \hideinitializer */
392 #define CLK_CLKDIV4_UART6(x) (((x) - 1UL) << CLK_CLKDIV4_UART6DIV_Pos) /*!< CLKDIV4 Setting for UART6 clock divider. It could be 1~16 \hideinitializer */
393 #define CLK_CLKDIV4_UART7(x) (((x) - 1UL) << CLK_CLKDIV4_UART7DIV_Pos) /*!< CLKDIV4 Setting for UART7 clock divider. It could be 1~16 \hideinitializer */
394
395 /*---------------------------------------------------------------------------------------------------------*/
396 /* CLKDIV5 constant definitions. */
397 /*---------------------------------------------------------------------------------------------------------*/
398 #define CLK_CLKDIV5_CANFD0(x) (((x) - 1UL) << CLK_CLKDIV5_CANFD0DIV_Pos) /*!< CLKDIV5 Setting for CANFD0 clock divider. It could be 1~16 \hideinitializer */
399 #define CLK_CLKDIV5_CANFD1(x) (((x) - 1UL) << CLK_CLKDIV5_CANFD1DIV_Pos) /*!< CLKDIV5 Setting for CANFD1 clock divider. It could be 1~16 \hideinitializer */
400 #define CLK_CLKDIV5_CANFD2(x) (((x) - 1UL) << CLK_CLKDIV5_CANFD2DIV_Pos) /*!< CLKDIV5 Setting for CANFD2 clock divider. It could be 1~16 \hideinitializer */
401 #define CLK_CLKDIV5_CANFD3(x) (((x) - 1UL) << CLK_CLKDIV5_CANFD3DIV_Pos) /*!< CLKDIV5 Setting for CANFD3 clock divider. It could be 1~16 \hideinitializer */
402 #define CLK_CLKDIV5_UART8(x) (((x) - 1UL) << CLK_CLKDIV5_UART8DIV_Pos) /*!< CLKDIV5 Setting for UART8 clock divider. It could be 1~16 \hideinitializer */
403 #define CLK_CLKDIV5_UART9(x) (((x) - 1UL) << CLK_CLKDIV5_UART9DIV_Pos) /*!< CLKDIV5 Setting for UART9 clock divider. It could be 1~16 \hideinitializer */
404 #define CLK_CLKDIV5_EADC2(x) (((x) - 1UL) << CLK_CLKDIV5_EADC2DIV_Pos) /*!< CLKDIV5 Setting for EADC2 clock divider. It could be 1~256 \hideinitializer */
405
406 /*---------------------------------------------------------------------------------------------------------*/
407 /* PCLKDIV constant definitions. */
408 /*---------------------------------------------------------------------------------------------------------*/
409 #define CLK_PCLKDIV_PCLK0DIV1 (0x0UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = HCLK \hideinitializer */
410 #define CLK_PCLKDIV_PCLK0DIV2 (0x1UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/2 HCLK \hideinitializer */
411 #define CLK_PCLKDIV_PCLK0DIV4 (0x2UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/4 HCLK \hideinitializer */
412 #define CLK_PCLKDIV_PCLK0DIV8 (0x3UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/8 HCLK \hideinitializer */
413 #define CLK_PCLKDIV_PCLK0DIV16 (0x4UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/16 HCLK \hideinitializer */
414 #define CLK_PCLKDIV_PCLK1DIV1 (0x0UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = HCLK \hideinitializer */
415 #define CLK_PCLKDIV_PCLK1DIV2 (0x1UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/2 HCLK \hideinitializer */
416 #define CLK_PCLKDIV_PCLK1DIV4 (0x2UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/4 HCLK \hideinitializer */
417 #define CLK_PCLKDIV_PCLK1DIV8 (0x3UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/8 HCLK \hideinitializer */
418 #define CLK_PCLKDIV_PCLK1DIV16 (0x4UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/16 HCLK \hideinitializer */
419
420 #define CLK_PCLKDIV_APB0DIV_DIV1 (0x0UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = HCLK \hideinitializer */
421 #define CLK_PCLKDIV_APB0DIV_DIV2 (0x1UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/2 HCLK \hideinitializer */
422 #define CLK_PCLKDIV_APB0DIV_DIV4 (0x2UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/4 HCLK \hideinitializer */
423 #define CLK_PCLKDIV_APB0DIV_DIV8 (0x3UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/8 HCLK \hideinitializer */
424 #define CLK_PCLKDIV_APB0DIV_DIV16 (0x4UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/16 HCLK \hideinitializer */
425 #define CLK_PCLKDIV_APB1DIV_DIV1 (0x0UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = HCLK \hideinitializer */
426 #define CLK_PCLKDIV_APB1DIV_DIV2 (0x1UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/2 HCLK \hideinitializer */
427 #define CLK_PCLKDIV_APB1DIV_DIV4 (0x2UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/4 HCLK \hideinitializer */
428 #define CLK_PCLKDIV_APB1DIV_DIV8 (0x3UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/8 HCLK \hideinitializer */
429 #define CLK_PCLKDIV_APB1DIV_DIV16 (0x4UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/16 HCLK \hideinitializer */
430
431 /*---------------------------------------------------------------------------------------------------------*/
432 /* PLLCTL constant definitions. PLL = FIN * 2 * NF / NR / NO */
433 /*---------------------------------------------------------------------------------------------------------*/
434 #define CLK_PLLCTL_PLLSRC_HXT 0x00000000UL /*!< For PLL clock source is HXT. 4MHz < FIN/NR < 8MHz \hideinitializer */
435 #define CLK_PLLCTL_PLLSRC_HIRC 0x00080000UL /*!< For PLL clock source is HIRC. 4MHz < FIN/NR < 8MHz \hideinitializer */
436
437 #define CLK_PLLCTL_NF(x) (((x)-2UL)) /*!< x must be constant and 2 <= x <= 513. 200MHz < FIN*2*NF/NR < 500MHz. \hideinitializer */
438 #define CLK_PLLCTL_NR(x) (((x)-1UL)<<9) /*!< x must be constant and 1 <= x <= 32. 4MHz < FIN/NR < 8MHz \hideinitializer */
439
440 #define CLK_PLLCTL_NO_1 0x0000UL /*!< For output divider is 1 \hideinitializer */
441 #define CLK_PLLCTL_NO_2 0x4000UL /*!< For output divider is 2 \hideinitializer */
442 #define CLK_PLLCTL_NO_4 0xC000UL /*!< For output divider is 4 \hideinitializer */
443
444 #define CLK_PLLCTL_72MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 36UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 72MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
445 #define CLK_PLLCTL_80MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 80MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
446 #define CLK_PLLCTL_144MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 24UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 144MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
447 #define CLK_PLLCTL_160MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 160MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
448 #define CLK_PLLCTL_180MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 45UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 180MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
449 #define CLK_PLLCTL_192MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 32UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 192MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
450 #define CLK_PLLCTL_200MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 25UL) | CLK_PLLCTL_NO_1) /*!< Predefined PLLCTL setting for 200MHz PLL output with HXT(12MHz X'tal) \hideinitializer */
451
452 #define CLK_PLLCTL_72MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 36UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 72MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
453 #define CLK_PLLCTL_80MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 80MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
454 #define CLK_PLLCTL_144MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 24UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 144MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
455 #define CLK_PLLCTL_160MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 40UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 160MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
456 #define CLK_PLLCTL_180MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 45UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 180MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
457 #define CLK_PLLCTL_192MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 32UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 192MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
458 #define CLK_PLLCTL_200MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF( 25UL) | CLK_PLLCTL_NO_1) /*!< Predefined PLLCTL setting for 200MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
459 #define CLK_PLLCTL_384MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF( 48UL) | CLK_PLLCTL_NO_1) /*!< Predefined PLLCTL setting for 384MHz PLL output with HIRC(12MHz IRC) \hideinitializer */
460
461 /*---------------------------------------------------------------------------------------------------------*/
462 /* PLLFNCTL constant definitions. */
463 /*---------------------------------------------------------------------------------------------------------*/
464 #define CLK_PLLFNCTL1_PLLSRC_HXT 0x00000000UL
465 #define CLK_PLLFNCTL1_PLLSRC_HIRC CLK_PLLFNCTL1_PLLSRC_Msk
466
467 /*---------------------------------------------------------------------------------------------------------*/
468 /* MODULE constant definitions. */
469 /*---------------------------------------------------------------------------------------------------------*/
470 /* APBCLK(31:29)|CLKSEL(28:26)|CLKSEL_Msk(25:22)|CLKSEL_Pos(21:17)|CLKDIV(16:14)|CLKDIV_Msk(13:10)|CLKDIV_Pos(9:5)|IP_EN_Pos(4:0) */
471
472 #define MODULE_APBCLK(x) (((x) >>29) & 0x07UL) /*!< Calculate AHBCLK/APBCLK offset on MODULE index, 0x0:AHBCLK0, 0x1:APBCLK0, 0x2:APBCLK1, 0x3:APBCLK2, 0x4:AHBCLK1 \hideinitializer */
473 #define MODULE_CLKSEL(x) (((x) >>26) & 0x07UL) /*!< Calculate CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3, 0x4:CLKSEL4 \hideinitializer */
474 #define MODULE_CLKSEL_Msk(x) (((x) >>22) & 0x0fUL) /*!< Calculate CLKSEL mask offset on MODULE index \hideinitializer */
475 #define MODULE_CLKSEL_Pos(x) (((x) >>17) & 0x1fUL) /*!< Calculate CLKSEL position offset on MODULE index \hideinitializer */
476 #define MODULE_CLKDIV(x) (((x) >>14) & 0x07UL) /*!< Calculate APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x2:CLKDIV2, 0x3:CLKDIV3, 0x4:CLKDIV4, 0x5:CLKDIV5 \hideinitializer */
477 #define MODULE_CLKDIV_Msk(x) (((x) >>10) & 0x0fUL) /*!< Calculate CLKDIV mask offset on MODULE index \hideinitializer */
478 #define MODULE_CLKDIV_Pos(x) (((x) >>5 ) & 0x1fUL) /*!< Calculate CLKDIV position offset on MODULE index \hideinitializer */
479 #define MODULE_IP_EN_Pos(x) (((x) >>0 ) & 0x1fUL) /*!< Calculate APBCLK offset on MODULE index \hideinitializer */
480 #define MODULE_NoMsk 0x0UL /*!< Not mask on MODULE index \hideinitializer */
481 #define NA MODULE_NoMsk /*!< Not Available \hideinitializer */
482
483 #define MODULE_APBCLK_ENC(x) (((x) & 0x07UL) << 29) /*!< MODULE index, 0x0:AHBCLK0, 0x1:APBCLK0, 0x2:APBCLK1, 0x3:APBCLK2 0x4:AHBCLK1 \hideinitializer */
484 #define MODULE_CLKSEL_ENC(x) (((x) & 0x07UL) << 26) /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3, 0x4:CLKSEL4, 0x5:CLKSEL5 \hideinitializer */
485 #define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x0fUL) << 22) /*!< CLKSEL mask offset on MODULE index \hideinitializer */
486 #define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1fUL) << 17) /*!< CLKSEL position offset on MODULE index \hideinitializer */
487 #define MODULE_CLKDIV_ENC(x) (((x) & 0x07UL) << 14) /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x2:CLKDIV2, 0x3:CLKDIV3, 0x4:CLKDIV4, 0x4:CLKDIV5 \hideinitializer */
488 #define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0x0fUL) << 10) /*!< CLKDIV mask offset on MODULE index \hideinitializer */
489 #define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1fUL) << 5) /*!< CLKDIV position offset on MODULE index \hideinitializer */
490 #define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1fUL) << 0) /*!< AHBCLK/APBCLK offset on MODULE index \hideinitializer */
491
492 /* AHBCLK0 */
493 #define PDMA0_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_PDMA0CKEN_Pos)|\
494 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
495 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PDMA0 Module */
496
497 #define ISP_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_ISPCKEN_Pos)|\
498 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
499 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ISP Module */
500
501 #define EBI_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_EBICKEN_Pos)|\
502 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
503 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EBI Module */
504
505 #define ST_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_STCKEN_Pos)|\
506 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
507 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ST Module */
508
509 #define EMAC0_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_EMAC0CKEN_Pos)|\
510 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC( NA)|MODULE_CLKSEL_Pos_ENC( NA)|\
511 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< EMAC0 Module */
512
513 #define SDH0_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_SDH0CKEN_Pos)|\
514 MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(20UL)|\
515 MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(24UL)) /*!< SDH0 Module */
516
517 #define CRC_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_CRCCKEN_Pos)|\
518 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
519 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CRC Module */
520
521 #define CCAP_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_CCAPCKEN_Pos)|\
522 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
523 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CCAP Module */
524
525 #define SEN_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_SENCKEN_Pos)|\
526 MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(16UL)|\
527 MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 8UL)) /*!< SEN Module */
528
529 #define HSUSBD_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_HSUSBDCKEN_Pos)|\
530 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
531 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< HSUSBD Module */
532
533 #define HBI_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_HBICKEN_Pos)|\
534 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
535 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< HBI Module */
536
537 #define CRPT_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_CRPTCKEN_Pos)|\
538 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
539 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CRPT Module */
540
541 #define KS_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_KSCKEN_Pos)|\
542 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
543 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< KS Module */
544
545 #define SPIM_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_SPIMCKEN_Pos)|\
546 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
547 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPIM Module */
548
549 #define FMCIDLE_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_FMCIDLE_Pos)|\
550 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
551 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< FMCIDLE Module */
552
553 #define USBH_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_USBHCKEN_Pos)|\
554 MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\
555 MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0xFUL)|MODULE_CLKDIV_Pos_ENC( 4UL)) /*!< USBH Module */
556
557 #define SDH1_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_SDH1CKEN_Pos)|\
558 MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(22UL)|\
559 MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(24UL)) /*!< SDH1 Module */
560
561 #define PDMA1_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_PDMA1CKEN_Pos)|\
562 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
563 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PDMA1 Module */
564
565 #define TRACE_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_TRACECKEN_Pos)|\
566 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
567 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TRACE Module */
568
569 #define GPA_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_GPACKEN_Pos)|\
570 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
571 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPA Module */
572
573 #define GPB_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_GPBCKEN_Pos)|\
574 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
575 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPB Module */
576
577 #define GPC_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_GPCCKEN_Pos)|\
578 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
579 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPC Module */
580
581 #define GPD_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_GPDCKEN_Pos)|\
582 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
583 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPD Module */
584
585 #define GPE_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_GPECKEN_Pos)|\
586 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
587 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPE Module */
588
589 #define GPF_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_GPFCKEN_Pos)|\
590 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
591 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPF Module */
592
593 #define GPG_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_GPGCKEN_Pos)|\
594 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
595 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPG Module */
596
597 #define GPH_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK0_GPHCKEN_Pos)|\
598 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
599 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPH Module */
600
601 /* AHBCLK1 */
602 #define CANFD0_MODULE (MODULE_APBCLK_ENC( 4UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK1_CANFD0CKEN_Pos)|\
603 MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(24UL)|\
604 MODULE_CLKDIV_ENC( 5UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 0UL)) /*!< CANFD0 Module */
605
606 #define CANFD1_MODULE (MODULE_APBCLK_ENC( 4UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK1_CANFD1CKEN_Pos)|\
607 MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(26UL)|\
608 MODULE_CLKDIV_ENC( 5UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 4UL)) /*!< CANFD1 Module */
609
610 #define CANFD2_MODULE (MODULE_APBCLK_ENC( 4UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK1_CANFD2CKEN_Pos)|\
611 MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(28UL)|\
612 MODULE_CLKDIV_ENC( 5UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 8UL)) /*!< CANFD2 Module */
613
614 #define CANFD3_MODULE (MODULE_APBCLK_ENC( 4UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK1_CANFD3CKEN_Pos)|\
615 MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(30UL)|\
616 MODULE_CLKDIV_ENC( 5UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(12UL)) /*!< CANFD3 Module */
617
618 #define GPI_MODULE (MODULE_APBCLK_ENC( 4UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK1_GPICKEN_Pos)|\
619 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
620 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPI Module */
621
622 #define GPJ_MODULE (MODULE_APBCLK_ENC( 4UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK1_GPJCKEN_Pos)|\
623 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
624 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< GPJ Module */
625
626 #define BMC_MODULE (MODULE_APBCLK_ENC( 4UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK1_BMCCKEN_Pos)|\
627 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
628 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< BMC Module */
629
630 /* APBCLK0 */
631 #define WDT_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_WDTCKEN_Pos)|\
632 MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 0UL)|\
633 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< WDT Module */
634
635 #define WWDT_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_WDTCKEN_Pos)|\
636 MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(30UL)|\
637 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< WWDT Module */
638
639 #define RTC_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_RTCCKEN_Pos)|\
640 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC( NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
641 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< RTC Module */
642
643 #define TMR0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR0CKEN_Pos)|\
644 MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\
645 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR0 Module */
646
647 #define TMR1_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR1CKEN_Pos) |\
648 MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\
649 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR1 Module */
650
651 #define TMR2_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR2CKEN_Pos) |\
652 MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(16UL)|\
653 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR2 Module */
654
655 #define TMR3_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR3CKEN_Pos) |\
656 MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(20UL)|\
657 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR3 Module */
658
659 #define CLKO_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_CLKOCKEN_Pos) |\
660 MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC( 4UL)|\
661 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< CLKO Module */
662
663 #define ACMP01_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_ACMP01CKEN_Pos) |\
664 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
665 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ACMP01 Module */
666
667 #define I2C0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2C0CKEN_Pos) |\
668 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
669 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C0 Module */
670
671 #define I2C1_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2C1CKEN_Pos) |\
672 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
673 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C1 Module */
674
675 #define I2C2_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2C2CKEN_Pos) |\
676 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
677 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C2 Module */
678
679 #define I2C3_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2C3CKEN_Pos) |\
680 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
681 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C3 Module */
682
683 #define QSPI0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_QSPI0CKEN_Pos) |\
684 MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 2UL)|\
685 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< QSPI0 Module */
686
687 #define SPI0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_SPI0CKEN_Pos) |\
688 MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC( 4UL)|\
689 MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< SPI0 Module */
690
691 #define SPI1_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_SPI1CKEN_Pos) |\
692 MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\
693 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< SPI1 Module */
694
695 #define SPI2_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_SPI2CKEN_Pos) |\
696 MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC( 9UL)|\
697 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< SPI2 Module */
698
699 #define UART0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART0CKEN_Pos)|\
700 MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(24UL)|\
701 MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 8UL)) /*!< UART0 Module */
702
703 #define UART1_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART1CKEN_Pos)|\
704 MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(26UL)|\
705 MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(12UL)) /*!< UART1 Module */
706
707 #define UART2_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART2CKEN_Pos)|\
708 MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(24UL)|\
709 MODULE_CLKDIV_ENC( 4UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 0UL)) /*!< UART2 Module */
710
711 #define UART3_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART3CKEN_Pos)|\
712 MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(26UL)|\
713 MODULE_CLKDIV_ENC( 4UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 4UL)) /*!< UART3 Module */
714
715 #define UART4_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART4CKEN_Pos)|\
716 MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(28UL)|\
717 MODULE_CLKDIV_ENC( 4UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 8UL)) /*!< UART4 Module */
718
719 #define UART5_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART5CKEN_Pos)|\
720 MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(30UL)|\
721 MODULE_CLKDIV_ENC( 4UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(12UL)) /*!< UART5 Module */
722
723 #define UART6_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART6CKEN_Pos)|\
724 MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(20UL)|\
725 MODULE_CLKDIV_ENC( 4UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(16UL)) /*!< UART6 Module */
726
727 #define UART7_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART7CKEN_Pos)|\
728 MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(22UL)|\
729 MODULE_CLKDIV_ENC( 4UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(20UL)) /*!< UART7 Module */
730
731 #define OTG_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_OTGCKEN_Pos)|\
732 MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\
733 MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0xFUL)|MODULE_CLKDIV_Pos_ENC( 4UL)) /*!< OTG Module */
734
735 #define USBD_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_USBDCKEN_Pos)|\
736 MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\
737 MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0xFUL)|MODULE_CLKDIV_Pos_ENC( 4UL)) /*!< USBD Module */
738
739 #define EADC0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_EADC0CKEN_Pos)|\
740 MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(10UL)|\
741 MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(16UL)) /*!< EADC0 Module */
742
743 #define I2S0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2S0CKEN_Pos)|\
744 MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(16UL)|\
745 MODULE_CLKDIV_ENC( 2UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 0UL)) /*!< I2S0 Module */
746
747 #define HSOTG_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_HSOTGCKEN_Pos)|\
748 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
749 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< HSOTG Module */
750
751 /* APBCLK1 */
752 #define SC0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SC0CKEN_Pos) |\
753 MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 0UL)|\
754 MODULE_CLKDIV_ENC( 1UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 0UL)) /*!< SC0 Module */
755
756 #define SC1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SC1CKEN_Pos) |\
757 MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 2UL)|\
758 MODULE_CLKDIV_ENC( 1UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 8UL)) /*!< SC1 Module */
759
760 #define SC2_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SC2CKEN_Pos) |\
761 MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 4UL)|\
762 MODULE_CLKDIV_ENC( 1UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(16UL)) /*!< SC2 Module */
763
764 #define I2C4_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_I2C4CKEN_Pos)|\
765 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
766 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C4 Module */
767
768 #define QSPI1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_QSPI1CKEN_Pos)|\
769 MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(10UL)|\
770 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< QSPI1 Module */
771
772 #define SPI3_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SPI3CKEN_Pos)|\
773 MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\
774 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI3 Module */
775
776 #define SPI4_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SPI4CKEN_Pos)|\
777 MODULE_CLKSEL_ENC( 4UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC( 0UL)|\
778 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI4 Module */
779
780 #define USCI0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_USCI0CKEN_Pos)|\
781 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
782 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< USCI0 Module */
783
784 #define PSIO_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_PSIOCKEN_Pos)|\
785 MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(28UL)|\
786 MODULE_CLKDIV_ENC( 1UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(24UL)) /*!< PSIO Module */
787
788 #define DAC_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_DACCKEN_Pos)|\
789 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
790 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< DAC Module */
791
792 #define ECAP2_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_ECAP2CKEN_Pos)|\
793 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
794 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ECAP2 Module */
795
796 #define ECAP3_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_ECAP3CKEN_Pos)|\
797 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
798 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ECAP3 Module */
799
800 #define EPWM0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EPWM0CKEN_Pos)|\
801 MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 0UL)|\
802 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EPWM0 Module */
803
804 #define EPWM1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EPWM1CKEN_Pos)|\
805 MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 1UL)|\
806 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EPWM1 Module */
807
808 #define BPWM0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_BPWM0CKEN_Pos)|\
809 MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\
810 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< BPWM0 Module */
811
812 #define BPWM1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_BPWM1CKEN_Pos)|\
813 MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 9UL)|\
814 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< BPWM1 Module */
815
816 #define EQEI0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EQEI0CKEN_Pos)|\
817 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
818 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EQEI0 Module */
819
820 #define EQEI1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EQEI1CKEN_Pos)|\
821 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
822 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EQEI1 Module */
823
824 #define EQEI2_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EQEI2CKEN_Pos)|\
825 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
826 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EQEI2 Module */
827
828 #define EQEI3_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EQEI3CKEN_Pos)|\
829 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
830 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EQEI3 Module */
831
832 #define TRNG_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_TRNGCKEN_Pos)|\
833 MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC(27UL)|\
834 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TRNG Module */
835
836 #define ECAP0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_ECAP0CKEN_Pos)|\
837 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
838 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ECAP0 Module */
839
840 #define ECAP1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_ECAP1CKEN_Pos)|\
841 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
842 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ECAP1 Module */
843
844 #define I2S1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_I2S1CKEN_Pos)|\
845 MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(16UL)|\
846 MODULE_CLKDIV_ENC( 2UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 4UL)) /*!< I2S1 Module */
847
848 #define EADC1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EADC1CKEN_Pos)|\
849 MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\
850 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EADC1 Module */
851
852 /* APBCLK2 */
853 #define KPI_MODULE (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_KPICKEN_Pos) |\
854 MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 6UL)|\
855 MODULE_CLKDIV_ENC( 2UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 8UL)) /*!< KPI Module */
856
857 #define EADC2_MODULE (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_EADC2CKEN_Pos)|\
858 MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(14UL)|\
859 MODULE_CLKDIV_ENC( 2UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(24UL)) /*!< EADC2 Module */
860
861 #define ACMP23_MODULE (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_ACMP23CKEN_Pos) |\
862 MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
863 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ACMP23 Module */
864
865 #define SPI5_MODULE (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_SPI5CKEN_Pos)|\
866 MODULE_CLKSEL_ENC( 4UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC( 4UL)|\
867 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI5 Module */
868
869 #define SPI6_MODULE (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_SPI6CKEN_Pos)|\
870 MODULE_CLKSEL_ENC( 4UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\
871 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI6 Module */
872
873 #define SPI7_MODULE (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_SPI7CKEN_Pos)|\
874 MODULE_CLKSEL_ENC( 4UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\
875 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI7 Module */
876
877 #define SPI8_MODULE (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_SPI8CKEN_Pos)|\
878 MODULE_CLKSEL_ENC( 4UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(16UL)|\
879 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI8 Module */
880
881 #define SPI9_MODULE (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_SPI9CKEN_Pos)|\
882 MODULE_CLKSEL_ENC( 4UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(20UL)|\
883 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI9 Module */
884
885 #define SPI10_MODULE (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_SPI10CKEN_Pos)|\
886 MODULE_CLKSEL_ENC( 4UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(24UL)|\
887 MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI10 Module */
888
889 #define UART8_MODULE (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_UART8CKEN_Pos)|\
890 MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(20UL)|\
891 MODULE_CLKDIV_ENC( 5UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(16UL)) /*!< UART8 Module */
892
893 #define UART9_MODULE (MODULE_APBCLK_ENC( 3UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK2_UART9CKEN_Pos)|\
894 MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(22UL)|\
895 MODULE_CLKDIV_ENC( 5UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(20UL)) /*!< UART9 Module */
896
897
898 /*---------------------------------------------------------------------------------------------------------*/
899 /* PDMSEL constant definitions. */
900 /*---------------------------------------------------------------------------------------------------------*/
901 #define CLK_PMUCTL_PDMSEL_PD (0x0UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Power-down mode \hideinitializer */
902 #define CLK_PMUCTL_PDMSEL_LLPD (0x1UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Low leakage Power-down mode \hideinitializer */
903 #define CLK_PMUCTL_PDMSEL_FWPD (0x2UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Fast wake-up Power-down mode \hideinitializer */
904 #define CLK_PMUCTL_PDMSEL_SPD (0x4UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Standby Power-down mode \hideinitializer */
905 #define CLK_PMUCTL_PDMSEL_DPD (0x6UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mode is Deep Power-down mode \hideinitializer */
906
907 /*---------------------------------------------------------------------------------------------------------*/
908 /* WKTMRIS constant definitions. */
909 /*---------------------------------------------------------------------------------------------------------*/
910 #define CLK_PMUCTL_WKTMRIS_128 (0x0UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 128 OSC10K clocks (12.8 ms) \hideinitializer */
911 #define CLK_PMUCTL_WKTMRIS_256 (0x1UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 256 OSC10K clocks (25.6 ms) \hideinitializer */
912 #define CLK_PMUCTL_WKTMRIS_512 (0x2UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 512 OSC10K clocks (51.2 ms) \hideinitializer */
913 #define CLK_PMUCTL_WKTMRIS_1024 (0x3UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 1024 OSC10K clocks (102.4ms) \hideinitializer */
914 #define CLK_PMUCTL_WKTMRIS_4096 (0x4UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 4096 OSC10K clocks (409.6ms) \hideinitializer */
915 #define CLK_PMUCTL_WKTMRIS_8192 (0x5UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 8192 OSC10K clocks (819.2ms) \hideinitializer */
916 #define CLK_PMUCTL_WKTMRIS_16384 (0x6UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 16384 OSC10K clocks (1638.4ms) \hideinitializer */
917 #define CLK_PMUCTL_WKTMRIS_65536 (0x7UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 65536 OSC10K clocks (6553.6ms) \hideinitializer */
918 #define CLK_PMUCTL_WKTMRIS_131072 (0x8UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 131072 OSC10K clocks (13107.2 ms) \hideinitializer */
919 #define CLK_PMUCTL_WKTMRIS_262144 (0x9UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 262144 OSC10K clocks (26214.4 ms) \hideinitializer */
920 #define CLK_PMUCTL_WKTMRIS_524288 (0xaUL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 524288 OSC10K clocks (52428.8ms) \hideinitializer */
921 #define CLK_PMUCTL_WKTMRIS_1048576 (0xbUL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 1048576 OSC10K clocks (104857.6ms) \hideinitializer */
922
923 /*---------------------------------------------------------------------------------------------------------*/
924 /* SWKDBCLKSEL constant definitions. */
925 /*---------------------------------------------------------------------------------------------------------*/
926 #define CLK_SWKDBCTL_SWKDBCLKSEL_1 (0x0UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 1 clocks \hideinitializer */
927 #define CLK_SWKDBCTL_SWKDBCLKSEL_2 (0x1UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2 clocks \hideinitializer */
928 #define CLK_SWKDBCTL_SWKDBCLKSEL_4 (0x2UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4 clocks \hideinitializer */
929 #define CLK_SWKDBCTL_SWKDBCLKSEL_8 (0x3UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8 clocks \hideinitializer */
930 #define CLK_SWKDBCTL_SWKDBCLKSEL_16 (0x4UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16 clocks \hideinitializer */
931 #define CLK_SWKDBCTL_SWKDBCLKSEL_32 (0x5UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32 clocks \hideinitializer */
932 #define CLK_SWKDBCTL_SWKDBCLKSEL_64 (0x6UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64 clocks \hideinitializer */
933 #define CLK_SWKDBCTL_SWKDBCLKSEL_128 (0x7UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128 clocks \hideinitializer */
934 #define CLK_SWKDBCTL_SWKDBCLKSEL_256 (0x8UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 256 clocks \hideinitializer */
935 #define CLK_SWKDBCTL_SWKDBCLKSEL_2x256 (0x9UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2x256 clocks \hideinitializer */
936 #define CLK_SWKDBCTL_SWKDBCLKSEL_4x256 (0xaUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4x256 clocks \hideinitializer */
937 #define CLK_SWKDBCTL_SWKDBCLKSEL_8x256 (0xbUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8x256 clocks \hideinitializer */
938 #define CLK_SWKDBCTL_SWKDBCLKSEL_16x256 (0xcUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16x256 clocks \hideinitializer */
939 #define CLK_SWKDBCTL_SWKDBCLKSEL_32x256 (0xdUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32x256 clocks \hideinitializer */
940 #define CLK_SWKDBCTL_SWKDBCLKSEL_64x256 (0xeUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64x256 clocks \hideinitializer */
941 #define CLK_SWKDBCTL_SWKDBCLKSEL_128x256 (0xfUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128x256 clocks \hideinitializer */
942
943 /*---------------------------------------------------------------------------------------------------------*/
944 /* DPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */
945 /*---------------------------------------------------------------------------------------------------------*/
946 #define CLK_DPDWKPIN0_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN0_Pos) /*!< Disable Wake-up pin0 (GPC.0) at Deep Power-down mode \hideinitializer */
947 #define CLK_DPDWKPIN0_RISING (0x1UL << CLK_PMUCTL_WKPINEN0_Pos) /*!< Enable Wake-up pin0 (GPC.0) rising edge at Deep Power-down mode \hideinitializer */
948 #define CLK_DPDWKPIN0_FALLING (0x2UL << CLK_PMUCTL_WKPINEN0_Pos) /*!< Enable Wake-up pin0 (GPC.0) falling edge at Deep Power-down mode \hideinitializer */
949 #define CLK_DPDWKPIN0_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN0_Pos) /*!< Enable Wake-up pin0 (GPC.0) both edge at Deep Power-down mode \hideinitializer */
950
951 #define CLK_DPDWKPIN1_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Disable Wake-up pin1 (GPB.0) at Deep Power-down mode \hideinitializer */
952 #define CLK_DPDWKPIN1_RISING (0x1UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Enable Wake-up pin1 (GPB.0) rising edge at Deep Power-down mode \hideinitializer */
953 #define CLK_DPDWKPIN1_FALLING (0x2UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Enable Wake-up pin1 (GPB.0) falling edge at Deep Power-down mode \hideinitializer */
954 #define CLK_DPDWKPIN1_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN1_Pos) /*!< Enable Wake-up pin1 (GPB.0) both edge at Deep Power-down mode \hideinitializer */
955
956 #define CLK_DPDWKPIN2_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Disable Wake-up pin2 (GPB.2) at Deep Power-down mode \hideinitializer */
957 #define CLK_DPDWKPIN2_RISING (0x1UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Enable Wake-up pin2 (GPB.2) rising edge at Deep Power-down mode \hideinitializer */
958 #define CLK_DPDWKPIN2_FALLING (0x2UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Enable Wake-up pin2 (GPB.2) falling edge at Deep Power-down mode \hideinitializer */
959 #define CLK_DPDWKPIN2_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN2_Pos) /*!< Enable Wake-up pin2 (GPB.2) both edge at Deep Power-down mode \hideinitializer */
960
961 #define CLK_DPDWKPIN3_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Disable Wake-up pin3 (GPB.12) at Deep Power-down mode \hideinitializer */
962 #define CLK_DPDWKPIN3_RISING (0x1UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Enable Wake-up pin3 (GPB.12) rising edge at Deep Power-down mode \hideinitializer */
963 #define CLK_DPDWKPIN3_FALLING (0x2UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Enable Wake-up pin3 (GPB.12) falling edge at Deep Power-down mode \hideinitializer */
964 #define CLK_DPDWKPIN3_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN3_Pos) /*!< Enable Wake-up pin3 (GPB.12) both edge at Deep Power-down mode \hideinitializer */
965
966 #define CLK_DPDWKPIN4_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Disable Wake-up pin4 (GPF.6) at Deep Power-down mode \hideinitializer */
967 #define CLK_DPDWKPIN4_RISING (0x1UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Enable Wake-up pin4 (GPF.6) rising edge at Deep Power-down mode \hideinitializer */
968 #define CLK_DPDWKPIN4_FALLING (0x2UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Enable Wake-up pin4 (GPF.6) falling edge at Deep Power-down mode \hideinitializer */
969 #define CLK_DPDWKPIN4_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN4_Pos) /*!< Enable Wake-up pin4 (GPF.6) both edge at Deep Power-down mode \hideinitializer */
970
971 /*---------------------------------------------------------------------------------------------------------*/
972 /* SPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */
973 /*---------------------------------------------------------------------------------------------------------*/
974 #define CLK_SPDWKPIN_ENABLE (0x1UL << 0) /*!< Enable Standby Power-down Pin Wake-up \hideinitializer */
975 #define CLK_SPDWKPIN_RISING (0x1UL << 1) /*!< Standby Power-down Wake-up on Standby Power-down Pin rising edge \hideinitializer */
976 #define CLK_SPDWKPIN_FALLING (0x1UL << 2) /*!< Standby Power-down Wake-up on Standby Power-down Pin falling edge \hideinitializer */
977 #define CLK_SPDWKPIN_DEBOUNCEEN (0x1UL << 8) /*!< Enable Standby power-down pin De-bounce function \hideinitializer */
978 #define CLK_SPDWKPIN_DEBOUNCEDIS (0x0UL << 8) /*!< Disable Standby power-down pin De-bounce function \hideinitializer */
979
980 #define CLK_SPDSRETSEL_NO (0x0UL << CLK_PMUCTL_SRETSEL_Pos) /*!< No SRAM retention when chip enter SPD mode \hideinitializer */
981 #define CLK_SPDSRETSEL_16K (0x1UL << CLK_PMUCTL_SRETSEL_Pos) /*!< 16K SRAM retention when chip enter SPD mode \hideinitializer */
982 #define CLK_SPDSRETSEL_32K (0x2UL << CLK_PMUCTL_SRETSEL_Pos) /*!< 32K SRAM retention when chip enter SPD mode \hideinitializer */
983 #define CLK_SPDSRETSEL_64K (0x3UL << CLK_PMUCTL_SRETSEL_Pos) /*!< 64K SRAM retention when chip enter SPD mode \hideinitializer */
984 #define CLK_SPDSRETSEL_128K (0x4UL << CLK_PMUCTL_SRETSEL_Pos) /*!< 128K SRAM retention when chip enter SPD mode \hideinitializer */
985 #define CLK_SPDSRETSEL_256K (0x5UL << CLK_PMUCTL_SRETSEL_Pos) /*!< 256K SRAM retention when chip enter SPD mode \hideinitializer */
986
987
988 /*@}*/ /* end of group CLK_EXPORTED_CONSTANTS */
989
990 /** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions
991 @{
992 */
993
994 /**
995 * @brief Disable Wake-up Timer
996 * @param None
997 * @return None
998 * @details This macro disables Wake-up timer at Standby or Deep Power-down mode.
999 */
1000 #define CLK_DISABLE_WKTMR() (CLK->PMUCTL &= ~CLK_PMUCTL_WKTMREN_Msk)
1001
1002 /**
1003 * @brief Enable Wake-up Timer
1004 * @param None
1005 * @return None
1006 * @details This macro enables Wake-up timer at Standby or Deep Power-down mode.
1007 */
1008 #define CLK_ENABLE_WKTMR() (CLK->PMUCTL |= CLK_PMUCTL_WKTMREN_Msk)
1009
1010 /**
1011 * @brief Disable DPD Mode Wake-up Pin 0
1012 * @param None
1013 * @return None
1014 * @details This macro disables Wake-up pin 0 (GPC.0) at Deep Power-down mode.
1015 */
1016 #define CLK_DISABLE_DPDWKPIN0() (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN0_Msk)
1017
1018 /**
1019 * @brief Disable DPD Mode Wake-up Pin 1
1020 * @param None
1021 * @return None
1022 * @details This macro disables Wake-up pin 1 (GPB.0) at Deep Power-down mode.
1023 */
1024 #define CLK_DISABLE_DPDWKPIN1() (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN1_Msk)
1025
1026 /**
1027 * @brief Disable DPD Mode Wake-up Pin 2
1028 * @param None
1029 * @return None
1030 * @details This macro disables Wake-up pin 2 (GPB.2) at Deep Power-down mode.
1031 */
1032 #define CLK_DISABLE_DPDWKPIN2() (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN2_Msk)
1033
1034 /**
1035 * @brief Disable DPD Mode Wake-up Pin 3
1036 * @param None
1037 * @return None
1038 * @details This macro disables Wake-up pin 3 (GPB.12) at Deep Power-down mode.
1039 */
1040 #define CLK_DISABLE_DPDWKPIN3() (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN3_Msk)
1041
1042 /**
1043 * @brief Disable DPD Mode Wake-up Pin 4
1044 * @param None
1045 * @return None
1046 * @details This macro disables Wake-up pin 4 (GPF.6) at Deep Power-down mode.
1047 */
1048 #define CLK_DISABLE_DPDWKPIN4() (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN4_Msk)
1049
1050 /**
1051 * @brief Disable SPD Mode ACMP Wake-up
1052 * @param None
1053 * @return None
1054 * @details This macro disables ACMP wake-up at Standby Power-down mode.
1055 */
1056 #define CLK_DISABLE_SPDACMP() (CLK->PMUCTL &= ~CLK_PMUCTL_ACMPSPWK_Msk)
1057
1058 /**
1059 * @brief Enable SPD Mode ACMP Wake-up
1060 * @param None
1061 * @return None
1062 * @details This macro enables ACMP wake-up at Standby Power-down mode.
1063 */
1064 #define CLK_ENABLE_SPDACMP() (CLK->PMUCTL |= CLK_PMUCTL_ACMPSPWK_Msk)
1065
1066 /**
1067 * @brief Disable SPD and DPD Mode RTC Wake-up
1068 * @param None
1069 * @return None
1070 * @details This macro disables RTC Wake-up at Standby or Deep Power-down mode.
1071 */
1072 #define CLK_DISABLE_RTCWK() (CLK->PMUCTL &= ~CLK_PMUCTL_RTCWKEN_Msk)
1073
1074 /**
1075 * @brief Enable SPD and DPD Mode RTC Wake-up
1076 * @param None
1077 * @return None
1078 * @details This macro enables RTC Wake-up at Standby or Deep Power-down mode.
1079 */
1080 #define CLK_ENABLE_RTCWK() (CLK->PMUCTL |= CLK_PMUCTL_RTCWKEN_Msk)
1081
1082 /**
1083 * @brief Set Wake-up Timer Time-out Interval
1084 *
1085 * @param[in] u32Interval The Wake-up Timer Time-out Interval selection. It could be
1086 * - \ref CLK_PMUCTL_WKTMRIS_128
1087 * - \ref CLK_PMUCTL_WKTMRIS_256
1088 * - \ref CLK_PMUCTL_WKTMRIS_512
1089 * - \ref CLK_PMUCTL_WKTMRIS_1024
1090 * - \ref CLK_PMUCTL_WKTMRIS_4096
1091 * - \ref CLK_PMUCTL_WKTMRIS_8192
1092 * - \ref CLK_PMUCTL_WKTMRIS_16384
1093 * - \ref CLK_PMUCTL_WKTMRIS_65536
1094 * - \ref CLK_PMUCTL_WKTMRIS_131072
1095 * - \ref CLK_PMUCTL_WKTMRIS_262144
1096 * - \ref CLK_PMUCTL_WKTMRIS_524288
1097 * - \ref CLK_PMUCTL_WKTMRIS_1048576
1098 *
1099 * @return None
1100 *
1101 * @details This function set Wake-up Timer Time-out Interval.
1102 *
1103 * \hideinitializer
1104 */
1105 #define CLK_SET_WKTMR_INTERVAL(u32Interval) CLK->PMUCTL = (CLK->PMUCTL & (~CLK_PMUCTL_WKTMRIS_Msk)) | (u32Interval)
1106
1107 /**
1108 * @brief Set De-bounce Sampling Cycle Time
1109 *
1110 * @param[in] u32CycleSel The de-bounce sampling cycle selection. It could be
1111 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_1
1112 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2
1113 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4
1114 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8
1115 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16
1116 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32
1117 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64
1118 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128
1119 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_256
1120 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2x256
1121 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4x256
1122 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8x256
1123 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16x256
1124 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32x256
1125 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64x256
1126 * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128x256
1127 *
1128 * @return None
1129 *
1130 * @details This function set De-bounce Sampling Cycle Time for Standby Power-down pin wake-up.
1131 *
1132 * \hideinitializer
1133 */
1134 #define CLK_SET_SPDDEBOUNCETIME(u32CycleSel) (CLK->SWKDBCTL = (u32CycleSel))
1135
1136 /*---------------------------------------------------------------------------------------------------------*/
1137 /* static inline functions */
1138 /*---------------------------------------------------------------------------------------------------------*/
1139 /* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
1140 __STATIC_INLINE void CLK_SysTickDelay(uint32_t us);
1141 __STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us);
1142
1143 /**
1144 * @brief This function execute delay function.
1145 * @param[in] us Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex:
1146 * 200MHz => 83886us, 180MHz => 93206us ...
1147 * @return None
1148 * @details Use the SysTick to generate the delay time and the unit is in us.
1149 * The SysTick clock source is from HCLK, i.e the same as system core clock.
1150 * User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function.
1151 */
CLK_SysTickDelay(uint32_t us)1152 __STATIC_INLINE void CLK_SysTickDelay(uint32_t us)
1153 {
1154 SysTick->LOAD = us * CyclesPerUs;
1155 SysTick->VAL = 0x0UL;
1156 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
1157
1158 /* Waiting for down-count to zero */
1159 while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL)
1160 {
1161 }
1162
1163 /* Disable SysTick counter */
1164 SysTick->CTRL = 0UL;
1165 }
1166
1167 /**
1168 * @brief This function execute long delay function.
1169 * @param[in] us Delay time.
1170 * @return None
1171 * @details Use the SysTick to generate the long delay time and the UNIT is in us.
1172 * The SysTick clock source is from HCLK, i.e the same as system core clock.
1173 * User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function.
1174 */
CLK_SysTickLongDelay(uint32_t us)1175 __STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us)
1176 {
1177 uint32_t u32Delay;
1178
1179 /* It should <= 65536us for each delay loop */
1180 u32Delay = 65536UL;
1181
1182 do
1183 {
1184 if(us > u32Delay)
1185 {
1186 us -= u32Delay;
1187 }
1188 else
1189 {
1190 u32Delay = us;
1191 us = 0UL;
1192 }
1193
1194 SysTick->LOAD = u32Delay * CyclesPerUs;
1195 SysTick->VAL = (0x0UL);
1196 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
1197
1198 /* Waiting for down-count to zero */
1199 while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL);
1200
1201 /* Disable SysTick counter */
1202 SysTick->CTRL = 0UL;
1203 }while(us > 0UL);
1204 }
1205
1206
1207 void CLK_DisableCKO(void);
1208 void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
1209 void CLK_PowerDown(void);
1210 void CLK_Idle(void);
1211 uint32_t CLK_GetHXTFreq(void);
1212 uint32_t CLK_GetLXTFreq(void);
1213 uint32_t CLK_GetHCLKFreq(void);
1214 uint32_t CLK_GetPCLK0Freq(void);
1215 uint32_t CLK_GetPCLK1Freq(void);
1216 uint32_t CLK_GetCPUFreq(void);
1217 uint32_t CLK_SetCoreClock(uint32_t u32Hclk);
1218 void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
1219 void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
1220 void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc);
1221 void CLK_EnableXtalRC(uint32_t u32ClkMask);
1222 void CLK_DisableXtalRC(uint32_t u32ClkMask);
1223 void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
1224 void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
1225 uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
1226 void CLK_DisablePLL(void);
1227 uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
1228 void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);
1229 void CLK_DisableSysTick(void);
1230 void CLK_SetPowerDownMode(uint32_t u32PDMode);
1231 void CLK_EnableDPDWKPin(uint32_t u32TriggerType);
1232 uint32_t CLK_GetPMUWKSrc(void);
1233 void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn);
1234 uint32_t CLK_GetPLLClockFreq(void);
1235 uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx);
1236 uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx);
1237 void CLK_DisablePLLFN(void);
1238 uint32_t CLK_EnablePLLFN(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
1239 uint32_t CLK_GetPLLFNClockFreq(void);
1240
1241 /*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */
1242
1243 /*@}*/ /* end of group CLK_Driver */
1244
1245 /*@}*/ /* end of group Standard_Driver */
1246
1247 #ifdef __cplusplus
1248 }
1249 #endif
1250
1251 #endif /* __CLK_H__ */
1252
