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Searched refs:uint8_t (Results 1 – 25 of 384) sorted by relevance

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/hal_microchip-latest/mpfs/mpfs_hal/common/
Dmss_plic.h44 uint8_t Invalid_IRQHandler(void);
45 uint8_t l2_metadata_corr_IRQHandler(void);
46 uint8_t l2_metadata_uncorr_IRQHandler(void);
47 uint8_t l2_data_corr_IRQHandler(void);
48 uint8_t l2_data_uncorr_IRQHandler(void);
49 uint8_t dma_ch0_DONE_IRQHandler(void);
50 uint8_t dma_ch0_ERR_IRQHandler(void);
51 uint8_t dma_ch1_DONE_IRQHandler(void);
52 uint8_t dma_ch1_ERR_IRQHandler(void);
53 uint8_t dma_ch2_DONE_IRQHandler(void);
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Dmss_irq_handler_stubs.c81 __attribute__((weak)) uint8_t Invalid_IRQHandler(void) in Invalid_IRQHandler()
86 __attribute__((weak)) uint8_t External_1_IRQHandler(void) in External_1_IRQHandler()
91 __attribute__((weak)) uint8_t External_2_IRQHandler(void) in External_2_IRQHandler()
96 __attribute__((weak)) uint8_t External_3_IRQHandler(void) in External_3_IRQHandler()
101 __attribute__((weak)) uint8_t USART0_plic_4_IRQHandler(void) in USART0_plic_4_IRQHandler()
106 __attribute__((weak)) uint8_t External_5_IRQHandler(void) in External_5_IRQHandler()
111 __attribute__((weak)) uint8_t External_6_IRQHandler(void) in External_6_IRQHandler()
116 __attribute__((weak)) uint8_t External_7_IRQHandler(void) in External_7_IRQHandler()
121 __attribute__((weak)) uint8_t External_8_IRQHandler(void) in External_8_IRQHandler()
126 __attribute__((weak)) uint8_t External_9_IRQHandler(void) in External_9_IRQHandler()
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/hal_microchip-latest/pic32c/pic32cxsg/include/fixups/component/
Ddac_component_fixup_pic32cxsg.h14 uint8_t SWRST:1; /*!< bit: 0 Software Reset */
15 uint8_t ENABLE:1; /*!< bit: 1 Enable DAC Controller */
16 uint8_t :6; /*!< bit: 2.. 7 Reserved */
18 uint8_t reg; /*!< Type used for register access */
26 uint8_t DIFF:1; /*!< bit: 0 Differential mode enable */
27 uint8_t REFSEL:2; /*!< bit: 1.. 2 Reference Selection for DAC0/1 */
28 uint8_t :5; /*!< bit: 3.. 7 Reserved */
30 uint8_t reg; /*!< Type used for register access */
38 uint8_t STARTEI0:1; /*!< bit: 0 Start Conversion Event Input DAC 0 */
39 uint8_t STARTEI1:1; /*!< bit: 1 Start Conversion Event Input DAC 1 */
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Dusb_component_fixup_pic32cxsg.h49 uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
50 uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
51 uint8_t :6; /*!< bit: 2.. 7 Reserved */
53 uint8_t reg; /*!< Type used for register access */
96 uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */
97 uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */
98 uint8_t :6; /*!< bit: 2.. 7 Reserved */
100 uint8_t reg; /*!< Type used for register access */
137 uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */
138 uint8_t :1; /*!< bit: 3 Reserved */
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Dac_component_fixup_pic32cxsg.h14 uint8_t SWRST:1; /*!< bit: 0 Software Reset */
15 uint8_t ENABLE:1; /*!< bit: 1 Enable */
16 uint8_t :6; /*!< bit: 2.. 7 Reserved */
18 uint8_t reg; /*!< Type used for register access */
26 uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */
27 uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */
28 uint8_t :6; /*!< bit: 2.. 7 Reserved */
31 uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */
32 uint8_t :6; /*!< bit: 2.. 7 Reserved */
34 uint8_t reg; /*!< Type used for register access */
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Dtc_component_fixup_pic32cxsg.h49 uint8_t DIR:1; /*!< bit: 0 Counter Direction */
50 uint8_t LUPD:1; /*!< bit: 1 Lock Update */
51 uint8_t ONESHOT:1; /*!< bit: 2 One-Shot on Counter */
52 uint8_t :2; /*!< bit: 3.. 4 Reserved */
53 uint8_t CMD:3; /*!< bit: 5.. 7 Command */
55 uint8_t reg; /*!< Type used for register access */
63 uint8_t DIR:1; /*!< bit: 0 Counter Direction */
64 uint8_t LUPD:1; /*!< bit: 1 Lock Update */
65 uint8_t ONESHOT:1; /*!< bit: 2 One-Shot on Counter */
66 uint8_t :2; /*!< bit: 3.. 4 Reserved */
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Dpdec_component_fixup_pic32cxsg.h52 uint8_t :1; /*!< bit: 0 Reserved */
53 uint8_t LUPD:1; /*!< bit: 1 Lock Update */
54 uint8_t :3; /*!< bit: 2.. 4 Reserved */
55 uint8_t CMD:3; /*!< bit: 5.. 7 Command */
57 uint8_t reg; /*!< Type used for register access */
65 uint8_t :1; /*!< bit: 0 Reserved */
66 uint8_t LUPD:1; /*!< bit: 1 Lock Update */
67 uint8_t :3; /*!< bit: 2.. 4 Reserved */
68 uint8_t CMD:3; /*!< bit: 5.. 7 Command */
70 uint8_t reg; /*!< Type used for register access */
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Dpm_component_fixup_pic32cxsg.h14 uint8_t :2; /*!< bit: 0.. 1 Reserved */
15 uint8_t IORET:1; /*!< bit: 2 I/O Retention */
16 uint8_t :5; /*!< bit: 3.. 7 Reserved */
18 uint8_t reg; /*!< Type used for register access */
26 uint8_t SLEEPMODE:3; /*!< bit: 0.. 2 Sleep Mode */
27 uint8_t :5; /*!< bit: 3.. 7 Reserved */
29 uint8_t reg; /*!< Type used for register access */
37 uint8_t SLEEPRDY:1; /*!< bit: 0 Sleep Mode Entry Ready Enable */
38 uint8_t :7; /*!< bit: 1.. 7 Reserved */
40 uint8_t reg; /*!< Type used for register access */
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Dadc_component_fixup_pic32cxsg.h33 uint8_t FLUSHEI:1; /*!< bit: 0 Flush Event Input Enable */
34 uint8_t STARTEI:1; /*!< bit: 1 Start Conversion Event Input Enable */
35 uint8_t FLUSHINV:1; /*!< bit: 2 Flush Event Invert Enable */
36 uint8_t STARTINV:1; /*!< bit: 3 Start Conversion Event Invert Enable */
37 uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
38 uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
39 uint8_t :2; /*!< bit: 6.. 7 Reserved */
41 uint8_t reg; /*!< Type used for register access */
49 uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
50 uint8_t :7; /*!< bit: 1.. 7 Reserved */
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/hal_microchip-latest/mpfs/drivers/mss/mss_usb/
Dmss_usb_host.h485 uint8_t (*usbh_class_allocate)(uint8_t tdev_addr);
486 uint8_t (*usbh_class_release)(uint8_t tdev_addr);
487 uint8_t (*usbh_class_cep_xfr_done)(uint8_t tdev_addr,
488 uint8_t status,
491 uint8_t (*usbh_class_tx_done)(uint8_t tdev_addr,
492 uint8_t status,
495 uint8_t (*usbh_class_rx_done)(uint8_t tdev_addr,
496 uint8_t status,
499 uint8_t (*usbh_class_sof)(uint32_t frame_number);
552 uint8_t addr;
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Dmss_usb_device_msd.h251 uint8_t (*media_init)(uint8_t lun);
252 uint8_t (*media_get_capacity)(uint8_t lun,
256 uint8_t (*media_is_ready)(uint8_t lun);
257 uint8_t (*media_is_write_protected)(uint8_t lun);
258 uint32_t(*media_read)(uint8_t lun,
259 uint8_t **buf,
263 uint8_t*(*media_acquire_write_buf)(uint8_t lun,
267 uint32_t(*media_write_ready)(uint8_t lun,
271 uint8_t (*media_get_max_lun)(void);
272 uint8_t*(*media_inquiry)(uint8_t lun, uint32_t *len);
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Dmss_usb_core_regs.h326 volatile uint8_t TX_TYPE;
327 volatile uint8_t TX_INTERVAL;
328 volatile uint8_t RX_TYPE;
329 volatile uint8_t RX_INTERVAL;
330 volatile uint8_t RESERVED;
331 volatile uint8_t FIFO_SIZE;
336 volatile uint8_t TX_FUNC_ADDR;
337 volatile uint8_t UNUSED0;
338 volatile uint8_t TX_HUB_ADDR;
339 volatile uint8_t TX_HUB_PORT;
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Dmss_usb_device_hid.c32 static uint8_t* usbd_hid_get_descriptor_cb(uint8_t recepient,
33 uint8_t type,
37 static uint8_t usbd_hid_init_cb(uint8_t cfgidx, mss_usb_device_speed_t musb_speed);
38 static uint8_t usbd_hid_release_cb(uint8_t cfgidx);
40 static uint8_t usbd_hid_process_request_cb(mss_usbd_setup_pkt_t * setup_pkt,
41 uint8_t** buf_pp,
44 static uint8_t usbd_hid_tx_complete_cb(mss_usb_ep_num_t num, uint8_t status);
45 static uint8_t usbd_hid_rx_cb(mss_usb_ep_num_t num, uint8_t status, uint32_t rx_count);
46 static uint8_t usbd_hid_cep_tx_done_cb(uint8_t status);
47 static uint8_t usbd_hid_cep_rx_done_cb(uint8_t status);
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Dmss_usb_device.h197 extern volatile uint8_t capture_start;
241 uint8_t* (*usbd_device_descriptor)(uint32_t* length);
243 uint8_t* (*usbd_device_qual_descriptor)(mss_usb_device_speed_t speed,
246 uint8_t* (*usbd_string_descriptor)(uint8_t index, uint32_t* length);
277 uint8_t request_type;
278 uint8_t request;
368 uint8_t(*usbd_class_init)(uint8_t cfgidx, mss_usb_device_speed_t musb_speed);
369 uint8_t(*usbd_class_release)(uint8_t cfgidx);
371 uint8_t*(*usbd_class_get_descriptor)(uint8_t recepient,
372 uint8_t type,
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Dmss_usb_common_cif.h222 uint8_t dpb_enable; /*0 or 1*/
225 uint8_t dma_enable;
229 uint8_t stall;
240 uint8_t num_usb_pkt;
241 uint8_t* buf_addr;
268 uint8_t cep_data_dir;
269 uint8_t* cep_cmd_addr;
270 uint8_t disable_ping; /*Depends on target speed*/
280 uint8_t tdev_idx;
291 uint8_t device_addr;
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Dmss_usb_host_hid.c72 uint8_t bLength;
73 uint8_t bDescriptorType;
76 uint8_t bCountryCode; /* specifies the transfer type. */
77 uint8_t bNumDescriptors; /* specifies the transfer type. */
78 uint8_t bReportDescriptorType;/* Maximum Packet Size this endpoint is
88 uint8_t g_hid_report[50] = {0};
89 volatile uint8_t toggle_in = 0;
91 volatile uint8_t next = 0;
92 volatile uint8_t USBH_HID_RX_buffer[10] = {0x00};
98 uint8_t num;
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/hal_microchip-latest/mec5/drivers/
Dmec_espi_vw.h94 uint8_t host_idx;
95 uint8_t reset_src;
96 uint8_t reset_val_bm;
97 uint8_t src_val_bm;
98 uint8_t src_irq_sel[4];
161 int mec_hal_espi_vw_ct_girq_ctrl(uint8_t ct_idx, uint8_t src_idx, uint8_t enable);
162 void mec_hal_espi_vw_ct_girq_ctrl_all(uint8_t enable);
163 int mec_hal_espi_vw_ct_girq_clr(uint8_t ct_idx, uint8_t src_idx);
164 int mec_hal_espi_vw_ct_girq_clr_msk(uint8_t ct_idx, uint8_t clr_msk);
166 uint32_t mec_hal_espi_vw_ct_girq_sts(uint8_t ct_idx, uint8_t src_idx);
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/hal_microchip-latest/mpfs/drivers/mss/mss_mmuart/
Dmss_uart.h378 #define MSS_UART_DATA_5_BITS ((uint8_t) 0x00)
379 #define MSS_UART_DATA_6_BITS ((uint8_t) 0x01)
380 #define MSS_UART_DATA_7_BITS ((uint8_t) 0x02)
381 #define MSS_UART_DATA_8_BITS ((uint8_t) 0x03)
398 #define MSS_UART_NO_PARITY ((uint8_t) 0x00)
399 #define MSS_UART_ODD_PARITY ((uint8_t) 0x08)
400 #define MSS_UART_EVEN_PARITY ((uint8_t) 0x18)
401 #define MSS_UART_STICK_PARITY_0 ((uint8_t) 0x38)
402 #define MSS_UART_STICK_PARITY_1 ((uint8_t) 0x28)
417 #define MSS_UART_ONE_STOP_BIT ((uint8_t) 0x00)
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/hal_microchip-latest/mpfs/drivers/mss/mss_i2c/
Dmss_i2c_regs.h20 #define CR0 (uint8_t)0u
21 #define CR1 (uint8_t)1u
22 #define AA (uint8_t)2u
23 #define SI (uint8_t)3u
24 #define STO (uint8_t)4u
25 #define STA (uint8_t)5u
26 #define ENS1 (uint8_t)6u
27 #define CR2 (uint8_t)7u
29 #define CR0_MASK (uint8_t)(0x01)
30 #define CR1_MASK (uint8_t)(0x02)
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Dmss_i2c.h520 …ndler_ret_t (*mss_i2c_slave_wr_handler_t)( mss_i2c_instance_t *instance, uint8_t * data, uint16_t …
524 volatile uint8_t CTRL;
525 uint8_t RESERVED0;
527 uint8_t STATUS;
528 uint8_t RESERVED2;
530 volatile uint8_t DATA;
531 uint8_t RESERVED4;
533 volatile uint8_t ADDR;
534 uint8_t RESERVED6;
536 volatile uint8_t SMBUS;
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/hal_microchip-latest/mpfs/drivers/fpga_ip/CoreSysServices_PF/
Dcore_sysservices_pf.h642 uint8_t
645 const uint8_t * p_serial_number,
671 uint8_t
674 const uint8_t * p_user_code,
710 uint8_t
713 const uint8_t * p_design_info,
746 uint8_t
749 const uint8_t * p_device_certificate,
774 uint8_t SYS_read_digest
776 const uint8_t * p_digest,
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Dcore_sysservices_pf.c16 #define NULL_BUFFER (( uint8_t* ) 0)
18 static uint8_t execute_ss_command
20 uint8_t cmd_opcode,
21 const uint8_t* cmd_data,
23 const uint8_t* p_response,
48 uint8_t
51 const uint8_t * p_serial_number, in SYS_get_serial_number()
55 uint8_t status = SYS_PARAM_ERR; in SYS_get_serial_number()
77 uint8_t
80 const uint8_t * p_user_code, in SYS_get_user_code()
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/hal_microchip-latest/mpfs/drivers/mss/mss_ethernet_mac/
Dvsc8662_phy.c42 MSS_MAC_write_phy_reg(this_mac, (uint8_t)(phy_base_address + 2), 31, 0x0000U); in vsc8662_post_reset_step_01()
43 MSS_MAC_write_phy_reg(this_mac, (uint8_t)(phy_base_address + 2), 0, 0x0800U); in vsc8662_post_reset_step_01()
44 MSS_MAC_write_phy_reg(this_mac, (uint8_t)(phy_base_address + 3), 31, 0x0000U); in vsc8662_post_reset_step_01()
45 MSS_MAC_write_phy_reg(this_mac, (uint8_t)(phy_base_address + 3), 0, 0x0800U); in vsc8662_post_reset_step_01()
58 MSS_MAC_write_phy_reg(this_mac, (uint8_t)(phy_base_address), 31, 0x0000U); in vsc8662_enable_bcast_writes()
59 temp_reg = MSS_MAC_read_phy_reg(this_mac, (uint8_t)(phy_base_address), 22); in vsc8662_enable_bcast_writes()
61 MSS_MAC_write_phy_reg(this_mac, (uint8_t)(phy_base_address), 22, temp_reg); in vsc8662_enable_bcast_writes()
74 MSS_MAC_write_phy_reg(this_mac, (uint8_t)(phy_base_address), 31, 0x0000U); in vsc8662_disable_bcast_writes()
75 temp_reg = MSS_MAC_read_phy_reg(this_mac, (uint8_t)(phy_base_address), 22); in vsc8662_disable_bcast_writes()
77 MSS_MAC_write_phy_reg(this_mac, (uint8_t)(phy_base_address), 22, temp_reg); in vsc8662_disable_bcast_writes()
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/hal_microchip-latest/mpfs/drivers/mss/mss_sys_services/
Dmss_sys_services.h946 uint8_t sys_service_mode,
986 uint8_t * p_serial_number,
1029 uint8_t * p_user_code,
1081 uint8_t * p_design_info,
1123 uint8_t * p_device_certificate,
1165 uint8_t * p_digest,
1207 uint8_t * p_security_locks,
1249 uint8_t * p_debug_info,
1294 uint8_t * p_envm_param,
1497 uint8_t * p_challenge,
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Dmss_sys_services.c22 #define NULL_BUFFER (( uint8_t* ) 0)
41 volatile uint8_t g_message_received = 0u;
42 uint8_t g_service_mode = 0u;
44 uint8_t* gp_int_service_response;
48 volatile uint8_t g_message_interrupt_counter = 0u;
60 uint8_t cmd_opcode,
61 uint8_t* cmd_data,
63 uint8_t* p_response,
71 uint8_t cmd_opcode,
72 uint8_t* cmd_data,
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