| /hal_microchip-latest/pic32c/pic32cxsg/include/fixups/component/ |
| D | sdhc_component_fixup_pic32cxsg.h | 27 uint16_t BLOCKSIZE:10; /*!< bit: 0.. 9 Transfer Block Size */
28 uint16_t :2; /*!< bit: 10..11 Reserved */
29 uint16_t BOUNDARY:3; /*!< bit: 12..14 SDMA Buffer Boundary */
30 uint16_t :1; /*!< bit: 15 Reserved */
32 uint16_t reg; /*!< Type used for register access */
40 uint16_t BCNT:16; /*!< bit: 0..15 Blocks Count for Current Transfer */
42 uint16_t reg; /*!< Type used for register access */
60 uint16_t DMAEN:1; /*!< bit: 0 DMA Enable */
61 uint16_t BCEN:1; /*!< bit: 1 Block Count Enable */
62 uint16_t ACMDEN:2; /*!< bit: 2.. 3 Auto Command Enable */
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| D | rtc_component_fixup_pic32cxsg.h | 14 uint16_t SWRST:1; /*!< bit: 0 Software Reset */
15 uint16_t ENABLE:1; /*!< bit: 1 Enable */
16 uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
17 uint16_t :3; /*!< bit: 4.. 6 Reserved */
18 uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
19 uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
20 uint16_t :1; /*!< bit: 12 Reserved */
21 uint16_t BKTRST:1; /*!< bit: 13 BKUP Registers Reset On Tamper Enable */
22 uint16_t GPTRST:1; /*!< bit: 14 GP Registers Reset On Tamper Enable */
23 uint16_t COUNTSYNC:1; /*!< bit: 15 Count Read Synchronization Enable */
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| D | i2s_component_fixup_pic32cxsg.h | 60 uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
61 uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
62 uint16_t :2; /*!< bit: 2.. 3 Reserved */
63 uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
64 uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
65 uint16_t :2; /*!< bit: 6.. 7 Reserved */
66 uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
67 uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
68 uint16_t :2; /*!< bit: 10..11 Reserved */
69 uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
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| D | nvmctrl_component_fixup_pic32cxsg.h | 14 uint16_t :2; /*!< bit: 0.. 1 Reserved */
15 uint16_t AUTOWS:1; /*!< bit: 2 Auto Wait State Enable */
16 uint16_t SUSPEN:1; /*!< bit: 3 Suspend Enable */
17 uint16_t WMODE:2; /*!< bit: 4.. 5 Write Mode */
18 uint16_t PRM:2; /*!< bit: 6.. 7 Power Reduction Mode during Sleep */
19 uint16_t RWS:4; /*!< bit: 8..11 NVM Read Wait States */
20 …uint16_t AHBNS0:1; /*!< bit: 12 Force AHB0 access to NONSEQ, burst transfers are cont…
21 …uint16_t AHBNS1:1; /*!< bit: 13 Force AHB1 access to NONSEQ, burst transfers are cont…
22 uint16_t CACHEDIS0:1; /*!< bit: 14 AHB0 Cache Disable */
23 uint16_t CACHEDIS1:1; /*!< bit: 15 AHB1 Cache Disable */
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| D | usb_component_fixup_pic32cxsg.h | 37 uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
38 uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
39 uint16_t :1; /*!< bit: 15 Reserved */
41 uint16_t reg; /*!< Type used for register access */
84 uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */
85 uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */
86 uint16_t :1; /*!< bit: 15 Reserved */
88 uint16_t reg; /*!< Type used for register access */
108 uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */
109 uint16_t :1; /*!< bit: 7 Reserved */
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| D | adc_component_fixup_pic32cxsg.h | 14 uint16_t SWRST:1; /*!< bit: 0 Software Reset */
15 uint16_t ENABLE:1; /*!< bit: 1 Enable */
16 uint16_t :1; /*!< bit: 2 Reserved */
17 uint16_t DUALSEL:2; /*!< bit: 3.. 4 Dual Mode Trigger Selection */
18 uint16_t SLAVEEN:1; /*!< bit: 5 Slave Enable */
19 uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
20 uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
21 uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */
22 uint16_t :4; /*!< bit: 11..14 Reserved */
23 uint16_t R2R:1; /*!< bit: 15 Rail to Rail Operation Enable */
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| D | pdec_component_fixup_pic32cxsg.h | 78 uint16_t EVACT:2; /*!< bit: 0.. 1 Event Action */
79 uint16_t EVINV:3; /*!< bit: 2.. 4 Inverted Event Input Enable */
80 uint16_t EVEI:3; /*!< bit: 5.. 7 Event Input Enable */
81 uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */
82 uint16_t ERREO:1; /*!< bit: 9 Error Output Event Enable */
83 uint16_t DIREO:1; /*!< bit: 10 Direction Output Event Enable */
84 uint16_t VLCEO:1; /*!< bit: 11 Velocity Output Event Enable */
85 uint16_t MCEO0:1; /*!< bit: 12 Match Channel 0 Event Output Enable */
86 uint16_t MCEO1:1; /*!< bit: 13 Match Channel 1 Event Output Enable */
87 uint16_t :2; /*!< bit: 14..15 Reserved */
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| D | ac_component_fixup_pic32cxsg.h | 42 uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */
43 uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */
44 uint16_t :2; /*!< bit: 2.. 3 Reserved */
45 uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */
46 uint16_t :3; /*!< bit: 5.. 7 Reserved */
47 uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input Enable */
48 uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input Enable */
49 uint16_t :2; /*!< bit: 10..11 Reserved */
50 uint16_t INVEI0:1; /*!< bit: 12 Comparator 0 Input Event Invert Enable */
51 uint16_t INVEI1:1; /*!< bit: 13 Comparator 1 Input Event Invert Enable */
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| D | dmac_component_fixup_pic32cxsg.h | 14 uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */
15 uint16_t EVOSEL:2; /*!< bit: 1.. 2 Block Event Output Selection */
16 uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */
17 uint16_t :3; /*!< bit: 5.. 7 Reserved */
18 uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */
19 uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */
20 uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */
21 uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */
22 uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */
24 uint16_t reg; /*!< Type used for register access */
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| D | osc32kctrl_component_fixup_pic32cxsg.h | 78 uint16_t :1; /*!< bit: 0 Reserved */
79 uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
80 uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
81 uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */
82 uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */
83 uint16_t :1; /*!< bit: 5 Reserved */
84 uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
85 uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
86 uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
87 uint16_t :1; /*!< bit: 11 Reserved */
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| D | tcc_component_fixup_pic32cxsg.h | 436 uint16_t PGE0:1; /*!< bit: 0 Pattern Generator 0 Output Enable */
437 uint16_t PGE1:1; /*!< bit: 1 Pattern Generator 1 Output Enable */
438 uint16_t PGE2:1; /*!< bit: 2 Pattern Generator 2 Output Enable */
439 uint16_t PGE3:1; /*!< bit: 3 Pattern Generator 3 Output Enable */
440 uint16_t PGE4:1; /*!< bit: 4 Pattern Generator 4 Output Enable */
441 uint16_t PGE5:1; /*!< bit: 5 Pattern Generator 5 Output Enable */
442 uint16_t PGE6:1; /*!< bit: 6 Pattern Generator 6 Output Enable */
443 uint16_t PGE7:1; /*!< bit: 7 Pattern Generator 7 Output Enable */
444 uint16_t PGV0:1; /*!< bit: 8 Pattern Generator 0 Output Value */
445 uint16_t PGV1:1; /*!< bit: 9 Pattern Generator 1 Output Value */
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| D | dac_component_fixup_pic32cxsg.h | 171 uint16_t LEFTADJ:1; /*!< bit: 0 Left Adjusted Data */
172 uint16_t ENABLE:1; /*!< bit: 1 Enable DAC0 */
173 uint16_t CCTRL:2; /*!< bit: 2.. 3 Current Control */
174 uint16_t :1; /*!< bit: 4 Reserved */
175 uint16_t FEXT:1; /*!< bit: 5 Standalone Filter */
176 uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
177 uint16_t DITHER:1; /*!< bit: 7 Dithering Mode */
178 uint16_t REFRESH:4; /*!< bit: 8..11 Refresh period */
179 uint16_t :1; /*!< bit: 12 Reserved */
180 uint16_t OSR:3; /*!< bit: 13..15 Sampling Rate */
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| /hal_microchip-latest/mec/mec1501/component/ |
| D | espi_mem.h | 193 __IOM uint16_t EBAR_MBX_H0; /*! (@ 0x0000) Mailbox Logical Device BAR Internal b[15:0] */
194 __IOM uint16_t EBAR_MBX_H1; /*! (@ 0x0002) Mailbox Logical Device BAR Internal b[31:16] */
195 __IOM uint16_t EBAR_MBX_H2; /*! (@ 0x0004) Mailbox Logical Device BAR Internal b[47:32] */
196 __IOM uint16_t EBAR_MBX_H3; /*! (@ 0x0006) Mailbox Logical Device BAR Internal b[63:48] */
197 __IOM uint16_t EBAR_MBX_H4; /*! (@ 0x0008) Mailbox Logical Device BAR Internal b[79:64] */
198 __IOM uint16_t EBAR_ACPI_EC_0_H0; /*! (@ 0x000a) ACPI EC0 Logical Device BAR Internal b[15:0] */
199 __IOM uint16_t EBAR_ACPI_EC_0_H1; /*! (@ 0x000c) ACPI EC0 Logical Device BAR Internal b[31:16] */
200 __IOM uint16_t EBAR_ACPI_EC_0_H2; /*! (@ 0x000e) ACPI EC0 Logical Device BAR Internal b[47:32] */
201 __IOM uint16_t EBAR_ACPI_EC_0_H3; /*! (@ 0x0010) ACPI EC0 Logical Device BAR Internal b[63:48] */
202 __IOM uint16_t EBAR_ACPI_EC_0_H4; /*! (@ 0x0012) ACPI EC0 Logical Device BAR Internal b[79:64] */
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| /hal_microchip-latest/mpfs/drivers/mss/mss_sys_services/ |
| D | mss_sys_services.c | 45 uint16_t g_int_service_response_size;
46 uint16_t g_int_service_response_offset;
58 static uint16_t execute_ss_polling_mode
62 uint16_t cmd_data_size,
64 uint16_t response_size,
65 uint16_t mb_offset,
66 uint16_t response_offset
69 static uint16_t execute_ss_interrupt_mode
73 uint16_t cmd_data_size,
75 uint16_t response_size,
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| D | mss_sys_services.h | 911 uint16_t
983 uint16_t
987 uint16_t mb_offset
1026 uint16_t
1030 uint16_t mb_offset
1078 uint16_t
1082 uint16_t mb_offset
1120 uint16_t
1124 uint16_t mb_offset
1162 uint16_t
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| /hal_microchip-latest/mpfs/drivers/mss/mss_usb/ |
| D | mss_usb_core_regs.h | 321 volatile uint16_t TX_MAX_P;
322 volatile uint16_t TX_CSR;
323 volatile uint16_t RX_MAX_P;
324 volatile uint16_t RX_CSR;
325 volatile uint16_t RX_COUNT;
363 volatile uint16_t VALUE;
364 volatile uint16_t RESERVED;
372 volatile uint16_t TX_MAX_P;
373 volatile uint16_t CSR0;
374 volatile uint16_t RX_MAX_P;
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| D | mss_usb_host.h | 558 uint16_t tdev_maxpktsz0;
706 uint16_t bcdUSB;
711 uint16_t idVendor;
712 uint16_t idProduct;
713 uint16_t bcdDevice;
718 uint16_t reserved; /*Word alignment*/
776 uint16_t wTotalLength;
1092 uint16_t fifo_addr,
1093 uint16_t fifo_size,
1094 uint16_t max_pkt_size,
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| /hal_microchip-latest/mec5/drivers/ |
| D | mec_i3c_api.h | 142 uint16_t data_len;
166 uint16_t DAT_start;
186 uint16_t data_len;
190 uint16_t rem_data_len;
236 uint16_t *max_rd_len, uint16_t *max_wr_len);
261 void MEC_HAL_I3C_DAT_info_get(struct mec_i3c_ctx *ctx, uint16_t *start_addr, uint16_t *depth);
263 void MEC_HAL_I3C_DCT_info_get(struct mec_i3c_ctx *ctx, uint16_t *start_addr, uint16_t *depth);
265 void MEC_HAL_I3C_DCT_read(struct mec_i3c_ctx *ctx, uint16_t DCT_start, uint16_t DCT_idx,
274 void MEC_HAL_I3C_DAT_DynamicAddrAssign_write(struct mec_i3c_ctx *ctx, uint16_t DAT_start,
275 uint16_t DAT_idx, uint8_t address);
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| D | mec_vbat.c | 73 int mec_hal_bbram_rd8(uint16_t byte_ofs, uint8_t *val) in mec_hal_bbram_rd8()
84 int mec_hal_bbram_wr8(uint16_t byte_ofs, uint8_t val) in mec_hal_bbram_wr8()
95 int mec_hal_bbram_rd32(uint16_t byte_ofs, uint32_t *val) in mec_hal_bbram_rd32()
106 for (uint16_t i = 0; i < 4u; i++) { in mec_hal_bbram_rd32()
117 int mec_hal_bbram_wr32(uint16_t byte_ofs, uint32_t val) in mec_hal_bbram_wr32()
126 for (uint16_t i = 0; i < 4u; i++) { in mec_hal_bbram_wr32()
135 int mec_hal_bbram_rd(uint16_t byte_ofs, uint8_t *data, size_t datasz, size_t *nread) in mec_hal_bbram_rd()
141 for (uint16_t idx = byte_ofs; idx < (uint16_t)MEC_VBAT_MEM_SIZE; idx++) { in mec_hal_bbram_rd()
155 int mec_hal_bbram_wr(uint16_t byte_ofs, uint8_t *data, size_t datasz, size_t *nwritten) in mec_hal_bbram_wr()
161 for (uint16_t idx = byte_ofs; idx < (uint16_t)MEC_VBAT_MEM_SIZE; idx++) { in mec_hal_bbram_wr()
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| /hal_microchip-latest/mpfs/drivers/mss/mss_ethernet_mac/ |
| D | vsc8541_phy.c | 101 volatile uint16_t temp_reg; in MSS_MAC_VSC8541_phy_init()
158 MSS_MAC_write_phy_reg(this_mac, phy_addr, 23, (uint16_t)(0x0000)); in MSS_MAC_VSC8541_phy_init()
172 …MSS_MAC_write_phy_reg(this_mac, phy_addr, MII_BMCR, (uint16_t)(BMCR_ANENABLE | BMCR_FULLDPLX | BMC… in MSS_MAC_VSC8541_phy_init()
175 MSS_MAC_write_phy_reg(this_mac, phy_addr, MII_ADVERTISE, (uint16_t)(ADVERTISE_FULL)); in MSS_MAC_VSC8541_phy_init()
178 MSS_MAC_write_phy_reg(this_mac, phy_addr, MII_CTRL1000, (uint16_t)(ADVERTISE_1000FULL)); in MSS_MAC_VSC8541_phy_init()
195 MSS_MAC_write_phy_reg(this_mac, phy_addr, 18, (uint16_t)(0x0084U)); in MSS_MAC_VSC8541_phy_init()
198 MSS_MAC_write_phy_reg(this_mac, phy_addr, 23, (uint16_t)(0x2880U)); in MSS_MAC_VSC8541_phy_init()
201 MSS_MAC_write_phy_reg(this_mac, phy_addr, 23, (uint16_t)(0xC050U)); in MSS_MAC_VSC8541_phy_init()
204 MSS_MAC_write_phy_reg(this_mac, phy_addr, 29, (uint16_t)(0x0123U)); in MSS_MAC_VSC8541_phy_init()
207 MSS_MAC_write_phy_reg(this_mac, phy_addr, 30, (uint16_t)(0x0000U)); in MSS_MAC_VSC8541_phy_init()
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| D | vsc8662_phy.c | 55 uint16_t temp_reg; in vsc8662_enable_bcast_writes()
71 uint16_t temp_reg; in vsc8662_disable_bcast_writes()
87 uint16_t temp_reg; in vsc8662_enable_LED_blink()
113 uint16_t temp_reg; in vsc8662_100tx_1000t_amplitude_fix()
192 temp_reg = (uint16_t)((temp_reg & 0xFFFFU) | 0x0040U); in vsc8662_100tx_1000t_amplitude_fix()
196 temp_reg = (uint16_t)((temp_reg & 0xFFFFU) | 0x0010U); in vsc8662_100tx_1000t_amplitude_fix()
209 uint16_t temp_reg; in vsc8662_10t_performance_fix()
218 temp_reg = (uint16_t)((temp_reg & 0xFFEFU) | 0x0060U); in vsc8662_10t_performance_fix()
249 uint16_t temp_reg; in MSS_MAC_VSC8662_phy_init()
250 volatile uint16_t phy_reg; in MSS_MAC_VSC8662_phy_init()
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| D | ti_dp83867_phy.c | 56 uint16_t phy_reg; in MSS_MAC_DP83867_phy_init()
97 uint16_t phy_reg; in MSS_MAC_DP83867_phy_set_link_speed()
100 const uint16_t mii_advertise_bits[4] = {ADVERTISE_10FULL, ADVERTISE_10HALF, in MSS_MAC_DP83867_phy_set_link_speed()
111 phy_reg &= (uint16_t)(~(ADVERTISE_10HALF | ADVERTISE_10FULL | in MSS_MAC_DP83867_phy_set_link_speed()
132 phy_reg &= (uint16_t)(~(ADVERTISE_1000FULL | ADVERTISE_1000HALF)); in MSS_MAC_DP83867_phy_set_link_speed()
148 uint16_t temp_reg = 0x0000U; /* Default with 10M, half duplex */ in MSS_MAC_DP83867_phy_set_link_speed()
175 …MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_CTRL1000, (uint16_t)(ADVERTISE_10… in MSS_MAC_DP83867_phy_set_link_speed()
179 …MSS_MAC_write_phy_reg(this_mac, (uint8_t)this_mac->phy_addr, MII_CTRL1000, (uint16_t)(ADVERTISE_10… in MSS_MAC_DP83867_phy_set_link_speed()
191 volatile uint16_t phy_reg; in MSS_MAC_DP83867_phy_autonegotiate()
192 uint16_t autoneg_complete; in MSS_MAC_DP83867_phy_autonegotiate()
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| /hal_microchip-latest/mpfs/drivers/fpga_ip/CoreSysServices_PF/ |
| D | core_sysservices_pf.h | 646 uint16_t mb_offset
675 uint16_t mb_offset
714 uint16_t mb_offset
750 uint16_t mb_offset
777 uint16_t mb_offset
805 uint16_t mb_offset
833 uint16_t mb_offset
870 uint16_t mb_offset
913 uint16_t mb_offset
956 uint16_t mb_offset
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| D | core_sysservices_pf.c | 22 uint16_t cmd_data_size,
24 uint16_t response_size,
25 uint16_t mb_offset,
26 uint16_t response_offset
52 uint16_t mb_offset in SYS_get_serial_number()
81 uint16_t mb_offset in SYS_get_user_code()
109 uint16_t mb_offset in SYS_get_design_info()
137 uint16_t mb_offset in SYS_get_device_certificate()
164 uint16_t mb_offset in SYS_read_digest()
202 uint16_t mb_offset in SYS_query_security()
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| /hal_microchip-latest/mpfs/drivers/mss/mss_i2c/ |
| D | mss_i2c.h | 520 …_ret_t (*mss_i2c_slave_wr_handler_t)( mss_i2c_instance_t *instance, uint8_t * data, uint16_t size);
526 uint16_t RESERVED1;
529 uint16_t RESERVED3;
532 uint16_t RESERVED5;
535 uint16_t RESERVED7;
538 uint16_t RESERVED9;
541 uint16_t RESERVED11;
544 uint16_t RESERVED13;
547 uint16_t RESERVED15;
820 uint16_t write_size,
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