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/hal_microchip-latest/mpfs/drivers/fpga_ip/CoreSysServices_PF/
Dcore_sysservices_pf.c29 uint32_t g_css_pf_base_addr = 0u;
64 0u, in SYS_get_serial_number()
68 0u); in SYS_get_serial_number()
93 0u, in SYS_get_user_code()
97 0u); in SYS_get_user_code()
121 0u, in SYS_get_design_info()
125 0u); in SYS_get_design_info()
149 0u, in SYS_get_device_certificate()
153 0u); in SYS_get_device_certificate()
177 0u, in SYS_read_digest()
[all …]
Dcoresysservicespf_regs.h21 #define SS_CMD_SHIFT 0u
30 #define SS_STAT_SHIFT 0u
40 #define SS_REQ_REQ_SHIFT 0u
68 #define MBX_ECCSTATUS_SHIFT 0u
78 #define MBX_WCNT_SHIFT 0u
87 #define MBX_RCNT_SHIFT 0u
96 #define MBX_WADDR_SHIFT 0u
105 #define MBX_RADDR_SHIFT 0u
114 #define MBX_WDATA_SHIFT 0u
124 #define MBX_RDATA_SHIFT 0u
[all …]
/hal_microchip-latest/mpfs/drivers/mss/mss_usb/
Dmss_usb_host_msc.c83 static volatile uint8_t g_usbh_msc_alloc_event = 0u;
84 static uint8_t g_usbh_msc_release_event = 0u;
85 static volatile uint8_t g_usbh_msc_cep_event = 0u;
86 static volatile uint8_t g_usbh_msc_tx_event = 0u;
87 static volatile uint8_t g_usbh_msc_rx_event = 0u;
115 static uint8_t g_msd_tdev_addr = 0u;
120 static uint32_t g_tdev_max_lun_idx = 0u;
174 g_tdev_max_lun_idx = 0u; in MSS_USBH_MSC_init()
175 memset(g_msd_conf_desc, 0u, sizeof(g_msd_conf_desc)); in MSS_USBH_MSC_init()
176 memset(g_bot_inquiry, 0u, sizeof(g_bot_inquiry)); in MSS_USBH_MSC_init()
[all …]
Dmss_usb_device_msd.c187 uint32_t g_xfr_buf_len = 0u;
188 uint32_t g_xfr_lba_addr = 0u;
340 uint8_t conf_desc_len = 0u; in usbd_msc_get_descriptor_cb()
341 uint8_t os_conf_desc_len = 0u; in usbd_msc_get_descriptor_cb()
354 os_conf_desc = 0u; in usbd_msc_get_descriptor_cb()
355 os_conf_desc_len = 0u; in usbd_msc_get_descriptor_cb()
392 ASSERT(os_conf_desc != 0u); in usbd_msc_get_descriptor_cb()
426 uint16_t bulk_rxep_fifo_sz = 0u; in usbd_msc_init_cb()
427 uint16_t bulk_rxep_maxpktsz = 0u; in usbd_msc_init_cb()
429 uint16_t bulk_txep_fifo_sz = 0u; in usbd_msc_init_cb()
[all …]
Dmss_usb_host.c109 uint8_t volatile gh_tdev_connect_event = 0u;
110 uint8_t volatile gh_tdev_discon_event = 0u;
111 uint8_t volatile gh_cep_cb_event = 0u;
159 static volatile uint8_t g_internal_cep_xfr = 0u;
227 g_tdev[TDEV_R].hub_addr = 0u; in MSS_USBH_init()
228 g_tdev[TDEV_R].hub_port = 0u; in MSS_USBH_init()
229 g_tdev[TDEV_R].hub_mtt = 0u; in MSS_USBH_init()
231 g_tdev[TDEV_R].class_handle = 0u; in MSS_USBH_init()
250 g_rcd[0].alloc_state = 0u; in MSS_USBH_register_class_driver()
273 tdev_id_t tid = (tdev_id_t)0u; in MSS_USBH_configure_control_pipe()
[all …]
Dmss_usb_host_hid.c106 static volatile uint8_t g_usbh_hid_alloc_event = 0u;
107 static volatile uint8_t g_usbh_hid_cep_event = 0u;
108 static volatile uint8_t g_usbh_hid_tx_event = 0u;
109 static volatile uint8_t g_usbh_hid_rx_event = 0u;
111 static uint8_t g_hid_tdev_addr = 0u;
159 memset(g_hid_conf_desc, 0u, sizeof(g_hid_conf_desc)); in MSS_USBH_HID_init()
160 g_tdev_in_ep.maxpktsz = 0u; in MSS_USBH_HID_init()
161 g_tdev_in_ep.num = 0u; in MSS_USBH_HID_init()
162 g_hid_tdev_addr = 0u; in MSS_USBH_HID_init()
188 static volatile uint32_t wait_mili = 0u; in MSS_USBH_HID_task()
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Dmss_usb_device.c285 cep_ptr->stall = 0u; in MSS_USBD_cep_configure()
290 cep_ptr->buf_addr = 0u; in MSS_USBD_cep_configure()
312 cep_ptr->xfr_count = 0u; in MSS_USBD_cep_read_prepare()
313 cep_ptr->txn_count = 0u; in MSS_USBD_cep_read_prepare()
341 cep_ptr->xfr_count = 0u; in MSS_USBD_cep_write()
342 cep_ptr->txn_count = 0u; in MSS_USBD_cep_write()
441 txep_ptr->stall = 0u; in MSS_USBD_tx_ep_configure()
444 txep_ptr->buf_addr = 0u; in MSS_USBD_tx_ep_configure()
535 rxep_ptr->stall = 0u; in MSS_USBD_rx_ep_configure()
538 rxep_ptr->buf_addr = 0u; in MSS_USBD_rx_ep_configure()
[all …]
/hal_microchip-latest/mpfs/drivers/mss/mss_mmuart/
Dmss_uart_regs.h30 #define RXRDY_TXRDYN_EN 0u /* Enable TXRDY and RXRDY signals */
36 #define RXRDY_TXRDYN_EN_MASK (0x01u << 0u) /* Enable TXRDY and RXRDY signals */
52 #define DR 0u /* Data ready */
57 #define DR_MASK (0x01u << 0u) /* Data ready */
62 #define ERBFI 0u /* Enable receiver buffer full interrupt */
68 #define ERBFI_MASK (0x01u << 0u) /* Enable receiver buffer full interrupt */
86 #define E_MSB_RX 0u /* MSB / LSB first for receiver */
94 #define E_MSB_RX_MASK (0x01u << 0u) /* MSB / LSB first for receiver */
102 #define EERR 0u /* Enable ERR / NACK during stop time */
108 #define EERR_MASK (0x01u << 0u) /* Enable ERR / NACK during stop time */
[all …]
Dmss_uart.c59 #define TX_COMPLETE 0u
66 #define INVALID_INTERRUPT 0u
242 uint32_t char_idx = 0u; in MSS_UART_polled_tx()
248 ASSERT(tx_size > 0u); in MSS_UART_polled_tx()
250 if ((pbuff != ((uint8_t*)0)) && (temp_tx_size > 0u)) in MSS_UART_polled_tx()
273 for (size_sent = 0u; size_sent < fill_size; ++size_sent) in MSS_UART_polled_tx()
297 uint32_t char_idx = 0u; in MSS_UART_polled_tx_string()
313 while (0u != data_byte) in MSS_UART_polled_tx_string()
320 }while (0u == (status & MSS_UART_THRE)); in MSS_UART_polled_tx_string()
325 fill_size = 0u; in MSS_UART_polled_tx_string()
[all …]
/hal_microchip-latest/mpfs/drivers/mss/mss_pdma/
Dmss_pdma.c60 if (channel_config->src_addr == 0u) in MSS_PDMA_setup_transfer()
65 if (channel_config->dest_addr == 0u) in MSS_PDMA_setup_transfer()
203 return 0u; in MSS_PDMA_get_active_transfer_type()
223 return 0u; in MSS_PDMA_get_number_bytes_remaining()
243 return 0u; in MSS_PDMA_get_destination_current_addr()
263 return 0u; in MSS_PDMA_get_source_current_addr()
283 return 0u; in MSS_PDMA_get_transfer_complete_status()
295 return 0u; in MSS_PDMA_get_transfer_complete_status()
310 return 0u; in MSS_PDMA_get_transfer_error_status()
322 return 0u; in MSS_PDMA_get_transfer_error_status()
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/hal_microchip-latest/mpfs/drivers/mss/mss_spi/
Dmss_spi.c115 static uint8_t g_spi_axi_pos = 0u;
148 for (slave = 0u; slave < (uint16_t)MSS_SPI_MAX_NB_OF_SLAVES; slave++) in MSS_SPI_init()
220 this_spi->hw_reg->FRAMESUP = 0u; in MSS_SPI_configure_slave_mode()
253 ASSERT(0u == (clk_div & 0x00000001U)); in MSS_SPI_configure_master_mode()
406 this_spi->hw_reg->FRAMESUP = 0u; in MSS_SPI_transfer_frame()
419 while (0u == tx_done) in MSS_SPI_transfer_frame()
427 while (0u == rx_ready) in MSS_SPI_transfer_frame()
449 uint32_t transfer_idx = 0u; in MSS_SPI_transfer_block()
454 uint32_t transit = 0u; in MSS_SPI_transfer_block()
472 if (0u == transfer_size) in MSS_SPI_transfer_block()
[all …]
/hal_microchip-latest/mpfs/drivers/mss/mss_qspi/
Dmss_qspi.c21 static volatile uint32_t g_irq_rd_byte_size = 0u;
22 static volatile uint8_t g_rx_complete = 0u;
104 uint32_t words = 0u; in MSS_QSPI_polled_transfer_block()
109 QSPI->INTENABLE = 0u; in MSS_QSPI_polled_transfer_block()
111 while ((QSPI->STATUS & STTS_READY_MASK) == 0u){}; in MSS_QSPI_polled_transfer_block()
121 skips |= (((QSPI->CONTROL & CTRL_QMODE12_MASK)? 1u:0u) << FRMS_QSPI); in MSS_QSPI_polled_transfer_block()
131 for (idx = 0u; idx < words; ++idx) in MSS_QSPI_polled_transfer_block()
156 for (idx = 0u; idx < words; ++idx) in MSS_QSPI_polled_transfer_block()
171 while (0u == (QSPI->STATUS & STTS_RDONE_MASK)) in MSS_QSPI_polled_transfer_block()
198 uint8_t returnval = 0u; in MSS_QSPI_irq_transfer_block()
[all …]
Dmss_qspi_regs.h20 #define CTRL_EN 0u
44 #define FRMS_TBYTES 0u
58 #define INTE_TDONE 0u
73 #define STTS_TDONE 0u
92 #define RDAT 0u
96 #define TDAT 0u
100 #define X4RDAT 0u
104 #define X4TDAT 0u
108 #define DIRECT_EN_SSEL 0u
135 #define UADDAR 0u
/hal_microchip-latest/mpfs/drivers/mss/mss_mmc/
Dmss_mmc_types.h28 #define MMC_CMD_0_GO_IDLE_STATE 0u /* No Rsp */
73 MSS_MMC_RESPONSE_NO_RESP = 0u,
89 MSS_MMC_ACCESS_MODE_SDR12 = 0u,
118 MSS_MMC_PHY_DELAY_INPUT_HIGH_SPEED = 0u,
156 MSS_MMC_CCCR_SDIO_REV = 0u,
204 MSS_MMC_FBR_STD_SDIO_FN = 0u,
217 MSS_MMC_TUPLE_CISTPL_NULL = 0u,
/hal_microchip-latest/mec/mec1501/component/
Dtimer.h90 #define MCHP_BTMR_STS_ACTIVE_POS 0u
98 #define MCHP_BTMR_INTEN_POS 0u
100 #define MCHP_BTMR_INTDIS 0u
126 #define MCHP_BTMR_CTRL_ENABLE_POS 0u
135 #define MCHP_B16TMR0_GIRQ_POS 0u
197 #define MCHP_HTMR_CTRL_RESOL_POS 0u
199 #define MCHP_HTMR_CTRL_RESOL_30US (0u << (MCHP_HTMR_CTRL_EN_POS))
208 #define MCHP_HTMR_CNT_STOP_VALUE 0u
255 #define MCHP_CCT_CTRL_TCLK_DIV_1 (0u)
338 #define MCHP_RTMR_CTRL_BLK_EN_POS 0u
[all …]
Dport92.h51 #define MCHP_PORT92_HOST_ALT_CPU_RST_POS 0u
60 #define MCHP_PORT92_GA20_CTRL_VAL_POS 0u
63 #define MCHP_PORT92_GA20_CTRL_VAL_LO (0u << 0)
70 #define MCHP_PORT92_SETGA20L_SET_POS 0u
78 #define MCHP_PORT92_RSTGA20L_SET_POS 0u
Despi_io.h112 #define MCHP_ESPI_GBL_CAP1_MAX_FREQ_POS 0u
123 (0u << (MCHP_ESPI_GBL_CAP1_ALERT_POS))
129 #define MCHP_ESPI_GBL_CAP1_IO_MODE0_1 0u
219 #define MCHP_ESPI_RST_ISTS_POS 0u
260 #define MCHP_ESPI_VW_ERR_STS_FATAL_POS 0u
331 #define MCHP_ESPI_PC_LC_LEN_POS 0u
386 #define MCHP_ESPI_LTR_STS_TX_DONE_POS 0u
395 #define MCHP_ESPI_LTR_IEN_TX_DONE_POS 0u
398 #define MCHP_ESPI_LTR_CTRL_START_POS 0u
404 #define MCHP_ESPI_LTR_MSG_VAL_POS 0u
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Dacpi_ec.h106 #define MCHP_ACPI_EC_STS_OBF_POS 0u
126 #define MCHP_ACPI_EC_BYTE_CTRL_4B_POS 0u
177 #define MCHP_ACPI_PM1_RT_STS1_REG_OFS 0u
179 #define MCHP_ACPI_PM1_STS1_REG_MASK 0u
194 #define MCHP_ACPI_PM1_EN1_REG_MASK 0u
207 #define MCHP_ACPI_PM1_CTRL1_REG_MASK 0u
221 #define MCHP_ACPI_PM1_CTRL21_REG_MASK 0u
226 #define MCHP_ACPI_PM1_CTRL22_REG_MASK 0u
Dtfdp.h51 #define MCHP_TFDP_CTRL_EN_POS 0u
58 #define MCHP_TFDP_OUT_ON_RISING_EDGE (0u << 1)
60 #define MCHP_TFDP_CLK_AHB_DIV_2 (0u << 2)
66 #define MCHP_TFDP_IP_DLY_1 (0u << 4)
Dqmspi.h73 #define MCHP_QMSPI_SPI_MODE0 0u
89 #define MCHP_QMSPI_M_ACT_SRST_OFS 0u
131 #define MCHP_QMSPI_M_CPHA_MOSI_CE1 (0u << 9)
137 #define MCHP_QMSPI_M_CPHA_MISO_CE1 0u
182 #define MCHP_QMSPI_C_RX_DIS (0u << MCHP_QMSPI_C_RX_POS)
191 #define MCHP_QMSPI_C_NO_CLOSE (0u << MCHP_QMSPI_C_CLOSE_POS)
203 #define MCHP_QMSPI_C_DESCR0 (0u << MCHP_QMSPI_C_NEXT_DESCR_POS)
273 #define MCHP_QMSPI_TX_BUF_CNT_STS_POS 0u
292 #define MCHP_QMSPI_TX_BUF_CNT_TRIG_POS 0u
298 #define MCHP_QMSPI_DLY_CS_ON_CK_STR_POS 0u
[all …]
Despi_vw.h43 #define ESPI_M2SW0_OFS 0u
49 #define ESPI_M2SW0_MTOS_SRC_ESPI_RST ((0u) << (ESPI_VW_M2S_MTOS_SRC_POS))
116 #define ESPI_S2MW0_STOM_SRC_ESPI_RST ((0u) << (ESPI_S2MW0_STOM_SRC_POS))
140 #define ESPI_S2MW1_SRC0_POS 0u
176 #define MEC_ESPI_MSVW00_SRC0_POS 0u
237 #define MEC_ESPI_MSVW07_SRC0_POS 0u
272 #define MSVW_INDEX_OFS 0u
284 #define SMVW_INDEX_OFS 0u
307 #define MEC_MSVW_SRC0_IRQ_SEL_POS 0u
331 #define MEC_MSVW_SRC0_POS 0u
[all …]
/hal_microchip-latest/mpfs/drivers/mss/mss_i2c/
Dmss_i2c.c22 #define WRITE_DIR 0u
26 #define NO_TRANSACTION 0u
189 this_i2c->master_tx_idx = 0u; in MSS_I2C_write()
262 this_i2c->master_rx_idx = 0u; in MSS_I2C_read()
313 ASSERT(offset_size > 0u); in MSS_I2C_write_read()
315 ASSERT(read_size > 0u); in MSS_I2C_write_read()
318 if ((read_size > 0u) && (offset_size > 0u)) in MSS_I2C_write_read()
344 this_i2c->master_tx_idx = 0u; in MSS_I2C_write_read()
348 this_i2c->master_rx_idx = 0u; in MSS_I2C_write_read()
480 this_i2c->slave_tx_idx = 0u; in MSS_I2C_set_slave_tx_buffer()
[all …]
/hal_microchip-latest/mpfs/drivers/mss/mss_rtc/
Dmss_rtc.c123 mss_rtc->MODE_REG = 0u; in MSS_RTC_init()
127 mss_rtc->ALARM_LOWER_REG = 0u; in MSS_RTC_init()
128 mss_rtc->ALARM_UPPER_REG = 0u; in MSS_RTC_init()
129 mss_rtc->COMPARE_LOWER_REG = 0u; in MSS_RTC_init()
130 mss_rtc->COMPARE_UPPER_REG = 0u; in MSS_RTC_init()
149 uint8_t error = 0u; in MSS_RTC_set_calendar_count()
168 0u, /* Seconds */ in MSS_RTC_set_calendar_count()
169 0u, /* Minutes */ in MSS_RTC_set_calendar_count()
170 0u, /* Hours */ in MSS_RTC_set_calendar_count()
173 0u, /* Years */ in MSS_RTC_set_calendar_count()
[all …]
/hal_microchip-latest/mpfs/drivers/mss/mss_can/
Dmss_can.c34 #define DISABLE 0u
76 canrxobj.ID = 0u; in MSS_CAN_init()
77 canrxobj.DATAHIGH = 0u; in MSS_CAN_init()
78 canrxobj.DATALOW = 0u; in MSS_CAN_init()
79 canrxobj.AMR.L = 0u; in MSS_CAN_init()
80 canrxobj.ACR.L = 0u; in MSS_CAN_init()
81 canrxobj.AMR_D = 0u; in MSS_CAN_init()
82 canrxobj.ACR_D = 0u; in MSS_CAN_init()
83 canrxobj.RXB.L = (0u | CAN_RX_WPNH_EBL | CAN_RX_WPNL_EBL); in MSS_CAN_init()
85 for (mailbox_number = 0u; mailbox_number < CAN_RX_MAILBOX; mailbox_number++) in MSS_CAN_init()
[all …]
/hal_microchip-latest/mpfs/drivers/mss/mss_sys_services/
Dmss_sys_services.c31 #define MSS_SYS_COMMON_RET_OFFSET 0u
41 volatile uint8_t g_message_received = 0u;
42 uint8_t g_service_mode = 0u;
48 volatile uint8_t g_message_interrupt_counter = 0u;
377 for (idx = 0u; idx < MSS_SYS_QUERY_SECURITY_RESP_LEN; idx++) in MSS_SYS_query_security()
490 uint8_t index = 0u; in MSS_SYS_puf_emulation_service()
650 for (index = 0u; index < (MSS_SYS_AUTHENTICATED_TEXT_DATA_LEN in MSS_SYS_secure_nvm_write()
658 for (index = 0u; index < MSS_SYS_USER_SECRET_KEY_LEN; index++) in MSS_SYS_secure_nvm_write()
690 for (index = 0u; index < (MSS_SYS_NON_AUTHENTICATED_TEXT_DATA_LEN - 4u); in MSS_SYS_secure_nvm_write()
741 uint16_t index = 0u; in MSS_SYS_secure_nvm_read()
[all …]

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